include/asm-mips/mach-generic/ide.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994-1996  Linus Torvalds & authors
   7  *
   8  * Copied from i386; many of the especially older MIPS or ISA-based platforms
   9  * are basically identical.  Using this file probably implies i8259 PIC
  10  * support in a system but the very least interrupt numbers 0 - 15 need to
  11  * be put aside for legacy devices.
  12  */
  13 #ifndef __ASM_MACH_GENERIC_IDE_H
  14 #define __ASM_MACH_GENERIC_IDE_H
  15
  16 #ifdef __KERNEL__
  17
  18 #include <linux/config.h>
  19 #include <linux/pci.h>
  20 #include <linux/stddef.h>
  21 #include <asm/processor.h>
  22
  23 #ifndef MAX_HWIFS
  24 # ifdef CONFIG_BLK_DEV_IDEPCI
  25 #define MAX_HWIFS       10
  26 # else
  27 #define MAX_HWIFS       6
  28 # endif
  29 #endif
  30
  31 #define IDE_ARCH_OBSOLETE_DEFAULTS
  32
  33 static __inline__ int ide_probe_legacy(void)
  34 {
  35 #ifdef CONFIG_PCI
  36         struct pci_dev *dev;
  37         if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL ||
  38             (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) {
  39                 pci_dev_put(dev);
  40
  41                 return 1;
  42         }
  43         return 0;
  44 #elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
  45         return 1;
  46 #else
  47         return 0;
  48 #endif
  49 }
  50
  51 static __inline__ int ide_default_irq(unsigned long base)
  52 {
  53         if (ide_probe_legacy())
  54                 switch (base) {
  55                 case 0x1f0:
  56                         return 14;
  57                 case 0x170:
  58                         return 15;
  59                 case 0x1e8:
  60                         return 11;
  61                 case 0x168:
  62                         return 10;
  63                 case 0x1e0:
  64                         return 8;
  65                 case 0x160:
  66                         return 12;
  67                 default:
  68                         return 0;
  69                 }
  70         else
  71                 return 0;
  72 }
  73
  74 static __inline__ unsigned long ide_default_io_base(int index)
  75 {
  76         if (ide_probe_legacy())
  77                 switch (index) {
  78                 case 0:
  79                         return 0x1f0;
  80                 case 1:
  81                         return 0x170;
  82                 case 2:
  83                         return 0x1e8;
  84                 case 3:
  85                         return 0x168;
  86                 case 4:
  87                         return 0x1e0;
  88                 case 5:
  89                         return 0x160;
  90                 default:
  91                         return 0;
  92                 }
  93         else
  94                 return 0;
  95 }
  96
  97 #define IDE_ARCH_OBSOLETE_INIT
  98 #define ide_default_io_ctl(base)        ((base) + 0x206) /* obsolete */
  99
 100 #ifdef CONFIG_BLK_DEV_IDEPCI
 101 #define ide_init_default_irq(base)      (0)
 102 #else
 103 #define ide_init_default_irq(base)      ide_default_irq(base)
 104 #endif
 105
 106 /* MIPS port and memory-mapped I/O string operations.  */
 107
 108 static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
 109 {
 110         if (cpu_has_dc_aliases) {
 111                 unsigned long end = addr + size;
 112                 for (; addr < end; addr += PAGE_SIZE)
 113                         flush_dcache_page(virt_to_page(addr));
 114         }
 115 }
 116
 117 static inline void __ide_insw(unsigned long port, void *addr,
 118         unsigned int count)
 119 {
 120         insw(port, addr, count);
 121         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 122 }
 123
 124 static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
 125 {
 126         insl(port, addr, count);
 127         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 128 }
 129
 130 static inline void __ide_outsw(unsigned long port, const void *addr,
 131         unsigned long count)
 132 {
 133         outsw(port, addr, count);
 134         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 135 }
 136
 137 static inline void __ide_outsl(unsigned long port, const void *addr,
 138         unsigned long count)
 139 {
 140         outsl(port, addr, count);
 141         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 142 }
 143
 144 static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
 145 {
 146         readsw(port, addr, count);
 147         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 148 }
 149
 150 static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
 151 {
 152         readsl(port, addr, count);
 153         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 154 }
 155
 156 static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
 157 {
 158         writesw(port, addr, count);
 159         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 160 }
 161
 162 static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
 163 {
 164         writesl(port, addr, count);
 165         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 166 }
 167
 168 /* ide_insw calls insw, not __ide_insw.  Why? */
 169 #undef insw
 170 #undef insl
 171 #undef outsw
 172 #undef outsl
 173 #define insw(port, addr, count) __ide_insw(port, addr, count)
 174 #define insl(port, addr, count) __ide_insl(port, addr, count)
 175 #define outsw(port, addr, count) __ide_outsw(port, addr, count)
 176 #define outsl(port, addr, count) __ide_outsl(port, addr, count)
 177
 178 #endif /* __KERNEL__ */
 179
 180 #endif /* __ASM_MACH_GENERIC_IDE_H */