drivers/ieee1394/csr.h

   1
   2 #ifndef _IEEE1394_CSR_H
   3 #define _IEEE1394_CSR_H
   4
   5 #ifdef CONFIG_PREEMPT
   6 #include <linux/sched.h>
   7 #endif
   8
   9 #include "csr1212.h"
  10
  11 #define CSR_REGISTER_BASE  0xfffff0000000ULL
  12
  13 /* register offsets relative to CSR_REGISTER_BASE */
  14 #define CSR_STATE_CLEAR           0x0
  15 #define CSR_STATE_SET             0x4
  16 #define CSR_NODE_IDS              0x8
  17 #define CSR_RESET_START           0xc
  18 #define CSR_SPLIT_TIMEOUT_HI      0x18
  19 #define CSR_SPLIT_TIMEOUT_LO      0x1c
  20 #define CSR_CYCLE_TIME            0x200
  21 #define CSR_BUS_TIME              0x204
  22 #define CSR_BUSY_TIMEOUT          0x210
  23 #define CSR_BUS_MANAGER_ID        0x21c
  24 #define CSR_BANDWIDTH_AVAILABLE   0x220
  25 #define CSR_CHANNELS_AVAILABLE    0x224
  26 #define CSR_CHANNELS_AVAILABLE_HI 0x224
  27 #define CSR_CHANNELS_AVAILABLE_LO 0x228
  28 #define CSR_BROADCAST_CHANNEL     0x234
  29 #define CSR_CONFIG_ROM            0x400
  30 #define CSR_CONFIG_ROM_END        0x800
  31 #define CSR_FCP_COMMAND           0xB00
  32 #define CSR_FCP_RESPONSE          0xD00
  33 #define CSR_FCP_END               0xF00
  34 #define CSR_TOPOLOGY_MAP          0x1000
  35 #define CSR_TOPOLOGY_MAP_END      0x1400
  36 #define CSR_SPEED_MAP             0x2000
  37 #define CSR_SPEED_MAP_END         0x3000
  38
  39 /* IEEE 1394 bus specific Configuration ROM Key IDs */
  40 #define IEEE1394_KV_ID_POWER_REQUIREMENTS (0x30)
  41
  42 /* IEEE 1394 Bus Inforamation Block specifics */
  43 #define CSR_BUS_INFO_SIZE (5 * sizeof(quadlet_t))
  44
  45 #define CSR_IRMC_SHIFT 31
  46 #define CSR_CMC_SHIFT  30
  47 #define CSR_ISC_SHIFT  29
  48 #define CSR_BMC_SHIFT  28
  49 #define CSR_PMC_SHIFT  27
  50 #define CSR_CYC_CLK_ACC_SHIFT 16
  51 #define CSR_MAX_REC_SHIFT 12
  52 #define CSR_MAX_ROM_SHIFT 8
  53 #define CSR_GENERATION_SHIFT 4
  54
  55 #define CSR_SET_BUS_INFO_GENERATION(csr, gen)                           \
  56         ((csr)->bus_info_data[2] =                                      \
  57                 cpu_to_be32((be32_to_cpu((csr)->bus_info_data[2]) &     \
  58                              ~(0xf << CSR_GENERATION_SHIFT)) |          \
  59                             (gen) << CSR_GENERATION_SHIFT))
  60
  61 struct csr_control {
  62         spinlock_t lock;
  63
  64         quadlet_t state;
  65         quadlet_t node_ids;
  66         quadlet_t split_timeout_hi, split_timeout_lo;
  67         unsigned long expire;   // Calculated from split_timeout
  68         quadlet_t cycle_time;
  69         quadlet_t bus_time;
  70         quadlet_t bus_manager_id;
  71         quadlet_t bandwidth_available;
  72         quadlet_t channels_available_hi, channels_available_lo;
  73         quadlet_t broadcast_channel;
  74
  75         /* Bus Info */
  76         quadlet_t guid_hi, guid_lo;
  77         u8 cyc_clk_acc;
  78         u8 max_rec;
  79         u8 max_rom;
  80         u8 generation;  /* Only use values between 0x2 and 0xf */
  81         u8 lnk_spd;
  82
  83         unsigned long gen_timestamp[16];
  84
  85         struct csr1212_csr *rom;
  86
  87         quadlet_t topology_map[256];
  88         quadlet_t speed_map[1024];
  89 };
  90
  91 extern struct csr1212_bus_ops csr_bus_ops;
  92
  93 int init_csr(void);
  94 void cleanup_csr(void);
  95
  96 #endif /* _IEEE1394_CSR_H */