PPCG 0.08.4
[ppcg.git] / gpu_array_tile.h
blobd7fcab8821e3f89211ea4c7ab1b8b2059ce9af3f
1 #ifndef GPU_ARRAY_TILE_H
2 #define GPU_ARRAY_TILE_H
4 #include <isl/aff_type.h>
5 #include <isl/map_type.h>
6 #include <isl/val.h>
8 /* The current index is such that if you add "shift",
9 * then the result is always a multiple of "stride",
10 * where "stride" may be equal to 1.
11 * Let D represent the initial tile->depth dimensions of the computed schedule.
12 * The spaces of "lb" and "shift" are of the form
14 * D -> [b]
16 struct gpu_array_bound {
17 isl_val *size;
18 isl_aff *lb;
20 isl_val *stride;
21 isl_aff *shift;
24 /* A tile of an outer array.
26 * requires_unroll is set if the schedule dimensions that are mapped
27 * to threads need to be unrolled for this (private) tile to be used.
29 * "depth" reflects the number of schedule dimensions that affect the tile.
30 * The copying into and/or out of the tile is performed at that depth.
32 * n is the dimension of the array.
33 * bound is an array of size "n" representing the lower bound
34 * and size for each index.
36 * tiling maps a tile in the global array to the corresponding
37 * shared/private memory tile and is of the form
39 * { [D[i] -> A[a]] -> T[(a + shift(i))/stride - lb(i)] }
41 * where D represents the initial "depth" dimensions
42 * of the computed schedule.
44 struct gpu_array_tile {
45 isl_ctx *ctx;
46 int requires_unroll;
47 int depth;
48 int n;
49 struct gpu_array_bound *bound;
50 isl_multi_aff *tiling;
53 struct gpu_array_tile *gpu_array_tile_create(isl_ctx *ctx, int n_index);
54 struct gpu_array_tile *gpu_array_tile_free(struct gpu_array_tile *tile);
56 __isl_give isl_val *gpu_array_tile_size(struct gpu_array_tile *tile);
58 #endif