2 * Copyright (C) 2011 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 struct ps3gpu_ctl_context_allocate
{
37 unsigned long control_handle
;
39 unsigned long driver_info_handle
;
41 unsigned long reports_handle
;
45 struct ps3gpu_ctl_context_free
{
50 enum ps3gpu_ctl_memory_type
{
51 PS3GPU_CTL_MEMORY_TYPE_VIDEO
,
52 PS3GPU_CTL_MEMORY_TYPE_GART
55 struct ps3gpu_ctl_memory_allocate
{
63 unsigned int gpu_addr
;
66 struct ps3gpu_ctl_memory_free
{
72 struct ps3gpu_ctl_setup_control
{
80 enum ps3gpu_ctl_head
{
85 enum ps3gpu_ctl_flip_mode
{
86 PS3GPU_CTL_FLIP_MODE_HSYNC
,
87 PS3GPU_CTL_FLIP_MODE_VSYNC
90 struct ps3gpu_ctl_set_flip_mode
{
97 struct ps3gpu_ctl_reset_flip_status
{
103 struct ps3gpu_ctl_flip
{
107 unsigned long offset
;
110 struct ps3gpu_ctl_display_buffer_set
{
117 unsigned long offset
;
120 struct ps3gpu_ctl_display_buffer_unset
{
126 struct ps3gpu_ctl_display_buffer_flip
{
133 struct ps3gpu_ctl_cursor_initialize
{
139 struct ps3gpu_ctl_cursor_set_image
{
143 unsigned long offset
;
146 struct ps3gpu_ctl_cursor_set_position
{
154 struct ps3gpu_ctl_cursor_enable
{
161 #define PS3GPU_CTL_CONTEXT_ALLOCATE _IOWR('G', 0, struct ps3gpu_ctl_context_allocate)
162 #define PS3GPU_CTL_CONTEXT_FREE _IOW('G', 1, struct ps3gpu_ctl_context_free)
163 #define PS3GPU_CTL_MEMORY_ALLOCATE _IOWR('G', 2, struct ps3gpu_ctl_memory_allocate)
164 #define PS3GPU_CTL_MEMORY_FREE _IOW('G', 3, struct ps3gpu_ctl_memory_free)
165 #define PS3GPU_CTL_SETUP_CONTROL _IOW('G', 4, struct ps3gpu_ctl_setup_control)
166 #define PS3GPU_CTL_SET_FLIP_MODE _IOW('G', 5, struct ps3gpu_ctl_set_flip_mode)
167 #define PS3GPU_CTL_RESET_FLIP_STATUS _IOW('G', 6, struct ps3gpu_ctl_reset_flip_status)
168 #define PS3GPU_CTL_FLIP _IOW('G', 7, struct ps3gpu_ctl_flip)
169 #define PS3GPU_CTL_DISPLAY_BUFFER_SET _IOW('G', 8, struct ps3gpu_ctl_display_buffer_set)
170 #define PS3GPU_CTL_DISPLAY_BUFFER_UNSET _IOW('G', 9, struct ps3gpu_ctl_display_buffer_unset)
171 #define PS3GPU_CTL_DISPLAY_BUFFER_FLIP _IOW('G', 10, struct ps3gpu_ctl_display_buffer_flip)
172 #define PS3GPU_CTL_CURSOR_INITIALIZE _IOW('G', 11, struct ps3gpu_ctl_cursor_initialize)
173 #define PS3GPU_CTL_CURSOR_SET_IMAGE _IOW('G', 12, struct ps3gpu_ctl_cursor_set_image)
174 #define PS3GPU_CTL_CURSOR_SET_POSITION _IOW('G', 13, struct ps3gpu_ctl_cursor_set_position)
175 #define PS3GPU_CTL_CURSOR_ENABLE _IOW('G', 14, struct ps3gpu_ctl_cursor_enable)
177 #endif /* _PS3GPU_CTL_H */