2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
54 struct ps3gpu_ctl_set_flip_mode set_flip_mode
;
55 struct ps3gpu_ctl_reset_flip_status reset_flip_status
;
56 struct ps3gpu_ctl_memory_allocate memory_allocate
;
57 struct ps3gpu_ctl_setup_control setup_control
;
58 struct ps3gpu_ctl_display_buffer_set display_buffer_set
;
60 volatile uint32_t *control
;
61 volatile uint8_t *driver_info
;
62 uint32_t *fifo
, *reset_gpu
, *db
[2];
63 unsigned long fifo_handle
, db_handle
[2];
64 unsigned int fifo_gaddr
, reset_gpu_gaddr
, db_gaddr
[2];
70 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
76 /* Create GPU context */
78 context_allocate
.vram_size
= 64; /* MB */
80 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
86 context_id
= context_allocate
.context_id
;
88 printf("context id %d\n", context_id
);
89 printf("control handle 0x%lx size %d\n",
90 context_allocate
.control_handle
, context_allocate
.control_size
);
91 printf("driver_info handle 0x%lx size %d\n",
92 context_allocate
.driver_info_handle
, context_allocate
.driver_info_size
);
94 /* Map control registers */
96 control
= mmap(NULL
, context_allocate
.control_size
,
97 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
98 if (control
== (void *) MAP_FAILED
) {
103 /* Map driver info */
105 driver_info
= mmap(NULL
, context_allocate
.driver_info_size
,
106 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.driver_info_handle
);
107 if (driver_info
== (void *) MAP_FAILED
) {
112 printf("channel id %d\n", get_channel_id(driver_info
));
113 printf("flip status %d %d\n", get_flip_status(driver_info
, 0), get_flip_status(driver_info
, 1));
117 set_flip_mode
.context_id
= context_id
;
118 set_flip_mode
.head
= PS3GPU_CTL_HEAD_A
;
119 set_flip_mode
.mode
= PS3GPU_CTL_FLIP_MODE_VSYNC
;
121 err
= ioctl(fd
, PS3GPU_CTL_SET_FLIP_MODE
, &set_flip_mode
);
127 set_flip_mode
.context_id
= context_id
;
128 set_flip_mode
.head
= PS3GPU_CTL_HEAD_B
;
129 set_flip_mode
.mode
= PS3GPU_CTL_FLIP_MODE_VSYNC
;
131 err
= ioctl(fd
, PS3GPU_CTL_SET_FLIP_MODE
, &set_flip_mode
);
137 /* Reset flip status */
139 reset_flip_status
.context_id
= context_id
;
140 reset_flip_status
.head
= PS3GPU_CTL_HEAD_A
;
142 err
= ioctl(fd
, PS3GPU_CTL_RESET_FLIP_STATUS
, &reset_flip_status
);
148 reset_flip_status
.context_id
= context_id
;
149 reset_flip_status
.head
= PS3GPU_CTL_HEAD_B
;
151 err
= ioctl(fd
, PS3GPU_CTL_RESET_FLIP_STATUS
, &reset_flip_status
);
159 memory_allocate
.context_id
= context_id
;
160 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
161 memory_allocate
.size
= 64 * 1024;
162 memory_allocate
.align
= 12;
164 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
170 fifo_handle
= memory_allocate
.handle
;
171 fifo_gaddr
= memory_allocate
.gpu_addr
;
173 printf("fifo handle 0x%lx gpu addr 0x%08x\n",
174 fifo_handle
, fifo_gaddr
);
178 fifo
= mmap(NULL
, memory_allocate
.size
,
179 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fifo_handle
);
180 if (fifo
== (void *) MAP_FAILED
) {
187 setup_control
.context_id
= context_id
;
188 setup_control
.put
= fifo_handle
;
189 setup_control
.get
= fifo_handle
;
190 setup_control
.ref
= 0xdeadbabe;
192 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
198 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
199 control
[0x10], control
[0x11], control
[0x12]);
201 /* Allocate FIFO for resetting GPU state */
203 memory_allocate
.context_id
= context_id
;
204 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
205 memory_allocate
.size
= 4 * 1024;
206 memory_allocate
.align
= 12;
208 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
214 reset_gpu_gaddr
= memory_allocate
.gpu_addr
;
216 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
217 memory_allocate
.handle
, reset_gpu_gaddr
);
219 /* Map FIFO for resetting GPU state */
221 reset_gpu
= mmap(NULL
, memory_allocate
.size
,
222 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, memory_allocate
.handle
);
223 if (reset_gpu
== (void *) MAP_FAILED
) {
228 memcpy(reset_gpu
, reset_gpu_state_3d
, reset_gpu_state_3d_size
);
232 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
233 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
234 fifo
[2] = 0xcafef00d;
236 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
238 err
= wait_fifo_idle(control
);
240 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
241 control
[0x10], control
[0x11], control
[0x12]);
242 dump_fifo(stderr
, fifo
, 0x400);
246 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
247 control
[0x10], control
[0x11], control
[0x12]);
249 /* Allocate display buffers */
251 memory_allocate
.context_id
= context_id
;
252 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
253 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
254 memory_allocate
.align
= 12;
256 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
262 db_handle
[0] = memory_allocate
.handle
;
263 db_gaddr
[0] = memory_allocate
.gpu_addr
;
265 printf("DB0 handle 0x%lx gpu addr 0x%08x\n",
266 db_handle
[0], db_gaddr
[0]);
268 db
[0] = mmap(NULL
, memory_allocate
.size
,
269 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, db_handle
[0]);
270 if (db
[0] == (void *) MAP_FAILED
) {
275 memory_allocate
.context_id
= context_id
;
276 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
277 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
278 memory_allocate
.align
= 12;
280 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
286 db_handle
[1] = memory_allocate
.handle
;
287 db_gaddr
[1] = memory_allocate
.gpu_addr
;
289 printf("DB1 handle 0x%lx gpu addr 0x%08x\n",
290 db_handle
[1], db_gaddr
[1]);
292 db
[1] = mmap(NULL
, memory_allocate
.size
,
293 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, db_handle
[1]);
294 if (db
[1] == (void *) MAP_FAILED
) {
299 /* Set display buffers */
301 display_buffer_set
.context_id
= context_id
;
302 display_buffer_set
.buffer_id
= 0;
303 display_buffer_set
.width
= DISPLAY_WIDTH
;
304 display_buffer_set
.height
= DISPLAY_HEIGHT
;
305 display_buffer_set
.pitch
= DISPLAY_PITCH
;
306 display_buffer_set
.offset
= db_handle
[0];
308 err
= ioctl(fd
, PS3GPU_CTL_DISPLAY_BUFFER_SET
, &display_buffer_set
);
314 display_buffer_set
.context_id
= context_id
;
315 display_buffer_set
.buffer_id
= 1;
316 display_buffer_set
.width
= DISPLAY_WIDTH
;
317 display_buffer_set
.height
= DISPLAY_HEIGHT
;
318 display_buffer_set
.pitch
= DISPLAY_PITCH
;
319 display_buffer_set
.offset
= db_handle
[1];
321 err
= ioctl(fd
, PS3GPU_CTL_DISPLAY_BUFFER_SET
, &display_buffer_set
);
327 const struct surface_desc surf_desc
[] = {
328 /* display buffer 0 */
330 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
331 .sd_color_off
= { db_gaddr
[0], 0, 0, 0 },
332 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
334 .sd_color_target
= 0x1,
335 .sd_depth_loc
= 0xfeed0000,
337 .sd_depth_pitch
= 64,
341 .sd_w
= DISPLAY_WIDTH
,
342 .sd_h
= DISPLAY_HEIGHT
,
344 /* display buffer 1 */
346 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
347 .sd_color_off
= { db_gaddr
[1], 0, 0, 0 },
348 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
350 .sd_color_target
= 0x1,
351 .sd_depth_loc
= 0xfeed0000,
353 .sd_depth_pitch
= 64,
357 .sd_w
= DISPLAY_WIDTH
,
358 .sd_h
= DISPLAY_HEIGHT
,
362 /* Flip display buffer 0 */
364 setup_control
.context_id
= context_id
;
365 setup_control
.put
= fifo_handle
;
366 setup_control
.get
= fifo_handle
;
367 setup_control
.ref
= 0xdeadbabe;
369 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
375 err
+= set_surface(fifo
+ err
, &surf_desc
[0]);
376 err
+= set_depth_mask(fifo
+ err
, 0x00000000);
377 err
+= set_color_mask(fifo
+ err
, 0x01010101);
378 err
+= set_color_mask_mrt(fifo
+ err
, 0x00000000);
379 err
+= set_clear_color(fifo
+ err
, 0xffffff00);
380 err
+= set_scissor(fifo
+ err
, 0, 0, 4095, 4095);
381 err
+= clear_surface(fifo
+ err
, 0x000000f1);
383 err
+= flip_display_buffer(fifo
+ err
, get_channel_id(driver_info
), 0, 0);
386 * Label with index 0 (head 0) is set by LV1 to 0x00000000 when flip is complete.
387 * Let GPU wait for it.
390 err
+= wait_label(fifo
+ err
, 0, 0x00000000);
392 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
394 err
= wait_fifo_idle(control
);
396 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
397 control
[0x10], control
[0x11], control
[0x12]);
398 dump_fifo(stderr
, fifo
, 0x400);
402 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
403 control
[0x10], control
[0x11], control
[0x12]);
407 /* Flip display buffer 1 */
409 /* Reset flip status */
411 reset_flip_status
.context_id
= context_id
;
412 reset_flip_status
.head
= PS3GPU_CTL_HEAD_A
;
414 err
= ioctl(fd
, PS3GPU_CTL_RESET_FLIP_STATUS
, &reset_flip_status
);
420 reset_flip_status
.context_id
= context_id
;
421 reset_flip_status
.head
= PS3GPU_CTL_HEAD_B
;
423 err
= ioctl(fd
, PS3GPU_CTL_RESET_FLIP_STATUS
, &reset_flip_status
);
429 setup_control
.context_id
= context_id
;
430 setup_control
.put
= fifo_handle
;
431 setup_control
.get
= fifo_handle
;
432 setup_control
.ref
= 0xdeadbabe;
434 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
440 err
+= set_surface(fifo
+ err
, &surf_desc
[1]);
441 err
+= set_depth_mask(fifo
+ err
, 0x00000000);
442 err
+= set_color_mask(fifo
+ err
, 0x01010101);
443 err
+= set_color_mask_mrt(fifo
+ err
, 0x00000000);
444 err
+= set_clear_color(fifo
+ err
, 0xff00ff00);
445 err
+= set_scissor(fifo
+ err
, 0, 0, 4095, 4095);
446 err
+= clear_surface(fifo
+ err
, 0x000000f1);
447 err
+= flip_display_buffer(fifo
+ err
, get_channel_id(driver_info
), 1, 0);
448 err
+= wait_label(fifo
+ err
, 0, 0x00000000);
450 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
452 err
= wait_fifo_idle(control
);
454 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
455 control
[0x10], control
[0x11], control
[0x12]);
456 dump_fifo(stderr
, fifo
, 0x400);
460 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
461 control
[0x10], control
[0x11], control
[0x12]);
463 /* Destroy GPU context */
465 context_free
.context_id
= context_id
;
467 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
478 /* Restore console */
480 ioctl(0, SW_TEXT_80x25
, NULL
);