2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
54 struct ps3gpu_ctl_memory_allocate memory_allocate
;
55 struct ps3gpu_ctl_setup_control setup_control
;
56 struct ps3gpu_ctl_flip flip
;
58 volatile uint32_t *control
;
59 uint32_t *fifo
, *reset_gpu
, *vram
;
60 unsigned long fifo_handle
, vram_handle
;
61 unsigned int fifo_gaddr
, reset_gpu_gaddr
, vram_gaddr
;
62 uint32_t data
[600 * 600];
70 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
76 /* Create GPU context */
78 context_allocate
.vram_size
= 64; /* MB */
80 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
86 context_id
= context_allocate
.context_id
;
88 printf("context id %d\n", context_id
);
89 printf("control handle 0x%lx size %d\n",
90 context_allocate
.control_handle
, context_allocate
.control_size
);
92 /* Map control registers */
94 control
= mmap(NULL
, context_allocate
.control_size
,
95 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
96 if (control
== (void *) MAP_FAILED
) {
103 memory_allocate
.context_id
= context_id
;
104 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
105 memory_allocate
.size
= 64 * 1024;
106 memory_allocate
.align
= 12;
108 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
114 fifo_handle
= memory_allocate
.handle
;
115 fifo_gaddr
= memory_allocate
.gpu_addr
;
117 printf("fifo handle 0x%lx gpu addr 0x08%x\n",
118 fifo_handle
, fifo_gaddr
);
122 fifo
= mmap(NULL
, memory_allocate
.size
,
123 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fifo_handle
);
124 if (fifo
== (void *) MAP_FAILED
) {
131 setup_control
.context_id
= context_id
;
132 setup_control
.put
= fifo_handle
;
133 setup_control
.get
= fifo_handle
;
134 setup_control
.ref
= 0xdeadbabe;
136 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
142 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
143 control
[0x10], control
[0x11], control
[0x12]);
145 /* Allocate FIFO for resetting GPU state */
147 memory_allocate
.context_id
= context_id
;
148 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
149 memory_allocate
.size
= 4 * 1024;
150 memory_allocate
.align
= 12;
152 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
158 reset_gpu_gaddr
= memory_allocate
.gpu_addr
;
160 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
161 memory_allocate
.handle
, reset_gpu_gaddr
);
163 /* Map FIFO for resetting GPU state */
165 reset_gpu
= mmap(NULL
, memory_allocate
.size
,
166 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, memory_allocate
.handle
);
167 if (reset_gpu
== (void *) MAP_FAILED
) {
172 memcpy(reset_gpu
, reset_gpu_state
, reset_gpu_state_size
);
176 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
177 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
178 fifo
[2] = 0xcafef00d;
180 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
182 err
= wait_fifo_idle(control
);
184 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
185 control
[0x10], control
[0x11], control
[0x12]);
186 dump_fifo(stderr
, fifo
, 0x400);
190 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
191 control
[0x10], control
[0x11], control
[0x12]);
195 memory_allocate
.context_id
= context_id
;
196 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
197 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
198 memory_allocate
.align
= 12;
200 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
206 vram_handle
= memory_allocate
.handle
;
207 vram_gaddr
= memory_allocate
.gpu_addr
;
209 printf("VRAM handle 0x%lx gpu addr 0x%08x\n",
210 vram_handle
, vram_gaddr
);
214 vram
= mmap(NULL
, memory_allocate
.size
,
215 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, vram_handle
);
216 if (vram
== (void *) MAP_FAILED
) {
221 memset32(vram
, 0xff404040, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
225 flip
.context_id
= context_id
;
226 flip
.head
= PS3GPU_CTL_HEAD_A
;
227 flip
.offset
= vram_handle
;
229 err
= ioctl(fd
, PS3GPU_CTL_FLIP
, &flip
);
235 flip
.context_id
= context_id
;
236 flip
.head
= PS3GPU_CTL_HEAD_B
;
237 flip
.offset
= vram_handle
;
239 err
= ioctl(fd
, PS3GPU_CTL_FLIP
, &flip
);
247 /* Test inline transfer */
249 setup_control
.context_id
= context_id
;
250 setup_control
.put
= fifo_handle
;
251 setup_control
.get
= fifo_handle
;
252 setup_control
.ref
= 0xdeadbabe;
254 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
263 for (y
= 0; y
< h
; y
++) {
264 for (x
= 0; x
< w
; x
++) {
266 data
[y
* w
+ x
] = 0xff00ff00;
268 data
[y
* w
+ x
] = 0xffffff00;
275 err
= transfer_inline(fifo
, 0xfeed0000,
276 vram_gaddr
+ y
* DISPLAY_PITCH
+ x
* DISPLAY_BPP
,
282 err
+= transfer_inline(fifo
+ err
, 0xfeed0000,
283 vram_gaddr
+ y
* DISPLAY_PITCH
+ x
* DISPLAY_BPP
,
286 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
288 err
= wait_fifo_idle(control
);
290 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
291 control
[0x10], control
[0x11], control
[0x12]);
292 dump_fifo(stderr
, fifo
, 0x400);
296 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
297 control
[0x10], control
[0x11], control
[0x12]);
299 save_image("image.argb", (const char *) vram
, DISPLAY_PITCH
* DISPLAY_HEIGHT
);
301 /* Destroy GPU context */
303 context_free
.context_id
= context_id
;
305 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
316 /* Restore console */
318 ioctl(0, SW_TEXT_80x25
, NULL
);