2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
55 volatile uint32_t *control
;
56 uint32_t *fifo
, *reset_gpu
, *vram
;
57 unsigned long fifo_handle
, reset_gpu_handle
, vram_handle
;
58 unsigned int fifo_gaddr
, reset_gpu_gaddr
, vram_gaddr
;
59 uint32_t data
[600 * 600];
67 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
73 /* Create GPU context */
75 context_allocate
.vram_size
= 64; /* MB */
77 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
83 context_id
= context_allocate
.context_id
;
85 printf("context id %d\n", context_id
);
86 printf("control handle 0x%lx size %d\n",
87 context_allocate
.control_handle
, context_allocate
.control_size
);
89 /* Map control registers */
91 control
= mmap(NULL
, context_allocate
.control_size
,
92 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
93 if (control
== (void *) MAP_FAILED
) {
100 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
101 64 * 1024, 12, &fifo_handle
, &fifo_gaddr
, (void **) &fifo
);
103 perror("memory_allocate");
107 printf("FIFO handle 0x%lx gpu addr 0x08%x\n",
108 fifo_handle
, fifo_gaddr
);
112 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
114 perror("setup_control");
118 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
119 control
[0x10], control
[0x11], control
[0x12]);
121 /* Allocate FIFO for resetting GPU state */
123 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
124 4 * 1024, 12, &reset_gpu_handle
, &reset_gpu_gaddr
, (void **) &reset_gpu
);
126 perror("memory_allocate");
130 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
131 reset_gpu_handle
, reset_gpu_gaddr
);
133 memcpy(reset_gpu
, reset_gpu_state
, reset_gpu_state_size
);
137 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
138 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
139 fifo
[2] = 0xcafef00d;
141 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
143 err
= wait_fifo_idle(control
);
145 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
146 control
[0x10], control
[0x11], control
[0x12]);
147 dump_fifo(stderr
, fifo
, 0x400);
151 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
152 control
[0x10], control
[0x11], control
[0x12]);
156 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_VIDEO
,
157 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
158 &vram_handle
, &vram_gaddr
, (void **) &vram
);
160 perror("memory_allocate");
164 printf("VRAM handle 0x%lx gpu addr 0x%08x\n",
165 vram_handle
, vram_gaddr
);
167 memset32(vram
, 0xff404040, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
171 err
= flip(fd
, context_id
, PS3GPU_CTL_HEAD_A
, vram_handle
);
177 err
= flip(fd
, context_id
, PS3GPU_CTL_HEAD_B
, vram_handle
);
185 /* Test inline transfer */
187 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
189 perror("setup_control");
196 for (y
= 0; y
< h
; y
++) {
197 for (x
= 0; x
< w
; x
++) {
199 data
[y
* w
+ x
] = 0xff00ff00;
201 data
[y
* w
+ x
] = 0xffffff00;
208 err
= transfer_inline(fifo
, 0xfeed0000,
209 vram_gaddr
+ y
* DISPLAY_PITCH
+ x
* DISPLAY_BPP
,
215 err
+= transfer_inline(fifo
+ err
, 0xfeed0000,
216 vram_gaddr
+ y
* DISPLAY_PITCH
+ x
* DISPLAY_BPP
,
219 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
221 err
= wait_fifo_idle(control
);
223 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
224 control
[0x10], control
[0x11], control
[0x12]);
225 dump_fifo(stderr
, fifo
, 0x400);
229 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
230 control
[0x10], control
[0x11], control
[0x12]);
232 save_image("image.argb", (const char *) vram
, DISPLAY_PITCH
* DISPLAY_HEIGHT
);
234 /* Destroy GPU context */
236 context_free
.context_id
= context_id
;
238 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
249 /* Restore console */
251 ioctl(0, SW_TEXT_80x25
, NULL
);