quad.c

   1 /*-
   2  * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification, immediately at the beginning of the file.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include <sys/types.h>
  35 #include <sys/stat.h>
  36 #include <sys/uio.h>
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <sys/fbio.h>
  40 #include <sys/consio.h>
  41 #include <fcntl.h>
  42 #include <unistd.h>
  43
  44 #include "ps3gpu_ctl.h"
  45 #include "ps3gpu_mth.h"
  46 #include "reset_gpu_state.h"
  47 #include "util.h"
  48
  49 int
  50 main(int argc, char **argv)
  51 {
  52         struct ps3gpu_ctl_context_allocate context_allocate;
  53         struct ps3gpu_ctl_context_free context_free;
  54         int context_id;
  55         volatile uint32_t *control;
  56         volatile uint8_t *driver_info;
  57         uint32_t *fifo, *reset_gpu, *db[2], *zb, *fp;
  58         unsigned long fifo_handle, reset_gpu_handle, db_handle[2], zb_handle, fp_handle;
  59         unsigned int fifo_gaddr, reset_gpu_gaddr, db_gaddr[2], zb_gaddr, fp_gaddr;
  60         int fd = -1;
  61         int i, err;
  62
  63         /* Open GPU device */
  64
  65         fd = open(PS3GPU_DEV_PATH, O_RDWR);
  66         if (fd < 0) {
  67                 perror("open");
  68                 goto done;
  69         }
  70
  71         /* Create GPU context */
  72
  73         context_allocate.vram_size = 64; /* MB */
  74
  75         err = ioctl(fd, PS3GPU_CTL_CONTEXT_ALLOCATE, &context_allocate);
  76         if (err < 0) {
  77                 perror("ioctl");
  78                 goto done;
  79         }
  80
  81         context_id = context_allocate.context_id;
  82
  83         printf("context id %d\n", context_id);
  84         printf("control handle 0x%lx size %d\n",
  85             context_allocate.control_handle, context_allocate.control_size);
  86         printf("driver_info handle 0x%lx size %d\n",
  87             context_allocate.driver_info_handle, context_allocate.driver_info_size);
  88
  89         /* Map control registers */
  90
  91         control = mmap(NULL, context_allocate.control_size,
  92             PROT_READ | PROT_WRITE, MAP_SHARED, fd, context_allocate.control_handle);
  93         if (control == (void *) MAP_FAILED) {
  94                 perror("mmap");
  95                 goto done;
  96         }
  97
  98         /* Map driver info */
  99
 100         driver_info = mmap(NULL, context_allocate.driver_info_size,
 101             PROT_READ | PROT_WRITE, MAP_SHARED, fd, context_allocate.driver_info_handle);
 102         if (driver_info == (void *) MAP_FAILED) {
 103                 perror("mmap");
 104                 goto done;
 105         }
 106
 107         printf("channel id %d\n", get_channel_id(driver_info));
 108
 109         /* Allocate FIFO */
 110
 111         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_GART,
 112             64 * 1024, 12, &fifo_handle, &fifo_gaddr, (void **) &fifo);
 113         if (err < 0) {
 114                 perror("memory_allocate");
 115                 goto done;
 116         }
 117
 118         printf("FIFO handle 0x%lx gpu addr 0x%08x\n",
 119             fifo_handle, fifo_gaddr);
 120
 121         /* Setup FIFO */
 122
 123         err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 124         if (err < 0) {
 125                 perror("setup_control");
 126                 goto done;
 127         }
 128
 129         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 130             control[0x10], control[0x11], control[0x12]);
 131
 132         /* Allocate FIFO for resetting GPU state */
 133
 134         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_GART,
 135             4 * 1024, 12, &reset_gpu_handle, &reset_gpu_gaddr, (void **)&reset_gpu);
 136         if (err < 0) {
 137                 perror("memory_allocate");
 138                 goto done;
 139         }
 140
 141         printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
 142             reset_gpu_handle, reset_gpu_gaddr);
 143
 144         memcpy(reset_gpu, reset_gpu_state_3d, reset_gpu_state_3d_size);
 145
 146         /* Kick FIFO */
 147
 148         fifo[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr | PS3GPU_MTH_ADDR_CALL);
 149         fifo[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF);
 150         fifo[2] = 0xcafef00d;
 151
 152         control[0x10] = fifo_gaddr + 3 * sizeof(uint32_t);
 153
 154         err = wait_fifo_idle(control);
 155         if (err < 0) {
 156                 fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 157                     control[0x10], control[0x11], control[0x12]);
 158                 dump_fifo(stderr, fifo, 0x400);
 159                 goto done;
 160         }
 161
 162         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 163             control[0x10], control[0x11], control[0x12]);
 164
 165         /* Allocate display buffers */
 166
 167         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 168             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 169             &db_handle[0], &db_gaddr[0], (void **) &db[0]);
 170         if (err < 0) {
 171                 perror("memory_allocate");
 172                 goto done;
 173         }
 174
 175         printf("DB0 handle 0x%lx gpu addr 0x%08x\n",
 176             db_handle[0], db_gaddr[0]);
 177
 178         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 179             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 180             &db_handle[1], &db_gaddr[1], (void **) &db[1]);
 181         if (err < 0) {
 182                 perror("memory_allocate");
 183                 goto done;
 184         }
 185
 186         printf("DB1 handle 0x%lx gpu addr 0x%08x\n",
 187             db_handle[1], db_gaddr[1]);
 188
 189         /* Allocate depth buffer */
 190
 191         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 192             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 193             &zb_handle, &zb_gaddr, (void **) &zb);
 194         if (err < 0) {
 195                 perror("memory_allocate");
 196                 goto done;
 197         }
 198
 199         printf("ZB handle 0x%lx gpu addr 0x%08x\n",
 200             zb_handle, zb_gaddr);
 201
 202         /* Allocate fragment program */
 203
 204         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 205             4 * 1024, 12, &fp_handle, &fp_gaddr, (void **) &fp);
 206         if (err < 0) {
 207                 perror("memory_allocate");
 208                 goto done;
 209         }
 210
 211         printf("FP handle 0x%lx gpu addr 0x%08x\n",
 212             fp_handle, fp_gaddr);
 213
 214         /* Set display buffers */
 215
 216         err = display_buffer_set(fd, context_id, 0, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 217             DISPLAY_PITCH, db_handle[0]);
 218         if (err < 0) {
 219                 perror("display_buffer_set");
 220                 goto done;
 221         }
 222
 223         err = display_buffer_set(fd, context_id, 1, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 224             DISPLAY_PITCH, db_handle[1]);
 225         if (err < 0) {
 226                 perror("display_buffer_set");
 227                 goto done;
 228         }
 229
 230         const struct surface_desc surf_desc[] = {
 231                 /* display buffer 0 */
 232                 {
 233                         .sd_color_loc = { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
 234                         .sd_color_off = { db_gaddr[0], 0, 0, 0 },
 235                         .sd_color_pitch = { DISPLAY_PITCH, 64, 64, 64 },
 236                         .sd_color_fmt = 0x8,
 237                         .sd_color_target = 0x1,
 238                         .sd_depth_loc = 0xfeed0000,
 239                         .sd_depth_off = zb_gaddr,
 240                         .sd_depth_pitch = DISPLAY_PITCH,
 241                         .sd_depth_fmt = 0x2,
 242                         .sd_x = 0,
 243                         .sd_y = 0,
 244                         .sd_w = DISPLAY_WIDTH,
 245                         .sd_h = DISPLAY_HEIGHT,
 246                 },
 247                 /* display buffer 1 */
 248                 {
 249                         .sd_color_loc = { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
 250                         .sd_color_off = { db_gaddr[1], 0, 0, 0 },
 251                         .sd_color_pitch = { DISPLAY_PITCH, 64, 64, 64 },
 252                         .sd_color_fmt = 0x8,
 253                         .sd_color_target = 0x1,
 254                         .sd_depth_loc = 0xfeed0000,
 255                         .sd_depth_off = zb_gaddr,
 256                         .sd_depth_pitch = DISPLAY_PITCH,
 257                         .sd_depth_fmt = 0x2,
 258                         .sd_x = 0,
 259                         .sd_y = 0,
 260                         .sd_w = DISPLAY_WIDTH,
 261                         .sd_h = DISPLAY_HEIGHT,
 262                 },
 263         };
 264
 265         const uint32_t clear_color[] = {
 266                 0xff404040,
 267                 0xffffffff,
 268         };
 269
 270         const float vp_offset[] = { DISPLAY_WIDTH * 0.5f, DISPLAY_HEIGHT * 0.5f, 0.5f, 0.0f };
 271         const float vp_scale[] = { DISPLAY_WIDTH * 0.5f, DISPLAY_HEIGHT * 0.5f, 0.5f, 0.0f };
 272
 273         const uint32_t vertex_prg[] = {
 274                 /* MOV o[0], v[0] */
 275                 0x401f9c6c, 0x0040000d, 0x8106c083, 0x6041ff80,
 276                 /* MOV o[1], v[3] */
 277                 0x401f9c6c, 0x0040030d, 0x8106c083, 0x6041ff85,
 278         };
 279
 280         uint32_t frag_prg[] = {
 281                 /* MOVR R0, f[1] */
 282                 0x3e010100, 0xc8011c9d, 0xc8000001, 0xc8003fe1,
 283         };
 284
 285         /*
 286          * (-0.5, -0.5) -------- (0.5, -0.5)
 287          *             |        |
 288          *             |        |
 289          *             |        |
 290          *             |        |
 291          * (-0.5, 0.5)  -------- (0.5, 0.5)
 292          *
 293          */
 294
 295         const float quad_pos[][4] = {
 296                 /* xyzw */
 297                 {  0.5f, -0.5f, -1.0f, 1.0f },
 298                 { -0.5f, -0.5f, -1.0f, 1.0f },
 299                 { -0.5f,  0.5f, -1.0f, 1.0f },
 300                 {  0.5f,  0.5f, -1.0f, 1.0f },
 301         };
 302         const float quad_color[][4] = {
 303                 /* rgba */
 304                 { 1.0f, 0.0f, 0.0f, 1.0f },
 305                 { 0.0f, 1.0f, 0.0f, 1.0f },
 306                 { 0.0f, 0.0f, 1.0f, 1.0f },
 307                 { 1.0f, 1.0f, 0.0f, 1.0f },
 308         };
 309
 310         err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 311         if (err < 0) {
 312                 perror("setup_control");
 313                 goto done;
 314         }
 315
 316         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 317             control[0x10], control[0x11], control[0x12]);
 318
 319         /* Transfer fragment program to VRAM */
 320
 321         err += transfer_inline(fifo + err, 0xfeed0000, fp_gaddr,
 322             frag_prg, ARRAY_SIZE(frag_prg));
 323
 324         control[0x10] = fifo_gaddr + err * sizeof(uint32_t);
 325
 326         err = wait_fifo_idle(control);
 327         if (err < 0) {
 328                 fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 329                     control[0x10], control[0x11], control[0x12]);
 330                 dump_fifo(stderr, fifo, 0x400);
 331                 goto done;
 332         }
 333
 334         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 335             control[0x10], control[0x11], control[0x12]);
 336
 337         for (i = 0; i < ARRAY_SIZE(surf_desc); i++) {
 338                 err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 339                 if (err < 0) {
 340                         perror("setup_control");
 341                         goto done;
 342                 }
 343
 344                 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 345                     control[0x10], control[0x11], control[0x12]);
 346
 347                 err += set_surface(fifo + err, &surf_desc[i]);
 348                 err += set_depth_mask(fifo + err, 0x00000000);
 349                 err += set_color_mask(fifo + err, 0x01010101);
 350                 err += set_color_mask_mrt(fifo + err, 0x00000000);
 351                 err += set_clear_color(fifo + err, clear_color[i]);
 352                 err += set_scissor(fifo + err, 0, 0, 4095, 4095);
 353                 err += clear_surface(fifo + err, 0x000000f1);
 354
 355                 err += set_viewport(fifo + err, 0, 0, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 356                     0.0f, 1.0f, vp_offset, vp_scale);
 357
 358                 /* Set vertex shader */
 359
 360                 err += load_vertex_prg(fifo + err, 0, vertex_prg, ARRAY_SIZE(vertex_prg) / 4);
 361                 err += set_vertex_prg_start_slot(fifo + err, 0);
 362                 err += set_vertex_prg_reg_count(fifo + err, 1);
 363                 err += set_vertex_attr_inmask(fifo + err, (1 << 3) | (1 << 0));
 364                 err += set_vertex_attr_outmask(fifo + err, (1 << 2) | (1 << 0));
 365
 366                 /* Set fragment shader */
 367
 368                 err += set_frag_prg(fifo + err, 0x1, fp_gaddr);
 369                 err += frag_prg_ctrl(fifo + err, 2, 0, 0, 0, 0);
 370
 371                 err += set_front_poly_mode(fifo + err, 0x1b02);
 372                 err += set_shade_mode(fifo + err, 0x1d01);
 373
 374                 /* register 0 - position */
 375                 err += set_vertex_data_arrfmt(fifo + err, 0, 0, 0, 0, 2);
 376                 /* register 3 - color */
 377                 err += set_vertex_data_arrfmt(fifo + err, 3, 0, 0, 0, 2);
 378
 379                 err += draw_begin(fifo + err, 0x8);
 380                 err += set_vertex_data_4f(fifo + err, 3, quad_color[0]);
 381                 err += set_vertex_data_4f(fifo + err, 0, quad_pos[0]);
 382                 err += set_vertex_data_4f(fifo + err, 3, quad_color[1]);
 383                 err += set_vertex_data_4f(fifo + err, 0, quad_pos[1]);
 384                 err += set_vertex_data_4f(fifo + err, 3, quad_color[2]);
 385                 err += set_vertex_data_4f(fifo + err, 0, quad_pos[2]);
 386                 err += set_vertex_data_4f(fifo + err, 3, quad_color[3]);
 387                 err += set_vertex_data_4f(fifo + err, 0, quad_pos[3]);
 388                 err += draw_end(fifo + err);
 389
 390                 err += flip_display_buffer(fifo + err, get_channel_id(driver_info), i, 0);
 391
 392                 /*
 393                  * Label with index 0 (head 0) is set by LV1 to 0x00000000 when flip is complete.
 394                  * Let GPU wait for it.
 395                  */
 396
 397                 err += wait_label(fifo + err, 0, 0x00000000);
 398
 399                 control[0x10] = fifo_gaddr + err * sizeof(uint32_t);
 400
 401                 err = wait_fifo_idle(control);
 402                 if (err < 0) {
 403                         fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 404                             control[0x10], control[0x11], control[0x12]);
 405                         dump_fifo(stderr, fifo, 0x400);
 406                         goto done;
 407                 }
 408
 409                 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 410                     control[0x10], control[0x11], control[0x12]);
 411
 412                 usleep(1000000);
 413         }
 414
 415         save_image("image.argb", (const char *) db[0], DISPLAY_PITCH * DISPLAY_HEIGHT);
 416
 417         /* Destroy GPU context */
 418
 419         context_free.context_id = context_id;
 420
 421         err = ioctl(fd, PS3GPU_CTL_CONTEXT_FREE, &context_free);
 422         if (err < 0) {
 423                 perror("ioctl");
 424                 goto done;
 425         }
 426
 427 done:
 428
 429         if (fd >= 0)
 430                 close(fd);
 431
 432         /* Restore console */
 433
 434         ioctl(0, SW_TEXT_80x25, NULL);
 435
 436         exit(0);
 437 }