2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
55 volatile uint32_t *control
;
56 volatile uint8_t *driver_info
;
57 volatile uint8_t *reports
;
58 uint32_t *fifo
, *reset_gpu
, *vram
, *gart
;
59 unsigned long fifo_handle
, reset_gpu_handle
, vram_handle
, gart_handle
;
60 unsigned int fifo_gaddr
, reset_gpu_gaddr
, vram_gaddr
, gart_gaddr
;
67 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
73 /* Create GPU context */
75 context_allocate
.vram_size
= 64; /* MB */
77 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
83 context_id
= context_allocate
.context_id
;
85 printf("context id %d\n", context_id
);
86 printf("control handle 0x%lx size %d\n",
87 context_allocate
.control_handle
, context_allocate
.control_size
);
88 printf("driver_info handle 0x%lx size %d\n",
89 context_allocate
.driver_info_handle
, context_allocate
.driver_info_size
);
90 printf("reports handle 0x%lx size %d\n",
91 context_allocate
.reports_handle
, context_allocate
.reports_size
);
93 /* Map control registers */
95 control
= mmap(NULL
, context_allocate
.control_size
,
96 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
97 if (control
== (void *) MAP_FAILED
) {
102 /* Map driver info */
104 driver_info
= mmap(NULL
, context_allocate
.driver_info_size
,
105 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.driver_info_handle
);
106 if (driver_info
== (void *) MAP_FAILED
) {
113 reports
= mmap(NULL
, context_allocate
.reports_size
,
114 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.reports_handle
);
115 if (reports
== (void *) MAP_FAILED
) {
120 printf("channel id %d\n", get_channel_id(driver_info
));
121 printf("label area offset 0x%08x\n", get_label_area_offset(driver_info
));
122 printf("report data area offset 0x%08x\n", get_report_data_area_offset(driver_info
));
126 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
127 64 * 1024, 12, &fifo_handle
, &fifo_gaddr
, (void **) &fifo
);
129 perror("memory_allocate");
133 printf("FIFO handle 0x%lx gpu addr 0x%08x\n",
134 fifo_handle
, fifo_gaddr
);
138 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
140 perror("setup_control");
144 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
145 control
[0x10], control
[0x11], control
[0x12]);
147 /* Allocate FIFO for resetting GPU state */
149 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
150 4 * 1024, 12, &reset_gpu_handle
, &reset_gpu_gaddr
, (void **) &reset_gpu
);
152 perror("memory_allocate");
156 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
157 reset_gpu_handle
, reset_gpu_gaddr
);
159 memcpy(reset_gpu
, reset_gpu_state_3d
, reset_gpu_state_3d_size
);
163 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
164 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
165 fifo
[2] = 0xcafef00d;
167 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
169 err
= wait_fifo_idle(control
);
171 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
172 control
[0x10], control
[0x11], control
[0x12]);
173 dump_fifo(stderr
, fifo
, 0x400);
177 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
178 control
[0x10], control
[0x11], control
[0x12]);
182 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_VIDEO
,
183 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
184 &vram_handle
, &vram_gaddr
, (void **) &vram
);
186 perror("memory_allocate");
190 printf("VRAM handle 0x%lx gpu addr 0x%08x\n",
191 vram_handle
, vram_gaddr
);
193 memset32(vram
, 0xff404040, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
197 err
= flip(fd
, context_id
, PS3GPU_CTL_HEAD_A
, vram_handle
);
203 err
= flip(fd
, context_id
, PS3GPU_CTL_HEAD_B
, vram_handle
);
213 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
214 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
215 &gart_handle
, &gart_gaddr
, (void **) &gart
);
217 perror("memory_allocate");
221 printf("GART handle 0x%lx gpu addr 0x%08x\n",
222 gart_handle
, gart_gaddr
);
224 memset32(gart
, 0xff0000ff, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
226 /* Blit GART buffer to VRAM with RSX DMA */
228 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
230 perror("setup_control");
234 err
+= set_timestamp(fifo
+ err
, 800);
235 err
+= transfer_data(fifo
+ err
, 0xfeed0001, 0xfeed0000,
236 vram_gaddr
, DISPLAY_PITCH
, gart_gaddr
, DISPLAY_PITCH
,
237 DISPLAY_PITCH
, DISPLAY_HEIGHT
);
238 err
+= set_timestamp(fifo
+ err
, 801);
239 err
+= set_reference(fifo
+ err
, 0xdeadb00b);
241 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
243 err
= wait_fifo_idle(control
);
245 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
246 control
[0x10], control
[0x11], control
[0x12]);
247 dump_fifo(stderr
, fifo
, 0x400);
251 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
252 control
[0x10], control
[0x11], control
[0x12]);
254 while (control
[0x12] != 0xdeadb00b)
257 ts1
= get_timestamp_value(driver_info
, reports
, 800);
258 ts2
= get_timestamp_value(driver_info
, reports
, 801);
260 printf("ts1 %lu ts2 %lu diff %lu ns\n", ts1
, ts2
, ts2
- ts1
);
262 save_image("image.argb", (const char *) vram
, DISPLAY_PITCH
* DISPLAY_HEIGHT
);
264 /* Destroy GPU context */
266 context_free
.context_id
= context_id
;
268 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
279 /* Restore console */
281 ioctl(0, SW_TEXT_80x25
, NULL
);