2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
54 struct ps3gpu_ctl_memory_allocate memory_allocate
;
55 struct ps3gpu_ctl_setup_control setup_control
;
56 struct ps3gpu_ctl_flip flip
;
58 volatile uint32_t *control
;
59 uint32_t *fifo
, *reset_gpu
, *vram
, *gart
;
60 unsigned long fifo_handle
, vram_handle
, gart_handle
;
61 unsigned int fifo_gaddr
, reset_gpu_gaddr
, vram_gaddr
, gart_gaddr
;
67 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
73 /* Create GPU context */
75 context_allocate
.vram_size
= 64; /* MB */
77 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
83 context_id
= context_allocate
.context_id
;
85 printf("context id %d\n", context_id
);
86 printf("control handle 0x%lx size %d\n",
87 context_allocate
.control_handle
, context_allocate
.control_size
);
89 /* Map control registers */
91 control
= mmap(NULL
, context_allocate
.control_size
,
92 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
93 if (control
== (void *) MAP_FAILED
) {
100 memory_allocate
.context_id
= context_id
;
101 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
102 memory_allocate
.size
= 64 * 1024;
103 memory_allocate
.align
= 12;
105 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
111 fifo_handle
= memory_allocate
.handle
;
112 fifo_gaddr
= memory_allocate
.gpu_addr
;
114 printf("fifo handle 0x%lx gpu addr 0x%08x\n",
115 fifo_handle
, fifo_gaddr
);
119 fifo
= mmap(NULL
, memory_allocate
.size
,
120 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fifo_handle
);
121 if (fifo
== (void *) MAP_FAILED
) {
128 setup_control
.context_id
= context_id
;
129 setup_control
.put
= fifo_handle
;
130 setup_control
.get
= fifo_handle
;
131 setup_control
.ref
= 0xdeadbabe;
133 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
139 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
140 control
[0x10], control
[0x11], control
[0x12]);
142 /* Allocate FIFO for resetting GPU state */
144 memory_allocate
.context_id
= context_id
;
145 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
146 memory_allocate
.size
= 4 * 1024;
147 memory_allocate
.align
= 12;
149 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
155 reset_gpu_gaddr
= memory_allocate
.gpu_addr
;
157 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
158 memory_allocate
.handle
, reset_gpu_gaddr
);
160 /* Map FIFO for resetting GPU state */
162 reset_gpu
= mmap(NULL
, memory_allocate
.size
,
163 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, memory_allocate
.handle
);
164 if (reset_gpu
== (void *) MAP_FAILED
) {
169 memcpy(reset_gpu
, reset_gpu_state
, reset_gpu_state_size
);
173 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
174 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
175 fifo
[2] = 0xcafef00d;
177 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
179 err
= wait_fifo_idle(control
);
181 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
182 control
[0x10], control
[0x11], control
[0x12]);
183 dump_fifo(stderr
, fifo
, 0x400);
187 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
188 control
[0x10], control
[0x11], control
[0x12]);
192 memory_allocate
.context_id
= context_id
;
193 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
194 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
195 memory_allocate
.align
= 12;
197 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
203 vram_handle
= memory_allocate
.handle
;
204 vram_gaddr
= memory_allocate
.gpu_addr
;
206 printf("VRAM handle 0x%lx gpu addr 0x%08x\n",
207 vram_handle
, vram_gaddr
);
211 vram
= mmap(NULL
, memory_allocate
.size
,
212 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, vram_handle
);
213 if (vram
== (void *) MAP_FAILED
) {
218 memset32(vram
, 0xff404040, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
222 flip
.context_id
= context_id
;
223 flip
.head
= PS3GPU_CTL_HEAD_A
;
224 flip
.offset
= vram_handle
;
226 err
= ioctl(fd
, PS3GPU_CTL_FLIP
, &flip
);
232 flip
.context_id
= context_id
;
233 flip
.head
= PS3GPU_CTL_HEAD_B
;
234 flip
.offset
= vram_handle
;
236 err
= ioctl(fd
, PS3GPU_CTL_FLIP
, &flip
);
246 memory_allocate
.context_id
= context_id
;
247 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
248 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
249 memory_allocate
.align
= 12;
251 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
257 gart_handle
= memory_allocate
.handle
;
258 gart_gaddr
= memory_allocate
.gpu_addr
;
260 printf("GART handle 0x%lx gpu addr 0x%08x\n",
261 gart_handle
, gart_gaddr
);
265 gart
= mmap(NULL
, memory_allocate
.size
,
266 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, gart_handle
);
267 if (gart
== (void *) MAP_FAILED
) {
272 memset32(gart
, 0xff0000ff, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
274 /* Blit GART buffer to VRAM with RSX DMA */
276 setup_control
.context_id
= context_id
;
277 setup_control
.put
= fifo_handle
;
278 setup_control
.get
= fifo_handle
;
279 setup_control
.ref
= 0xdeadbabe;
281 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
287 err
= transfer_data(fifo
, 0xfeed0001, 0xfeed0000,
288 vram_gaddr
, DISPLAY_PITCH
, gart_gaddr
, DISPLAY_PITCH
,
289 DISPLAY_PITCH
, DISPLAY_HEIGHT
);
291 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
293 err
= wait_fifo_idle(control
);
295 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
296 control
[0x10], control
[0x11], control
[0x12]);
297 dump_fifo(stderr
, fifo
, 0x400);
301 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
302 control
[0x10], control
[0x11], control
[0x12]);
304 save_image("image.argb", (const char *) vram
, DISPLAY_PITCH
* DISPLAY_HEIGHT
);
306 /* Destroy GPU context */
308 context_free
.context_id
= context_id
;
310 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
321 /* Restore console */
323 ioctl(0, SW_TEXT_80x25
, NULL
);