2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
54 struct ps3gpu_ctl_memory_allocate memory_allocate
;
55 struct ps3gpu_ctl_setup_control setup_control
;
56 struct ps3gpu_ctl_display_buffer_set display_buffer_set
;
58 volatile uint32_t *control
;
59 volatile uint8_t *driver_info
;
60 uint32_t *fifo
, *reset_gpu
, *db
[2], *zb
, *fp
;
61 unsigned long fifo_handle
, db_handle
[2], zb_handle
, fp_handle
;
62 unsigned int fifo_gaddr
, reset_gpu_gaddr
, db_gaddr
[2], zb_gaddr
, fp_gaddr
;
68 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
74 /* Create GPU context */
76 context_allocate
.vram_size
= 64; /* MB */
78 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
84 context_id
= context_allocate
.context_id
;
86 printf("context id %d\n", context_id
);
87 printf("control handle 0x%lx size %d\n",
88 context_allocate
.control_handle
, context_allocate
.control_size
);
89 printf("driver_info handle 0x%lx size %d\n",
90 context_allocate
.driver_info_handle
, context_allocate
.driver_info_size
);
92 /* Map control registers */
94 control
= mmap(NULL
, context_allocate
.control_size
,
95 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
96 if (control
== (void *) MAP_FAILED
) {
101 /* Map driver info */
103 driver_info
= mmap(NULL
, context_allocate
.driver_info_size
,
104 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.driver_info_handle
);
105 if (driver_info
== (void *) MAP_FAILED
) {
110 printf("channel id %d\n", get_channel_id(driver_info
));
114 memory_allocate
.context_id
= context_id
;
115 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
116 memory_allocate
.size
= 64 * 1024;
117 memory_allocate
.align
= 12;
119 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
125 fifo_handle
= memory_allocate
.handle
;
126 fifo_gaddr
= memory_allocate
.gpu_addr
;
128 printf("fifo handle 0x%lx gpu addr 0x%08x\n",
129 fifo_handle
, fifo_gaddr
);
133 fifo
= mmap(NULL
, memory_allocate
.size
,
134 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fifo_handle
);
135 if (fifo
== (void *) MAP_FAILED
) {
142 setup_control
.context_id
= context_id
;
143 setup_control
.put
= fifo_handle
;
144 setup_control
.get
= fifo_handle
;
145 setup_control
.ref
= 0xdeadbabe;
147 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
153 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
154 control
[0x10], control
[0x11], control
[0x12]);
156 /* Allocate FIFO for resetting GPU state */
158 memory_allocate
.context_id
= context_id
;
159 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
160 memory_allocate
.size
= 4 * 1024;
161 memory_allocate
.align
= 12;
163 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
169 reset_gpu_gaddr
= memory_allocate
.gpu_addr
;
171 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
172 memory_allocate
.handle
, reset_gpu_gaddr
);
174 /* Map FIFO for resetting GPU state */
176 reset_gpu
= mmap(NULL
, memory_allocate
.size
,
177 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, memory_allocate
.handle
);
178 if (reset_gpu
== (void *) MAP_FAILED
) {
183 memcpy(reset_gpu
, reset_gpu_state_3d
, reset_gpu_state_3d_size
);
187 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
188 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
189 fifo
[2] = 0xcafef00d;
191 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
193 err
= wait_fifo_idle(control
);
195 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
196 control
[0x10], control
[0x11], control
[0x12]);
197 dump_fifo(stderr
, fifo
, 0x400);
201 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
202 control
[0x10], control
[0x11], control
[0x12]);
204 /* Allocate display buffers */
206 memory_allocate
.context_id
= context_id
;
207 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
208 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
209 memory_allocate
.align
= 12;
211 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
217 db_handle
[0] = memory_allocate
.handle
;
218 db_gaddr
[0] = memory_allocate
.gpu_addr
;
220 printf("DB0 handle 0x%lx gpu addr 0x%08x\n",
221 db_handle
[0], db_gaddr
[0]);
223 db
[0] = mmap(NULL
, memory_allocate
.size
,
224 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, db_handle
[0]);
225 if (db
[0] == (void *) MAP_FAILED
) {
230 memory_allocate
.context_id
= context_id
;
231 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
232 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
233 memory_allocate
.align
= 12;
235 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
241 db_handle
[1] = memory_allocate
.handle
;
242 db_gaddr
[1] = memory_allocate
.gpu_addr
;
244 printf("DB1 handle 0x%lx gpu addr 0x%08x\n",
245 db_handle
[1], db_gaddr
[1]);
247 db
[1] = mmap(NULL
, memory_allocate
.size
,
248 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, db_handle
[1]);
249 if (db
[1] == (void *) MAP_FAILED
) {
254 /* Allocate depth buffer */
256 memory_allocate
.context_id
= context_id
;
257 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
258 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
259 memory_allocate
.align
= 12;
261 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
267 zb_handle
= memory_allocate
.handle
;
268 zb_gaddr
= memory_allocate
.gpu_addr
;
270 printf("ZB handle 0x%lx gpu addr 0x%08x\n",
271 zb_handle
, zb_gaddr
);
273 zb
= mmap(NULL
, memory_allocate
.size
,
274 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, zb_handle
);
275 if (zb
== (void *) MAP_FAILED
) {
280 /* Allocate fragment program */
282 memory_allocate
.context_id
= context_id
;
283 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
284 memory_allocate
.size
= 4 * 1024;
285 memory_allocate
.align
= 12;
287 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
293 fp_handle
= memory_allocate
.handle
;
294 fp_gaddr
= memory_allocate
.gpu_addr
;
296 printf("FP handle 0x%lx gpu addr 0x%08x\n",
297 fp_handle
, fp_gaddr
);
299 fp
= mmap(NULL
, memory_allocate
.size
,
300 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fp_handle
);
301 if (fp
== (void *) MAP_FAILED
) {
306 /* Set display buffers */
308 display_buffer_set
.context_id
= context_id
;
309 display_buffer_set
.buffer_id
= 0;
310 display_buffer_set
.width
= DISPLAY_WIDTH
;
311 display_buffer_set
.height
= DISPLAY_HEIGHT
;
312 display_buffer_set
.pitch
= DISPLAY_PITCH
;
313 display_buffer_set
.offset
= db_handle
[0];
315 err
= ioctl(fd
, PS3GPU_CTL_DISPLAY_BUFFER_SET
, &display_buffer_set
);
321 display_buffer_set
.context_id
= context_id
;
322 display_buffer_set
.buffer_id
= 1;
323 display_buffer_set
.width
= DISPLAY_WIDTH
;
324 display_buffer_set
.height
= DISPLAY_HEIGHT
;
325 display_buffer_set
.pitch
= DISPLAY_PITCH
;
326 display_buffer_set
.offset
= db_handle
[1];
328 err
= ioctl(fd
, PS3GPU_CTL_DISPLAY_BUFFER_SET
, &display_buffer_set
);
334 const struct surface_desc surf_desc
[] = {
335 /* display buffer 0 */
337 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
338 .sd_color_off
= { db_gaddr
[0], 0, 0, 0 },
339 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
341 .sd_color_target
= 0x1,
342 .sd_depth_loc
= 0xfeed0000,
343 .sd_depth_off
= zb_gaddr
,
344 .sd_depth_pitch
= DISPLAY_PITCH
,
348 .sd_w
= DISPLAY_WIDTH
,
349 .sd_h
= DISPLAY_HEIGHT
,
351 /* display buffer 1 */
353 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
354 .sd_color_off
= { db_gaddr
[1], 0, 0, 0 },
355 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
357 .sd_color_target
= 0x1,
358 .sd_depth_loc
= 0xfeed0000,
359 .sd_depth_off
= zb_gaddr
,
360 .sd_depth_pitch
= DISPLAY_PITCH
,
364 .sd_w
= DISPLAY_WIDTH
,
365 .sd_h
= DISPLAY_HEIGHT
,
369 const uint32_t clear_color
[] = {
374 const float vp_offset
[] = { DISPLAY_WIDTH
* 0.5f
, DISPLAY_HEIGHT
* 0.5f
, 0.5f
, 0.0f
};
375 const float vp_scale
[] = { DISPLAY_WIDTH
* 0.5f
, DISPLAY_HEIGHT
* 0.5f
, 0.5f
, 0.0f
};
377 const uint32_t vertex_prg
[] = {
379 0x401f9c6c, 0x0040000d, 0x8106c083, 0x6041ff80,
381 0x401f9c6c, 0x0040030d, 0x8106c083, 0x6041ff85,
384 uint32_t frag_prg
[] = {
386 0x01003e01, 0x1c9dc801, 0x0001c800, 0x3fe1c800,
395 * (-0.5, 0.5) /________\ (0.5, 0.5)
399 const float triangle_pos
[][4] = {
401 { 0.0f
, -0.5f
, -1.0f
, 1.0f
},
402 { -0.5f
, 0.5f
, -1.0f
, 1.0f
},
403 { 0.5f
, 0.5f
, -1.0f
, 1.0f
},
405 const float triangle_color
[][4] = {
407 { 1.0f
, 0.0f
, 0.0f
, 1.0f
},
408 { 0.0f
, 1.0f
, 0.0f
, 1.0f
},
409 { 0.0f
, 0.0f
, 1.0f
, 1.0f
},
412 /* Swap half-words in fragment program */
414 for (i
= 0; i
< ARRAY_SIZE(frag_prg
); i
++)
415 frag_prg
[i
] = (frag_prg
[i
] << 16) | (frag_prg
[i
] >> 16);
417 for (i
= 0; i
< ARRAY_SIZE(surf_desc
); i
++) {
418 setup_control
.context_id
= context_id
;
419 setup_control
.put
= fifo_handle
;
420 setup_control
.get
= fifo_handle
;
421 setup_control
.ref
= 0xdeadbabe;
423 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
429 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
430 control
[0x10], control
[0x11], control
[0x12]);
432 err
+= set_surface(fifo
+ err
, &surf_desc
[i
]);
433 err
+= set_depth_mask(fifo
+ err
, 0x00000000);
434 err
+= set_color_mask(fifo
+ err
, 0x01010101);
435 err
+= set_color_mask_mrt(fifo
+ err
, 0x00000000);
436 err
+= set_clear_color(fifo
+ err
, clear_color
[i
]);
437 err
+= set_scissor(fifo
+ err
, 0, 0, 4095, 4095);
438 err
+= clear_surface(fifo
+ err
, 0x000000f1);
440 err
+= set_viewport(fifo
+ err
, 0, 0, DISPLAY_WIDTH
, DISPLAY_HEIGHT
,
441 0.0f
, 1.0f
, vp_offset
, vp_scale
);
443 /* Set vertex shader */
445 err
+= load_vertex_prg(fifo
+ err
, 0, vertex_prg
, ARRAY_SIZE(vertex_prg
) / 4);
446 err
+= set_vertex_prg_start_slot(fifo
+ err
, 0);
447 err
+= set_vertex_prg_reg_count(fifo
+ err
, 2);
448 err
+= set_vertex_attr_inmask(fifo
+ err
, (1 << 3) | (1 << 0));
449 err
+= set_vertex_attr_outmask(fifo
+ err
, (1 << 2) | (1 << 0));
451 /* Transfer fragment program to VRAM */
453 err
+= transfer_inline(fifo
+ err
, 0xfeed0000, fp_gaddr
,
454 frag_prg
, ARRAY_SIZE(frag_prg
));
456 /* Set fragment shader */
458 err
+= set_frag_prg(fifo
+ err
, 0x1, fp_gaddr
);
459 err
+= frag_prg_ctrl(fifo
+ err
, 2, 0, 0, 0, 0);
461 err
+= set_front_poly_mode(fifo
+ err
, 0x1b02);
462 err
+= set_shade_mode(fifo
+ err
, 0x1d01);
464 /* register 0 - position */
465 err
+= set_vertex_data_arrfmt(fifo
+ err
, 0, 0, 0, 0, 2);
466 /* register 3 - color */
467 err
+= set_vertex_data_arrfmt(fifo
+ err
, 3, 0, 0, 0, 2);
469 err
+= draw_begin(fifo
+ err
, 0x5);
470 err
+= set_vertex_data_4f(fifo
+ err
, 3, triangle_color
[0]);
471 err
+= set_vertex_data_4f(fifo
+ err
, 0, triangle_pos
[0]);
472 err
+= set_vertex_data_4f(fifo
+ err
, 3, triangle_color
[1]);
473 err
+= set_vertex_data_4f(fifo
+ err
, 0, triangle_pos
[1]);
474 err
+= set_vertex_data_4f(fifo
+ err
, 3, triangle_color
[2]);
475 err
+= set_vertex_data_4f(fifo
+ err
, 0, triangle_pos
[2]);
476 err
+= draw_end(fifo
+ err
);
478 err
+= flip_display_buffer(fifo
+ err
, get_channel_id(driver_info
), i
, 0);
481 * Label with index 0 (head 0) is set by LV1 to 0x00000000 when flip is complete.
482 * Let GPU wait for it.
485 err
+= wait_label(fifo
+ err
, 0, 0x00000000);
487 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
489 err
= wait_fifo_idle(control
);
491 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
492 control
[0x10], control
[0x11], control
[0x12]);
493 dump_fifo(stderr
, fifo
, 0x400);
497 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
498 control
[0x10], control
[0x11], control
[0x12]);
503 save_image("image.argb", (const char *) db
[0], DISPLAY_PITCH
* DISPLAY_HEIGHT
);
505 /* Destroy GPU context */
507 context_free
.context_id
= context_id
;
509 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
520 /* Restore console */
522 ioctl(0, SW_TEXT_80x25
, NULL
);