2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/types.h>
38 #include <sys/ioctl.h>
41 #include <sys/consio.h>
45 #include "ps3gpu_ctl.h"
46 #include "ps3gpu_mth.h"
47 #include "reset_gpu_state.h"
56 main(int argc
, char **argv
)
58 struct ps3gpu_ctl_context_allocate context_allocate
;
59 struct ps3gpu_ctl_context_free context_free
;
60 struct ps3gpu_ctl_memory_allocate memory_allocate
;
61 struct ps3gpu_ctl_setup_control setup_control
;
62 struct ps3gpu_ctl_display_buffer_set display_buffer_set
;
64 volatile uint32_t *control
;
65 volatile uint8_t *driver_info
;
66 uint32_t *fifo
, *reset_gpu
, *db
[2], *zb
, *fp
, *verts
;
67 unsigned long fifo_handle
, db_handle
[2], zb_handle
, fp_handle
, verts_handle
;
68 unsigned int fifo_gaddr
, reset_gpu_gaddr
, db_gaddr
[2], zb_gaddr
, fp_gaddr
, verts_gaddr
;
74 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
80 /* Create GPU context */
82 context_allocate
.vram_size
= 64; /* MB */
84 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
90 context_id
= context_allocate
.context_id
;
92 printf("context id %d\n", context_id
);
93 printf("control handle 0x%lx size %d\n",
94 context_allocate
.control_handle
, context_allocate
.control_size
);
95 printf("driver_info handle 0x%lx size %d\n",
96 context_allocate
.driver_info_handle
, context_allocate
.driver_info_size
);
98 /* Map control registers */
100 control
= mmap(NULL
, context_allocate
.control_size
,
101 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
102 if (control
== (void *) MAP_FAILED
) {
107 /* Map driver info */
109 driver_info
= mmap(NULL
, context_allocate
.driver_info_size
,
110 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.driver_info_handle
);
111 if (driver_info
== (void *) MAP_FAILED
) {
116 printf("channel id %d\n", get_channel_id(driver_info
));
120 memory_allocate
.context_id
= context_id
;
121 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
122 memory_allocate
.size
= 64 * 1024;
123 memory_allocate
.align
= 12;
125 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
131 fifo_handle
= memory_allocate
.handle
;
132 fifo_gaddr
= memory_allocate
.gpu_addr
;
134 printf("fifo handle 0x%lx gpu addr 0x%08x\n",
135 fifo_handle
, fifo_gaddr
);
139 fifo
= mmap(NULL
, memory_allocate
.size
,
140 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fifo_handle
);
141 if (fifo
== (void *) MAP_FAILED
) {
148 setup_control
.context_id
= context_id
;
149 setup_control
.put
= fifo_handle
;
150 setup_control
.get
= fifo_handle
;
151 setup_control
.ref
= 0xdeadbabe;
153 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
159 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
160 control
[0x10], control
[0x11], control
[0x12]);
162 /* Allocate FIFO for resetting GPU state */
164 memory_allocate
.context_id
= context_id
;
165 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
166 memory_allocate
.size
= 4 * 1024;
167 memory_allocate
.align
= 12;
169 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
175 reset_gpu_gaddr
= memory_allocate
.gpu_addr
;
177 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
178 memory_allocate
.handle
, reset_gpu_gaddr
);
180 /* Map FIFO for resetting GPU state */
182 reset_gpu
= mmap(NULL
, memory_allocate
.size
,
183 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, memory_allocate
.handle
);
184 if (reset_gpu
== (void *) MAP_FAILED
) {
189 memcpy(reset_gpu
, reset_gpu_state_3d
, reset_gpu_state_3d_size
);
193 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
194 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
195 fifo
[2] = 0xcafef00d;
197 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
199 err
= wait_fifo_idle(control
);
201 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
202 control
[0x10], control
[0x11], control
[0x12]);
203 dump_fifo(stderr
, fifo
, 0x400);
207 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
208 control
[0x10], control
[0x11], control
[0x12]);
210 /* Allocate display buffers */
212 memory_allocate
.context_id
= context_id
;
213 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
214 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
215 memory_allocate
.align
= 12;
217 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
223 db_handle
[0] = memory_allocate
.handle
;
224 db_gaddr
[0] = memory_allocate
.gpu_addr
;
226 printf("DB0 handle 0x%lx gpu addr 0x%08x\n",
227 db_handle
[0], db_gaddr
[0]);
229 db
[0] = mmap(NULL
, memory_allocate
.size
,
230 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, db_handle
[0]);
231 if (db
[0] == (void *) MAP_FAILED
) {
236 memory_allocate
.context_id
= context_id
;
237 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
238 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
239 memory_allocate
.align
= 12;
241 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
247 db_handle
[1] = memory_allocate
.handle
;
248 db_gaddr
[1] = memory_allocate
.gpu_addr
;
250 printf("DB1 handle 0x%lx gpu addr 0x%08x\n",
251 db_handle
[1], db_gaddr
[1]);
253 db
[1] = mmap(NULL
, memory_allocate
.size
,
254 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, db_handle
[1]);
255 if (db
[1] == (void *) MAP_FAILED
) {
260 /* Allocate depth buffer */
262 memory_allocate
.context_id
= context_id
;
263 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
264 memory_allocate
.size
= ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024);
265 memory_allocate
.align
= 12;
267 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
273 zb_handle
= memory_allocate
.handle
;
274 zb_gaddr
= memory_allocate
.gpu_addr
;
276 printf("ZB handle 0x%lx gpu addr 0x%08x\n",
277 zb_handle
, zb_gaddr
);
279 zb
= mmap(NULL
, memory_allocate
.size
,
280 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, zb_handle
);
281 if (zb
== (void *) MAP_FAILED
) {
286 /* Allocate fragment program */
288 memory_allocate
.context_id
= context_id
;
289 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
290 memory_allocate
.size
= 4 * 1024;
291 memory_allocate
.align
= 12;
293 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
299 fp_handle
= memory_allocate
.handle
;
300 fp_gaddr
= memory_allocate
.gpu_addr
;
302 printf("FP handle 0x%lx gpu addr 0x%08x\n",
303 fp_handle
, fp_gaddr
);
305 fp
= mmap(NULL
, memory_allocate
.size
,
306 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fp_handle
);
307 if (fp
== (void *) MAP_FAILED
) {
312 /* Allocate vertices */
314 memory_allocate
.context_id
= context_id
;
315 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
316 memory_allocate
.size
= 4 * 1024;
317 memory_allocate
.align
= 12;
319 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
325 verts_handle
= memory_allocate
.handle
;
326 verts_gaddr
= memory_allocate
.gpu_addr
;
328 printf("VERTS handle 0x%lx gpu addr 0x%08x\n",
329 verts_handle
, verts_gaddr
);
331 verts
= mmap(NULL
, memory_allocate
.size
,
332 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, verts_handle
);
333 if (verts
== (void *) MAP_FAILED
) {
338 /* Set display buffers */
340 display_buffer_set
.context_id
= context_id
;
341 display_buffer_set
.buffer_id
= 0;
342 display_buffer_set
.width
= DISPLAY_WIDTH
;
343 display_buffer_set
.height
= DISPLAY_HEIGHT
;
344 display_buffer_set
.pitch
= DISPLAY_PITCH
;
345 display_buffer_set
.offset
= db_handle
[0];
347 err
= ioctl(fd
, PS3GPU_CTL_DISPLAY_BUFFER_SET
, &display_buffer_set
);
353 display_buffer_set
.context_id
= context_id
;
354 display_buffer_set
.buffer_id
= 1;
355 display_buffer_set
.width
= DISPLAY_WIDTH
;
356 display_buffer_set
.height
= DISPLAY_HEIGHT
;
357 display_buffer_set
.pitch
= DISPLAY_PITCH
;
358 display_buffer_set
.offset
= db_handle
[1];
360 err
= ioctl(fd
, PS3GPU_CTL_DISPLAY_BUFFER_SET
, &display_buffer_set
);
366 const struct surface_desc surf_desc
[] = {
367 /* display buffer 0 */
369 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
370 .sd_color_off
= { db_gaddr
[0], 0, 0, 0 },
371 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
373 .sd_color_target
= 0x1,
374 .sd_depth_loc
= 0xfeed0000,
375 .sd_depth_off
= zb_gaddr
,
376 .sd_depth_pitch
= DISPLAY_PITCH
,
380 .sd_w
= DISPLAY_WIDTH
,
381 .sd_h
= DISPLAY_HEIGHT
,
383 /* display buffer 1 */
385 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
386 .sd_color_off
= { db_gaddr
[1], 0, 0, 0 },
387 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
389 .sd_color_target
= 0x1,
390 .sd_depth_loc
= 0xfeed0000,
391 .sd_depth_off
= zb_gaddr
,
392 .sd_depth_pitch
= DISPLAY_PITCH
,
396 .sd_w
= DISPLAY_WIDTH
,
397 .sd_h
= DISPLAY_HEIGHT
,
401 const uint32_t clear_color
[] = {
406 const float vp_offset
[] = { DISPLAY_WIDTH
* 0.5f
, DISPLAY_HEIGHT
* 0.5f
, 0.5f
, 0.0f
};
407 const float vp_scale
[] = { DISPLAY_WIDTH
* 0.5f
, DISPLAY_HEIGHT
* 0.5f
, 0.5f
, 0.0f
};
409 const uint32_t vertex_prg
[] = {
411 0x401f9c6c, 0x0040000d, 0x8106c083, 0x6041ff80,
413 0x401f9c6c, 0x0040030d, 0x8106c083, 0x6041ff85,
416 uint32_t frag_prg
[] = {
418 0x01003e01, 0x1c9dc801, 0x0001c800, 0x3fe1c800,
427 * (-0.5, 0.5) /________\ (0.5, 0.5)
431 const struct vertex triangle_verts
[] = {
432 { 0.0f
, -0.5f
, -1.0f
, 0xff0000ff },
433 { -0.5f
, 0.5f
, -1.0f
, 0x00ff00ff },
434 { 0.5f
, 0.5f
, -1.0f
, 0x0000ffff },
437 /* Swap half-words in fragment program */
439 for (i
= 0; i
< ARRAY_SIZE(frag_prg
); i
++)
440 frag_prg
[i
] = (frag_prg
[i
] << 16) | (frag_prg
[i
] >> 16);
442 for (i
= 0; i
< ARRAY_SIZE(surf_desc
); i
++) {
443 setup_control
.context_id
= context_id
;
444 setup_control
.put
= fifo_handle
;
445 setup_control
.get
= fifo_handle
;
446 setup_control
.ref
= 0xdeadbabe;
448 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
454 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
455 control
[0x10], control
[0x11], control
[0x12]);
457 err
+= set_surface(fifo
+ err
, &surf_desc
[i
]);
458 err
+= set_depth_mask(fifo
+ err
, 0x00000000);
459 err
+= set_color_mask(fifo
+ err
, 0x01010101);
460 err
+= set_color_mask_mrt(fifo
+ err
, 0x00000000);
461 err
+= set_clear_color(fifo
+ err
, clear_color
[i
]);
462 err
+= set_scissor(fifo
+ err
, 0, 0, 4095, 4095);
463 err
+= clear_surface(fifo
+ err
, 0x000000f1);
465 err
+= set_viewport(fifo
+ err
, 0, 0, DISPLAY_WIDTH
, DISPLAY_HEIGHT
,
466 0.0f
, 1.0f
, vp_offset
, vp_scale
);
468 /* Set vertex shader */
470 err
+= load_vertex_prg(fifo
+ err
, 0, vertex_prg
, ARRAY_SIZE(vertex_prg
) / 4);
471 err
+= set_vertex_prg_start_slot(fifo
+ err
, 0);
472 err
+= set_vertex_prg_reg_count(fifo
+ err
, 2);
473 err
+= set_vertex_attr_inmask(fifo
+ err
, (1 << 3) | (1 << 0));
474 err
+= set_vertex_attr_outmask(fifo
+ err
, (1 << 2) | (1 << 0));
476 /* Transfer fragment program to VRAM */
478 err
+= transfer_inline(fifo
+ err
, 0xfeed0000, fp_gaddr
,
479 frag_prg
, ARRAY_SIZE(frag_prg
));
481 /* Set fragment shader */
483 err
+= set_frag_prg(fifo
+ err
, 0x1, fp_gaddr
);
484 err
+= frag_prg_ctrl(fifo
+ err
, 2, 0, 0, 0, 0);
486 err
+= set_front_poly_mode(fifo
+ err
, 0x1b02);
487 err
+= set_shade_mode(fifo
+ err
, 0x1d01);
489 /* Transfer vertices to VRAM */
491 err
+= transfer_inline(fifo
+ err
, 0xfeed0000, verts_gaddr
,
492 (uint32_t *) triangle_verts
, sizeof(triangle_verts
) / sizeof(uint32_t));
494 /* register 0 - position */
495 err
+= set_vertex_data_arr(fifo
+ err
, 0, 0, sizeof(struct vertex
),
496 3, 2, verts_gaddr
+ offsetof(struct vertex
, x
), 0x0);
497 /* register 3 - color */
498 err
+= set_vertex_data_arr(fifo
+ err
, 3, 0, sizeof(struct vertex
),
499 4, 4, verts_gaddr
+ offsetof(struct vertex
, rgba
), 0x0);
501 err
+= draw_arrays(fifo
+ err
, 0x5, 0, ARRAY_SIZE(triangle_verts
));
503 err
+= flip_display_buffer(fifo
+ err
, get_channel_id(driver_info
), i
, 0);
506 * Label with index 0 (head 0) is set by LV1 to 0x00000000 when flip is complete.
507 * Let GPU wait for it.
510 err
+= wait_label(fifo
+ err
, 0, 0x00000000);
512 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
514 err
= wait_fifo_idle(control
);
516 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
517 control
[0x10], control
[0x11], control
[0x12]);
518 dump_fifo(stderr
, fifo
, 0x400);
522 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
523 control
[0x10], control
[0x11], control
[0x12]);
528 save_image("image.argb", (const char *) db
[0], DISPLAY_PITCH
* DISPLAY_HEIGHT
);
530 /* Destroy GPU context */
532 context_free
.context_id
= context_id
;
534 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
545 /* Restore console */
547 ioctl(0, SW_TEXT_80x25
, NULL
);