pscnv/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "nouveau_drv.h"
  27 #include "drm.h"
  28 #include "drm_sarea.h"
  29 #include "drm_crtc_helper.h"
  30 #ifdef __linux__
  31 #include <linux/swab.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #endif
  36
  37 #include "pscnv_drm.h"
  38 #include "nouveau_reg.h"
  39 #include "nouveau_fbcon.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42 #include "pscnv_vm.h"
  43 #include "pscnv_chan.h"
  44 #include "pscnv_fifo.h"
  45 #include "pscnv_ioctl.h"
  46
  47 static void nouveau_stub_takedown(struct drm_device *dev) {}
  48 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  49
  50 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  51 {
  52         struct drm_nouveau_private *dev_priv = dev->dev_private;
  53         struct nouveau_engine *engine = &dev_priv->engine;
  54
  55         if (dev_priv->chipset < 0x10) {
  56                 engine->gpio.init               = nouveau_stub_init;
  57                 engine->gpio.takedown           = nouveau_stub_takedown;
  58                 engine->gpio.get                = NULL;
  59                 engine->gpio.set                = NULL;
  60                 engine->gpio.irq_enable         = NULL;
  61                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  62                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  63                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  64         } else if (dev_priv->chipset < 0x50 || (dev_priv->chipset & 0xf0) == 0x60) {
  65                 engine->gpio.init               = nouveau_stub_init;
  66                 engine->gpio.takedown           = nouveau_stub_takedown;
  67                 engine->gpio.get                = nv10_gpio_get;
  68                 engine->gpio.set                = nv10_gpio_set;
  69                 engine->gpio.irq_enable         = NULL;
  70                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  71                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  72                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  73         } else {
  74                 u32 chip = dev_priv->chipset;
  75                 if (chip >= 0xc0)
  76                         chip &= ~0xf;
  77                 engine->gpio.init               = nv50_gpio_init;
  78                 engine->gpio.takedown           = nouveau_stub_takedown;
  79                 engine->gpio.get                = nv50_gpio_get;
  80                 engine->gpio.set                = nv50_gpio_set;
  81                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
  82                 engine->pm.pwm_get              = nv50_pm_pwm_get;
  83                 engine->pm.pwm_set              = nv50_pm_pwm_set;
  84                 engine->pm.counter.init         = nv40_counter_init;
  85                 engine->pm.counter.takedown     = nv40_counter_fini;
  86                 engine->pm.counter.watch        = nv40_counter_watch_signal;
  87                 engine->pm.counter.unwatch      = nv40_counter_unwatch_signal;
  88                 engine->pm.counter.poll         = nv40_counter_poll;
  89                 engine->pm.counter.start        = nv40_counter_start;
  90                 engine->pm.counter.stop         = nv40_counter_stop;
  91                 engine->pm.counter.signal_value = nv40_counter_value;
  92                 switch (chip) {
  93                 case 0xa3:
  94                 case 0xa5:
  95                 case 0xa8:
  96                 case 0xaf:
  97                         engine->pm.clocks_get   = nva3_pm_clocks_get;
  98                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
  99                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 100                         break;
 101                 case 0xd0:
 102                         engine->gpio.get        = nvd0_gpio_get;
 103                         engine->gpio.set        = nvd0_gpio_set;
 104                         engine->pm.pwm_get      = NULL;
 105                         engine->pm.pwm_set      = NULL;
 106                 case 0xc0:
 107                         engine->pm.clocks_get           = nvc0_pm_clocks_get;
 108                         engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 109                         engine->pm.clocks_set           = nvc0_pm_clocks_set;
 110                         break;
 111                 default:
 112                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 113                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 114                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 115                         break;
 116                 }
 117         }
 118
 119         if (dev_priv->chipset < 0x40) {
 120                 // Missing
 121         } else if (dev_priv->chipset < 0x80) {
 122                 engine->pm.temp_get             = nv40_temp_get;
 123         } else {
 124                 engine->pm.temp_get             = nv84_temp_get;
 125         }
 126
 127         engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 128         engine->pm.voltage_set_range    = nouveau_voltage_gpio_set_range;
 129
 130         if (dev_priv->chipset < 0x50 || (dev_priv->chipset & 0xf0) == 0x60) {
 131 #if 0
 132                 engine->display.early_init      = nv04_display_early_init;
 133                 engine->display.late_takedown   = nv04_display_late_takedown;
 134                 engine->display.create          = nv04_display_create;
 135                 engine->display.init            = nv04_display_init;
 136                 engine->display.destroy         = nv04_display_destroy;
 137 #endif
 138                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 139                 return -ENOSYS;
 140         } else if (dev_priv->chipset < 0xd0) {
 141                 engine->display.early_init      = nv50_display_early_init;
 142                 engine->display.late_takedown   = nv50_display_late_takedown;
 143                 engine->display.create          = nv50_display_create;
 144                 engine->display.init            = nv50_display_init;
 145                 engine->display.destroy         = nv50_display_destroy;
 146         } else {
 147                 engine->display.early_init      = nouveau_stub_init;
 148                 engine->display.late_takedown   = nouveau_stub_takedown;
 149                 engine->display.create          = nvd0_display_create;
 150                 engine->display.init            = nvd0_display_init;
 151                 engine->display.destroy         = nvd0_display_destroy;
 152         }
 153
 154         return 0;
 155 }
 156
 157 #ifdef __linux__
 158 static unsigned int
 159 nouveau_vga_set_decode(void *priv, bool state)
 160 {
 161         struct drm_device *dev = priv;
 162         struct drm_nouveau_private *dev_priv = dev->dev_private;
 163
 164         if (dev_priv->chipset >= 0x40)
 165                 nv_wr32(dev, 0x88054, state);
 166         else
 167                 nv_wr32(dev, 0x1854, state);
 168
 169         if (state)
 170                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 171                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 172         else
 173                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 174 }
 175
 176 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 177                                          enum vga_switcheroo_state state)
 178 {
 179         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 180         if (state == VGA_SWITCHEROO_ON) {
 181                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 182                 nouveau_pci_resume(pdev);
 183         } else {
 184                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 185                 nouveau_pci_suspend(pdev, pmm);
 186         }
 187 }
 188
 189 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 190 {
 191         struct drm_device *dev = pci_get_drvdata(pdev);
 192         nouveau_fbcon_output_poll_changed(dev);
 193 }
 194
 195 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 196 {
 197         struct drm_device *dev = pci_get_drvdata(pdev);
 198         bool can_switch;
 199
 200         spin_lock(&dev->count_lock);
 201         can_switch = (dev->open_count == 0);
 202         spin_unlock(&dev->count_lock);
 203         return can_switch;
 204 }
 205 #endif
 206
 207 int
 208 nouveau_card_init(struct drm_device *dev)
 209 {
 210         struct drm_nouveau_private *dev_priv = dev->dev_private;
 211         struct nouveau_engine *engine;
 212         int ret;
 213         int i;
 214
 215         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 216
 217         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
 218                 return 0;
 219
 220         NV_INFO(dev, "Initializing card...\n");
 221
 222 #ifdef __linux__
 223         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 224 #ifdef PSCNV_KAPI_SWITCHEROO_REPROBE
 225         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 226                                                                    nouveau_switcheroo_can_switch);
 227 #else
 228         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 229                                                                    nouveau_switcheroo_reprobe,
 230                                                                    nouveau_switcheroo_can_switch);
 231 #endif
 232 #endif
 233
 234         dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
 235
 236         /* Initialise internal driver API hooks */
 237         ret = nouveau_init_engine_ptrs(dev);
 238         if (ret)
 239                 goto out;
 240         engine = &dev_priv->engine;
 241         spin_lock_init(&dev_priv->context_switch_lock);
 242
 243         /* Make the CRTCs and I2C buses accessible */
 244         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 245                 ret = engine->display.early_init(dev);
 246                 if (ret)
 247                         goto out;
 248         }
 249
 250         /* Parse BIOS tables / Run init tables if card not POSTed */
 251         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 252                 ret = nouveau_bios_init(dev);
 253                 if (ret)
 254                         goto out_display_early;
 255
 256                 /* workaround an odd issue on nvc1 by disabling the device's
 257                  * nosnoop capability.  hopefully won't cause issues until a
 258                  * better fix is found - assuming there is one...
 259                  */
 260                 if (dev_priv->chipset == 0xc1) {
 261                         nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 262                 }
 263         }
 264
 265         ret = pscnv_mem_init(dev);
 266         if (ret)
 267                 goto out_bios;
 268
 269         nouveau_pm_init(dev);
 270
 271         switch (dev_priv->card_type) {
 272                 case NV_50:
 273                         ret = nv50_chan_init(dev);
 274                         break;
 275                 case NV_D0:
 276                 case NV_C0:
 277                         ret = nvc0_chan_init(dev);
 278                         break;
 279                 default:
 280                         NV_ERROR(dev, "No CHAN implementation for NV%02x!\n", dev_priv->chipset);
 281                         ret = -ENOSYS;
 282         }
 283         if (ret)
 284                 goto out_vram;
 285
 286         switch (dev_priv->card_type) {
 287                 case NV_50:
 288                         ret = nv50_vm_init(dev);
 289                         break;
 290                 case NV_D0:
 291                 case NV_C0:
 292                         ret = nvc0_vm_init(dev);
 293                         break;
 294                 default:
 295                         NV_ERROR(dev, "No VM implementation for NV%02x!\n", dev_priv->chipset);
 296                         ret = -ENOSYS;
 297         }
 298         if (ret)
 299                 goto out_chan;
 300
 301         /* PMC */
 302         nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF);
 303
 304         /* PBUS */
 305         nv_wr32(dev, 0x1100, 0xFFFFFFFF);
 306         nv_wr32(dev, 0x1140, 0xFFFFFFFF);
 307
 308         /* PGPIO */
 309         ret = engine->gpio.init(dev);
 310         if (ret)
 311                 goto out_vm;
 312
 313         /* PTIMER */
 314         ret = nv04_timer_init(dev);
 315         if (ret)
 316                 goto out_gpio;
 317
 318         /* XXX: handle noaccel */
 319         switch (dev_priv->card_type) {
 320                 case NV_50:
 321                         /* PFIFO */
 322                         ret = nv50_fifo_init(dev);
 323                         if (!ret) {
 324                                 /* PGRAPH */
 325                                 nv50_graph_init(dev);
 326                         }
 327                         break;
 328                 case NV_D0:
 329                 case NV_C0:
 330                         /* PFIFO */
 331                         ret = nvc0_fifo_init(dev);
 332                         if (!ret) {
 333                                 /* PGRAPH */
 334                                 ret = nvc0_graph_init(dev);
 335                                 if (!ret && dev_priv->card_type == NV_C0) {
 336                                         /* PCOPY0 */
 337                                         nvc0_copy_init(dev, 0);
 338                                         /* PCOPY1 */
 339                                         nvc0_copy_init(dev, 1);
 340                                 }
 341                         }
 342                         break;
 343                 default:
 344                         break;
 345         }
 346         switch (dev_priv->chipset) {
 347                 case 0x84:
 348                 case 0x86:
 349                 case 0x92:
 350                 case 0x94:
 351                 case 0x96:
 352                 case 0xa0:
 353                         nv84_crypt_init(dev);
 354                         break;
 355                 case 0x98:
 356                 case 0xaa:
 357                 case 0xac:
 358                         nv98_crypt_init(dev);
 359                         break;
 360         }
 361
 362         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 363                 ret = nouveau_display_create(dev);
 364                 if (ret)
 365                         goto out_fifo;
 366         }
 367
 368         /* this call irq_preinstall, register irq handler and
 369          * call irq_postinstall
 370          */
 371 #ifdef __linux__
 372         ret = drm_irq_install(dev);
 373 #else
 374         // SIGH
 375         DRM_UNLOCK();
 376         ret = drm_irq_install(dev);
 377         DRM_LOCK();
 378 #endif
 379         if (ret)
 380                 goto out_display;
 381
 382         ret = drm_vblank_init(dev, 0);
 383         if (ret)
 384                 goto out_irq;
 385
 386         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 387 #if 0
 388         if (!engine->graph.accel_blocked) {
 389                 ret = nouveau_card_init_channel(dev);
 390                 if (ret)
 391                         goto out_irq;
 392         }
 393 #endif
 394
 395         ret = nouveau_backlight_init(dev);
 396         if (ret)
 397                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 398
 399         dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
 400
 401         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 402 #ifdef __linux__
 403                 nouveau_fbcon_init(dev);
 404 #else
 405                 // SIGH
 406                 DRM_UNLOCK();
 407                 nouveau_fbcon_init(dev);
 408                 DRM_LOCK();
 409 #endif
 410                 drm_kms_helper_poll_init(dev);
 411         }
 412
 413         NV_INFO(dev, "Card initialized.\n");
 414         return 0;
 415
 416 #if 0
 417 out_channel:
 418         if (dev_priv->channel) {
 419                 nouveau_channel_free(dev_priv->channel);
 420                 dev_priv->channel = NULL;
 421         }
 422 #endif
 423 out_irq:
 424         drm_irq_uninstall(dev);
 425 out_display:
 426         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 427                 nouveau_display_destroy(dev);
 428         }
 429 out_fifo:
 430         for (i = 0; i < PSCNV_ENGINES_NUM; i++)
 431                 if (dev_priv->engines[i]) {
 432                         dev_priv->engines[i]->takedown(dev_priv->engines[i]);
 433                         dev_priv->engines[i] = 0;
 434                 }
 435         if (dev_priv->fifo)
 436                 dev_priv->fifo->takedown(dev);
 437 out_gpio:
 438         engine->gpio.takedown(dev);
 439 out_vm:
 440         nv_wr32(dev, 0x1140, 0);
 441         dev_priv->vm->takedown(dev);
 442 out_chan:
 443         dev_priv->chan->takedown(dev);
 444         nouveau_pm_fini(dev);
 445 out_vram:
 446         pscnv_mem_takedown(dev);
 447 out_bios:
 448         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 449                 nouveau_bios_takedown(dev);
 450         }
 451 out_display_early:
 452         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 453                 engine->display.late_takedown(dev);
 454         }
 455 out:
 456 #ifdef __linux__
 457         vga_client_register(dev->pdev, NULL, NULL, NULL);
 458 #endif
 459         return ret;
 460 }
 461
 462 static void nouveau_card_takedown(struct drm_device *dev)
 463 {
 464         struct drm_nouveau_private *dev_priv = dev->dev_private;
 465         int i;
 466
 467         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 468
 469         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE) {
 470                 NV_INFO(dev, "Stopping card...\n");
 471                 nouveau_backlight_exit(dev);
 472                 drm_irq_uninstall(dev);
 473                 flush_workqueue(dev_priv->wq);
 474                 for (i = 0; i < PSCNV_ENGINES_NUM; i++)
 475                         if (dev_priv->engines[i]) {
 476                                 dev_priv->engines[i]->takedown(dev_priv->engines[i]);
 477                                 dev_priv->engines[i] = 0;
 478                         }
 479                 if (dev_priv->fifo)
 480                         dev_priv->fifo->takedown(dev);
 481                 dev_priv->vm->takedown(dev);
 482                 dev_priv->chan->takedown(dev);
 483                 pscnv_mem_takedown(dev);
 484                 nv_wr32(dev, 0x1140, 0);
 485                 nouveau_pm_fini(dev);
 486                 nouveau_bios_takedown(dev);
 487
 488 #ifdef __linux__
 489                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 490 #endif
 491                 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 492                 NV_INFO(dev, "Card stopped.\n");
 493         }
 494 }
 495
 496 /* here a client dies, release the stuff that was allocated for its
 497  * file_priv */
 498 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 499 {
 500         pscnv_chan_cleanup(dev, file_priv);
 501         pscnv_vspace_cleanup(dev, file_priv);
 502 }
 503
 504 /* first module load, setup the mmio/fb mapping */
 505 /* KMS: we need mmio at load time, not when the first drm client opens. */
 506 int nouveau_firstopen(struct drm_device *dev)
 507 {
 508         nouveau_card_init(dev);
 509         return 0;
 510 }
 511
 512 /* if we have an OF card, copy vbios to RAMIN */
 513 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 514 {
 515 #if defined(__powerpc__)
 516         int size, i;
 517         const uint32_t *bios;
 518         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 519         if (!dn) {
 520                 NV_INFO(dev, "Unable to get the OF node\n");
 521                 return;
 522         }
 523
 524         bios = of_get_property(dn, "NVDA,BMP", &size);
 525         if (bios) {
 526                 for (i = 0; i < size; i += 4)
 527                         nv_wi32(dev, i, bios[i/4]);
 528                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 529         } else {
 530                 NV_INFO(dev, "Unable to get the OF bios\n");
 531         }
 532 #endif
 533 }
 534
 535 #ifdef __linux__
 536 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 537 {
 538         struct pci_dev *pdev = dev->pdev;
 539         struct apertures_struct *aper = alloc_apertures(3);
 540         if (!aper)
 541                 return NULL;
 542
 543         aper->ranges[0].base = pci_resource_start(pdev, 1);
 544         aper->ranges[0].size = pci_resource_len(pdev, 1);
 545         aper->count = 1;
 546
 547         if (pci_resource_len(pdev, 2)) {
 548                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 549                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 550                 aper->count++;
 551         }
 552
 553         if (pci_resource_len(pdev, 3)) {
 554                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 555                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 556                 aper->count++;
 557         }
 558
 559         return aper;
 560 }
 561 #endif
 562
 563 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 564 {
 565 #ifdef __linux__
 566         struct drm_nouveau_private *dev_priv = dev->dev_private;
 567         bool primary = false;
 568         dev_priv->apertures = nouveau_get_apertures(dev);
 569         if (!dev_priv->apertures)
 570                 return -ENOMEM;
 571
 572 #ifdef CONFIG_X86
 573         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 574 #endif
 575
 576         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 577 #endif
 578         return 0;
 579 }
 580
 581 int nouveau_load(struct drm_device *dev, unsigned long flags)
 582 {
 583         struct drm_nouveau_private *dev_priv;
 584         uint32_t reg0, strap;
 585         resource_size_t mmio_start_offs;
 586         int ret;
 587
 588         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 589         if (!dev_priv)
 590                 return -ENOMEM;
 591         dev->dev_private = dev_priv;
 592         dev_priv->dev = dev;
 593
 594         dev_priv->flags = flags/* & NOUVEAU_FLAGS*/;
 595         dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 596
 597         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X\n",
 598                  dev->pci_vendor, dev->pci_device);
 599
 600         dev_priv->wq = create_workqueue("nouveau");
 601         if (!dev_priv->wq)
 602                 return -EINVAL;
 603
 604         /* resource 0 is mmio regs */
 605         /* resource 1 is linear FB */
 606         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 607         /* resource 6 is bios */
 608
 609         /* map the mmio regs */
 610         mmio_start_offs = drm_get_resource_start(dev, 0);
 611         ret = drm_addmap(dev, mmio_start_offs, 0x00800000, _DRM_REGISTERS,
 612             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio);
 613
 614         if (ret) {
 615                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 616                          "Please report your setup to " DRIVER_EMAIL "\n");
 617                 return ret;
 618         }
 619         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 620                                         (unsigned long long)mmio_start_offs);
 621
 622 #ifdef __BIG_ENDIAN
 623         /* Put the card in BE mode if it's not */
 624         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 625                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 626
 627         DRM_MEMORYBARRIER();
 628 #endif
 629
 630         /* Time to determine the card architecture */
 631         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 632
 633         /* We're dealing with >=NV10 */
 634         if ((reg0 & 0x0f000000) > 0) {
 635                 /* Bit 27-20 contain the architecture in hex */
 636                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 637         /* NV04 or NV05 */
 638         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 639                 if (reg0 & 0x00f00000)
 640                         dev_priv->chipset = 0x05;
 641                 else
 642                         dev_priv->chipset = 0x04;
 643         } else {
 644                 dev_priv->chipset = (reg0 & 0xf0000) >> 16;
 645                 if (dev_priv->chipset < 1 || dev_priv->chipset > 3)
 646                         dev_priv->chipset = 0xff;
 647         }
 648
 649         switch (dev_priv->chipset & 0xf0) {
 650         case 0x00:
 651                 if (dev_priv->chipset >= 4)
 652                         dev_priv->card_type = NV_04;
 653                 else
 654                         dev_priv->card_type = dev_priv->chipset;
 655                 break;
 656         case 0x10:
 657         case 0x20:
 658         case 0x30:
 659                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 660                 break;
 661         case 0x40:
 662         case 0x60:
 663                 dev_priv->card_type = NV_40;
 664                 break;
 665         case 0x50:
 666         case 0x80:
 667         case 0x90:
 668         case 0xa0:
 669                 dev_priv->card_type = NV_50;
 670                 break;
 671         case 0xc0:
 672                 dev_priv->card_type = NV_C0;
 673                 break;
 674         case 0xd0:
 675                 dev_priv->card_type = NV_D0;
 676                 break;
 677         default:
 678                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 679                 return -EINVAL;
 680         }
 681
 682         NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
 683                 dev_priv->card_type, reg0);
 684
 685         /* determine frequency of timing crystal */
 686         strap = nv_rd32(dev, 0x101000);
 687         if ( dev_priv->chipset < 0x17 ||
 688             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
 689                 strap &= 0x00000040;
 690         else
 691                 strap &= 0x00400040;
 692
 693         switch (strap) {
 694         case 0x00000000: dev_priv->crystal = 13500; break;
 695         case 0x00000040: dev_priv->crystal = 14318; break;
 696         case 0x00400000: dev_priv->crystal = 27000; break;
 697         case 0x00400040: dev_priv->crystal = 25000; break;
 698         }
 699
 700         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
 701
 702         dev_priv->fb_size = drm_get_resource_len(dev, 1);
 703         dev_priv->fb_phys = drm_get_resource_start(dev, 1);
 704         dev_priv->mmio_phys = drm_get_resource_start(dev, 0);
 705
 706         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 707                 int ret = nouveau_remove_conflicting_drivers(dev);
 708                 if (ret)
 709                         return ret;
 710         }
 711
 712         /* map larger RAMIN aperture on NV40 cards */
 713         if (dev_priv->card_type >= NV_40) {
 714                 int ramin_bar = 2;
 715                 if (drm_get_resource_len(dev, ramin_bar) < PAGE_SIZE)
 716                         ramin_bar = 3;
 717
 718                 dev_priv->ramin_size = drm_get_resource_len(dev, ramin_bar);
 719                 ret = drm_addmap(dev, drm_get_resource_start(dev, ramin_bar),
 720                                  dev_priv->ramin_size, _DRM_REGISTERS,
 721                                  _DRM_KERNEL | _DRM_DRIVER, &dev_priv->ramin);
 722                 if (ret) {
 723                         NV_ERROR(dev, "Failed to init RAMIN mapping\n");
 724                         return ret;
 725                 }
 726         }
 727
 728         nouveau_OF_copy_vbios_to_ramin(dev);
 729
 730         /* Special flags */
 731         if (dev->pci_device == 0x01a0)
 732                 dev_priv->flags |= NV_NFORCE;
 733         else if (dev->pci_device == 0x01f0)
 734                 dev_priv->flags |= NV_NFORCE2;
 735
 736         /* For kernel modesetting, init card now and bring up fbcon */
 737         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 738                 int ret = nouveau_card_init(dev);
 739                 if (ret)
 740                         return ret;
 741         }
 742
 743         return 0;
 744 }
 745
 746 static void nouveau_close(struct drm_device *dev)
 747 {
 748         struct drm_nouveau_private *dev_priv = dev->dev_private;
 749
 750         /* In the case of an error dev_priv may not be allocated yet */
 751         if (dev_priv)
 752                 nouveau_card_takedown(dev);
 753 }
 754
 755 /* KMS: we need mmio at load time, not when the first drm client opens. */
 756 void nouveau_lastclose(struct drm_device *dev)
 757 {
 758         if (drm_core_check_feature(dev, DRIVER_MODESET))
 759                 return;
 760
 761         nouveau_close(dev);
 762 }
 763
 764 int nouveau_unload(struct drm_device *dev)
 765 {
 766         struct drm_nouveau_private *dev_priv = dev->dev_private;
 767
 768         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 769                 nouveau_fbcon_fini(dev);
 770                 nouveau_display_destroy(dev);
 771                 nouveau_close(dev);
 772         }
 773         destroy_workqueue(dev_priv->wq);
 774
 775         drm_rmmap(dev, dev_priv->mmio);
 776         drm_rmmap(dev, dev_priv->ramin);
 777
 778         kfree(dev_priv);
 779         dev->dev_private = NULL;
 780         return 0;
 781 }
 782
 783 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
 784 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
 785                         uint32_t reg, uint32_t mask, uint32_t val)
 786 {
 787         uint64_t start = nv04_timer_read(dev);
 788
 789         do {
 790                 if ((nv_rd32(dev, reg) & mask) == val)
 791                         return true;
 792         } while (nv04_timer_read(dev) - start < timeout);
 793
 794         return false;
 795 }
 796
 797 /* Wait until (value(reg) & mask) != val, up until timeout has hit. */
 798 bool nouveau_wait_until_neq(struct drm_device *dev, uint64_t timeout,
 799                             uint32_t reg, uint32_t mask, uint32_t val)
 800 {
 801         uint64_t start = nv04_timer_read(dev);
 802
 803         do {
 804                 if ((nv_rd32(dev, reg) & mask) != val)
 805                         return true;
 806         } while (nv04_timer_read(dev) - start < timeout);
 807
 808         return false;
 809 }
 810
 811 bool
 812 nouveau_wait_cb(struct drm_device *dev, uint64_t timeout,
 813                 bool (*cond)(void *), void *data)
 814 {
 815         uint64_t start = nv04_timer_read(dev);
 816
 817         do {
 818                 if (cond(data) == true)
 819                         return true;
 820         } while (nv04_timer_read(dev) - start < timeout);
 821
 822         return false;
 823 }