pscnv/nouveau_dp.c

   1 /*
   2  * Copyright 2009 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25
  26 #include "nouveau_drv.h"
  27 #include "nouveau_reg.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_i2c.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_encoder.h"
  32
  33 static int
  34 auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
  35 {
  36         struct drm_device *dev = encoder->dev;
  37         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  38         struct nouveau_i2c_chan *auxch;
  39         int ret;
  40
  41         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
  42         if (!auxch)
  43                 return -ENODEV;
  44
  45         ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
  46         if (ret)
  47                 return ret;
  48
  49         return 0;
  50 }
  51
  52 static int
  53 auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
  54 {
  55         struct drm_device *dev = encoder->dev;
  56         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  57         struct nouveau_i2c_chan *auxch;
  58         int ret;
  59
  60         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
  61         if (!auxch)
  62                 return -ENODEV;
  63
  64         ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
  65         return ret;
  66 }
  67
  68 static int
  69 nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
  70 {
  71         struct drm_device *dev = encoder->dev;
  72         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  73         uint32_t tmp;
  74         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
  75
  76         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
  77         tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
  78                  NV50_SOR_DP_CTRL_LANE_MASK);
  79         tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
  80         if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  81                 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
  82         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
  83
  84         return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
  85 }
  86
  87 static int
  88 nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
  89 {
  90         struct drm_device *dev = encoder->dev;
  91         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  92         uint32_t tmp;
  93         int reg = 0x614300 + (nv_encoder->or * 0x800);
  94
  95         tmp  = nv_rd32(dev, reg);
  96         tmp &= 0xfff3ffff;
  97         if (cmd == DP_LINK_BW_2_7)
  98                 tmp |= 0x00040000;
  99         nv_wr32(dev, reg, tmp);
 100
 101         return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
 102 }
 103
 104 static int
 105 nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
 106 {
 107         struct drm_device *dev = encoder->dev;
 108         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 109         uint32_t tmp;
 110         uint8_t cmd;
 111         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
 112         int ret;
 113
 114         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 115         tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
 116         tmp |= (pattern << 24);
 117         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 118
 119         ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
 120         if (ret)
 121                 return ret;
 122         cmd &= ~DP_TRAINING_PATTERN_MASK;
 123         cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
 124         return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
 125 }
 126
 127 static int
 128 nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
 129 {
 130         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 131         struct drm_device *dev = encoder->dev;
 132         struct bit_displayport_encoder_table_entry *dpse;
 133         struct bit_displayport_encoder_table *dpe;
 134         int i, dpe_headerlen, max_vs = 0;
 135
 136         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 137         if (!dpe)
 138                 return false;
 139         dpse = (void *)((char *)dpe + dpe_headerlen);
 140
 141         for (i = 0; i < dpe_headerlen; i++, dpse++) {
 142                 if (dpse->vs_level > max_vs)
 143                         max_vs = dpse->vs_level;
 144         }
 145
 146         return max_vs;
 147 }
 148
 149 static int
 150 nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
 151 {
 152         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 153         struct drm_device *dev = encoder->dev;
 154         struct bit_displayport_encoder_table_entry *dpse;
 155         struct bit_displayport_encoder_table *dpe;
 156         int i, dpe_headerlen, max_pre = 0;
 157
 158         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 159         if (!dpe)
 160                 return false;
 161         dpse = (void *)((char *)dpe + dpe_headerlen);
 162
 163         for (i = 0; i < dpe_headerlen; i++, dpse++) {
 164                 if (dpse->vs_level != vs)
 165                         continue;
 166
 167                 if (dpse->pre_level > max_pre)
 168                         max_pre = dpse->pre_level;
 169         }
 170
 171         return max_pre;
 172 }
 173
 174 static bool
 175 nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
 176 {
 177         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 178         struct drm_device *dev = encoder->dev;
 179         struct bit_displayport_encoder_table_entry *dpse;
 180         struct bit_displayport_encoder_table *dpe;
 181         int ret, i, dpe_headerlen, vs = 0, pre = 0;
 182         uint8_t request[2];
 183
 184         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 185         if (!dpe)
 186                 return false;
 187         dpse = (void *)((char *)dpe + dpe_headerlen);
 188
 189         ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
 190         if (ret)
 191                 return false;
 192
 193         NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
 194
 195         /* Keep all lanes at the same level.. */
 196         for (i = 0; i < nv_encoder->dp.link_nr; i++) {
 197                 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
 198                 int lane_vs = lane_req & 3;
 199                 int lane_pre = (lane_req >> 2) & 3;
 200
 201                 if (lane_vs > vs)
 202                         vs = lane_vs;
 203                 if (lane_pre > pre)
 204                         pre = lane_pre;
 205         }
 206
 207         if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
 208                 vs  = nouveau_dp_max_voltage_swing(encoder);
 209                 vs |= 4;
 210         }
 211
 212         if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
 213                 pre  = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
 214                 pre |= 4;
 215         }
 216
 217         /* Update the configuration for all lanes.. */
 218         for (i = 0; i < nv_encoder->dp.link_nr; i++)
 219                 config[i] = (pre << 3) | vs;
 220
 221         return true;
 222 }
 223
 224 static bool
 225 nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
 226 {
 227         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 228         struct drm_device *dev = encoder->dev;
 229         struct bit_displayport_encoder_table_entry *dpse;
 230         struct bit_displayport_encoder_table *dpe;
 231         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
 232         int dpe_headerlen, ret, i;
 233
 234         NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
 235                  config[0], config[1], config[2], config[3]);
 236
 237         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 238         if (!dpe)
 239                 return false;
 240         dpse = (void *)((char *)dpe + dpe_headerlen);
 241
 242         for (i = 0; i < dpe->record_nr; i++, dpse++) {
 243                 if (dpse->vs_level == (config[0] & 3) &&
 244                     dpse->pre_level == ((config[0] >> 3) & 3))
 245                         break;
 246         }
 247         BUG_ON(i == dpe->record_nr);
 248
 249         for (i = 0; i < nv_encoder->dp.link_nr; i++) {
 250                 const int shift[4] = { 16, 8, 0, 24 };
 251                 uint32_t mask = 0xff << shift[i];
 252                 uint32_t reg0, reg1, reg2;
 253
 254                 reg0  = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
 255                 reg0 |= (dpse->reg0 << shift[i]);
 256                 reg1  = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
 257                 reg1 |= (dpse->reg1 << shift[i]);
 258                 reg2  = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
 259                 reg2 |= (dpse->reg2 << 8);
 260                 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
 261                 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
 262                 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
 263         }
 264
 265         ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
 266         if (ret)
 267                 return false;
 268
 269         return true;
 270 }
 271
 272 bool
 273 nouveau_dp_link_train(struct drm_encoder *encoder)
 274 {
 275         struct drm_device *dev = encoder->dev;
 276         struct drm_nouveau_private *dev_priv = dev->dev_private;
 277         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 278         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 279         struct nouveau_connector *nv_connector;
 280         struct bit_displayport_encoder_table *dpe;
 281         int dpe_headerlen;
 282         uint8_t config[4], status[3];
 283         bool cr_done, cr_max_vs, eq_done;
 284         int ret = 0, i, tries, voltage;
 285
 286         NV_DEBUG_KMS(dev, "link training!!\n");
 287
 288         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 289         if (!nv_connector)
 290                 return false;
 291
 292         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 293         if (!dpe) {
 294                 NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or);
 295                 return false;
 296         }
 297
 298         /* disable hotplug detect, this flips around on some panels during
 299          * link training.
 300          */
 301         pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
 302
 303         if (dpe->script0) {
 304                 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
 305                 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
 306                                             nv_encoder->dcb,
 307                                             nouveau_crtc(encoder->crtc)->index);
 308         }
 309
 310 train:
 311         cr_done = eq_done = false;
 312
 313         /* set link configuration */
 314         NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
 315                  nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
 316
 317         ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
 318         if (ret)
 319                 return false;
 320
 321         config[0] = nv_encoder->dp.link_nr;
 322         if (nv_encoder->dp.dpcd_version >= 0x11 &&
 323             nv_encoder->dp.enhanced_frame)
 324                 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 325
 326         ret = nouveau_dp_lane_count_set(encoder, config[0]);
 327         if (ret)
 328                 return false;
 329
 330         /* clock recovery */
 331         NV_DEBUG_KMS(dev, "\tbegin cr\n");
 332         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
 333         if (ret)
 334                 goto stop;
 335
 336         tries = 0;
 337         voltage = -1;
 338         memset(config, 0x00, sizeof(config));
 339         for (;;) {
 340                 if (!nouveau_dp_link_train_commit(encoder, config))
 341                         break;
 342
 343                 udelay(100);
 344
 345                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
 346                 if (ret)
 347                         break;
 348                 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
 349                          status[0], status[1]);
 350
 351                 cr_done = true;
 352                 cr_max_vs = false;
 353                 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
 354                         int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
 355
 356                         if (!(lane & DP_LANE_CR_DONE)) {
 357                                 cr_done = false;
 358                                 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
 359                                         cr_max_vs = true;
 360                                 break;
 361                         }
 362                 }
 363
 364                 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
 365                         voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 366                         tries = 0;
 367                 }
 368
 369                 if (cr_done || cr_max_vs || (++tries == 5))
 370                         break;
 371
 372                 if (!nouveau_dp_link_train_adjust(encoder, config))
 373                         break;
 374         }
 375
 376         if (!cr_done)
 377                 goto stop;
 378
 379         /* channel equalisation */
 380         NV_DEBUG_KMS(dev, "\tbegin eq\n");
 381         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
 382         if (ret)
 383                 goto stop;
 384
 385         for (tries = 0; tries <= 5; tries++) {
 386                 udelay(400);
 387
 388                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
 389                 if (ret)
 390                         break;
 391                 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
 392                          status[0], status[1]);
 393
 394                 eq_done = true;
 395                 if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
 396                         eq_done = false;
 397
 398                 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
 399                         int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
 400
 401                         if (!(lane & DP_LANE_CR_DONE)) {
 402                                 cr_done = false;
 403                                 break;
 404                         }
 405
 406                         if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
 407                             !(lane & DP_LANE_SYMBOL_LOCKED)) {
 408                                 eq_done = false;
 409                                 break;
 410                         }
 411                 }
 412
 413                 if (eq_done || !cr_done)
 414                         break;
 415
 416                 if (!nouveau_dp_link_train_adjust(encoder, config) ||
 417                     !nouveau_dp_link_train_commit(encoder, config))
 418                         break;
 419         }
 420
 421 stop:
 422         /* end link training */
 423         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
 424         if (ret)
 425                 return false;
 426
 427         /* retry at a lower setting, if possible */
 428         if (!ret && !(eq_done && cr_done)) {
 429                 NV_DEBUG_KMS(dev, "\twe failed\n");
 430                 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
 431                         NV_DEBUG_KMS(dev, "retry link training at low rate\n");
 432                         nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
 433                         goto train;
 434                 }
 435         }
 436
 437         if (dpe->script1) {
 438                 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
 439                 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
 440                                             nv_encoder->dcb,
 441                                             nouveau_crtc(encoder->crtc)->index);
 442         }
 443
 444         /* re-enable hotplug detect */
 445         pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true);
 446
 447         return eq_done;
 448 }
 449
 450 bool
 451 nouveau_dp_detect(struct drm_encoder *encoder)
 452 {
 453         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 454         struct drm_device *dev = encoder->dev;
 455         uint8_t dpcd[4];
 456         int ret;
 457
 458         ret = auxch_rd(encoder, 0x0000, dpcd, 4);
 459         if (ret)
 460                 return false;
 461
 462         NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
 463                       "display: link_bw %d, link_nr %d version 0x%02x\n",
 464                  nv_encoder->dcb->dpconf.link_bw,
 465                  nv_encoder->dcb->dpconf.link_nr,
 466                  dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
 467
 468         nv_encoder->dp.dpcd_version = dpcd[0];
 469
 470         nv_encoder->dp.link_bw = dpcd[1];
 471         if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
 472             !nv_encoder->dcb->dpconf.link_bw)
 473                 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
 474
 475         nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
 476         if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
 477                 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
 478
 479         nv_encoder->dp.enhanced_frame = (dpcd[2] & DP_ENHANCED_FRAME_CAP);
 480
 481         return true;
 482 }
 483
 484 int
 485 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
 486                  uint8_t *data, int data_nr)
 487 {
 488         struct drm_device *dev = auxch->dev;
 489         uint32_t tmp, ctrl, stat = 0, data32[4] = {};
 490         int ret = 0, i, index = auxch->rd;
 491
 492         NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
 493
 494         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
 495         nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
 496         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
 497         if (!(tmp & 0x01000000)) {
 498                 NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
 499                 ret = -EIO;
 500                 goto out;
 501         }
 502
 503         for (i = 0; i < 3; i++) {
 504                 tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
 505                 if (tmp & NV50_AUXCH_STAT_STATE_READY)
 506                         break;
 507                 udelay(100);
 508         }
 509
 510         if (i == 3) {
 511                 ret = -EBUSY;
 512                 goto out;
 513         }
 514
 515         if (!(cmd & 1)) {
 516                 memcpy(data32, data, data_nr);
 517                 for (i = 0; i < 4; i++) {
 518                         NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
 519                         nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
 520                 }
 521         }
 522
 523         nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
 524         ctrl  = nv_rd32(dev, NV50_AUXCH_CTRL(index));
 525         ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
 526         ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
 527         ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
 528
 529         for (i = 0; i < 16; i++) {
 530                 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
 531                 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
 532                 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
 533                 if (!nv_wait(dev, NV50_AUXCH_CTRL(index),
 534                              0x00010000, 0x00000000)) {
 535                         NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
 536                                  nv_rd32(dev, NV50_AUXCH_CTRL(index)));
 537                         ret = -EBUSY;
 538                         goto out;
 539                 }
 540
 541                 udelay(400);
 542
 543                 stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
 544                 if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
 545                             NV50_AUXCH_STAT_REPLY_AUX_DEFER)
 546                         break;
 547         }
 548
 549         if (i == 16) {
 550                 NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
 551                 ret = -EREMOTEIO;
 552                 goto out;
 553         }
 554
 555         if (cmd & 1) {
 556                 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
 557                         ret = -EREMOTEIO;
 558                         goto out;
 559                 }
 560
 561                 for (i = 0; i < 4; i++) {
 562                         data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
 563                         NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
 564                 }
 565                 memcpy(data, data32, data_nr);
 566         }
 567
 568 out:
 569         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
 570         nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
 571         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
 572         if (tmp & 0x01000000) {
 573                 NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
 574                 ret = -EIO;
 575         }
 576
 577         udelay(400);
 578
 579         return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
 580 }
 581
 582 #ifdef __linux__
 583
 584 static int
 585 nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 586 {
 587         struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
 588         struct drm_device *dev = auxch->dev;
 589         struct i2c_msg *msg = msgs;
 590         int ret, mcnt = num;
 591
 592         while (mcnt--) {
 593                 u8 remaining = msg->len;
 594                 u8 *ptr = msg->buf;
 595
 596                 while (remaining) {
 597                         u8 cnt = (remaining > 16) ? 16 : remaining;
 598                         u8 cmd;
 599
 600                         if (msg->flags & I2C_M_RD)
 601                                 cmd = AUX_I2C_READ;
 602                         else
 603                                 cmd = AUX_I2C_WRITE;
 604
 605                         if (mcnt || remaining > 16)
 606                                 cmd |= AUX_I2C_MOT;
 607
 608                         ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
 609                         if (ret < 0)
 610                                 return ret;
 611
 612                         switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
 613                         case NV50_AUXCH_STAT_REPLY_I2C_ACK:
 614                                 break;
 615                         case NV50_AUXCH_STAT_REPLY_I2C_NACK:
 616                                 return -EREMOTEIO;
 617                         case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
 618                                 udelay(100);
 619                                 continue;
 620                         default:
 621                                 NV_ERROR(dev, "bad auxch reply: 0x%08x\n", ret);
 622                                 return -EREMOTEIO;
 623                         }
 624
 625                         ptr += cnt;
 626                         remaining -= cnt;
 627                 }
 628
 629                 msg++;
 630         }
 631
 632         return num;
 633 }
 634
 635 static u32
 636 nouveau_dp_i2c_func(struct i2c_adapter *adap)
 637 {
 638         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 639 }
 640
 641 const struct i2c_algorithm nouveau_dp_i2c_algo = {
 642         .master_xfer = nouveau_dp_i2c_xfer,
 643         .functionality = nouveau_dp_i2c_func
 644 };
 645
 646 #endif