pscnv/nouveau_hw.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  * Copyright 2007-2009 Stuart Bennett
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  20  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  21  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "nouveau_drv.h"
  26 #include "nouveau_hw.h"
  27
  28 #define CHIPSET_NFORCE 0x01a0
  29 #define CHIPSET_NFORCE2 0x01f0
  30
  31 /*
  32  * misc hw access wrappers/control functions
  33  */
  34
  35 void
  36 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
  37 {
  38         NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
  39         NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
  40 }
  41
  42 uint8_t
  43 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
  44 {
  45         NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
  46         return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
  47 }
  48
  49 void
  50 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
  51 {
  52         NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
  53         NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
  54 }
  55
  56 uint8_t
  57 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
  58 {
  59         NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
  60         return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
  61 }
  62
  63 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
  64  * it affects only the 8 bit vga io regs, which we access using mmio at
  65  * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
  66  * in general, the set value of cr44 does not matter: reg access works as
  67  * expected and values can be set for the appropriate head by using a 0x2000
  68  * offset as required
  69  * however:
  70  * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
  71  *    cr44 must be set to 0 or 3 for accessing values on the correct head
  72  *    through the common 0xc03c* addresses
  73  * b) in tied mode (4) head B is programmed to the values set on head A, and
  74  *    access using the head B addresses can have strange results, ergo we leave
  75  *    tied mode in init once we know to what cr44 should be restored on exit
  76  *
  77  * the owner parameter is slightly abused:
  78  * 0 and 1 are treated as head values and so the set value is (owner * 3)
  79  * other values are treated as literal values to set
  80  */
  81 void
  82 NVSetOwner(struct drm_device *dev, int owner)
  83 {
  84         struct drm_nouveau_private *dev_priv = dev->dev_private;
  85
  86         if (owner == 1)
  87                 owner *= 3;
  88
  89         if (dev_priv->chipset == 0x11) {
  90                 /* This might seem stupid, but the blob does it and
  91                  * omitting it often locks the system up.
  92                  */
  93                 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
  94                 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
  95         }
  96
  97         /* CR44 is always changed on CRTC0 */
  98         NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
  99
 100         if (dev_priv->chipset == 0x11) {        /* set me harder */
 101                 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
 102                 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
 103         }
 104 }
 105
 106 void
 107 NVBlankScreen(struct drm_device *dev, int head, bool blank)
 108 {
 109         unsigned char seq1;
 110
 111         if (nv_two_heads(dev))
 112                 NVSetOwner(dev, head);
 113
 114         seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
 115
 116         NVVgaSeqReset(dev, head, true);
 117         if (blank)
 118                 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
 119         else
 120                 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
 121         NVVgaSeqReset(dev, head, false);
 122 }
 123
 124 /*
 125  * PLL setting
 126  */
 127
 128 static int
 129 powerctrl_1_shift(int chip_version, int reg)
 130 {
 131         int shift = -4;
 132
 133         if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
 134                 return shift;
 135
 136         switch (reg) {
 137         case NV_RAMDAC_VPLL2:
 138                 shift += 4;
 139         case NV_PRAMDAC_VPLL_COEFF:
 140                 shift += 4;
 141         case NV_PRAMDAC_MPLL_COEFF:
 142                 shift += 4;
 143         case NV_PRAMDAC_NVPLL_COEFF:
 144                 shift += 4;
 145         }
 146
 147         /*
 148          * the shift for vpll regs is only used for nv3x chips with a single
 149          * stage pll
 150          */
 151         if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
 152                           chip_version == 0x36 || chip_version >= 0x40))
 153                 shift = -4;
 154
 155         return shift;
 156 }
 157
 158 static void
 159 setPLL_single(struct drm_device *dev, uint32_t reg, struct nouveau_pll_vals *pv)
 160 {
 161         struct drm_nouveau_private *dev_priv = dev->dev_private;
 162         int chip_version = dev_priv->vbios.chip_version;
 163         uint32_t oldpll = NVReadRAMDAC(dev, 0, reg);
 164         int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
 165         uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
 166         uint32_t saved_powerctrl_1 = 0;
 167         int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
 168
 169         if (oldpll == pll)
 170                 return; /* already set */
 171
 172         if (shift_powerctrl_1 >= 0) {
 173                 saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
 174                 nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
 175                         (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
 176                         1 << shift_powerctrl_1);
 177         }
 178
 179         if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
 180                 /* upclock -- write new post divider first */
 181                 NVWriteRAMDAC(dev, 0, reg, pv->log2P << 16 | (oldpll & 0xffff));
 182         else
 183                 /* downclock -- write new NM first */
 184                 NVWriteRAMDAC(dev, 0, reg, (oldpll & 0xffff0000) | pv->NM1);
 185
 186         if (chip_version < 0x17 && chip_version != 0x11)
 187                 /* wait a bit on older chips */
 188                 msleep(64);
 189         NVReadRAMDAC(dev, 0, reg);
 190
 191         /* then write the other half as well */
 192         NVWriteRAMDAC(dev, 0, reg, pll);
 193
 194         if (shift_powerctrl_1 >= 0)
 195                 nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
 196 }
 197
 198 static uint32_t
 199 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
 200 {
 201         bool head_a = (reg1 == NV_PRAMDAC_VPLL_COEFF);
 202
 203         if (ss) /* single stage pll mode */
 204                 ramdac580 |= head_a ? NV_RAMDAC_580_VPLL1_ACTIVE :
 205                                       NV_RAMDAC_580_VPLL2_ACTIVE;
 206         else
 207                 ramdac580 &= head_a ? ~NV_RAMDAC_580_VPLL1_ACTIVE :
 208                                       ~NV_RAMDAC_580_VPLL2_ACTIVE;
 209
 210         return ramdac580;
 211 }
 212
 213 static void
 214 setPLL_double_highregs(struct drm_device *dev, uint32_t reg1,
 215                        struct nouveau_pll_vals *pv)
 216 {
 217         struct drm_nouveau_private *dev_priv = dev->dev_private;
 218         int chip_version = dev_priv->vbios.chip_version;
 219         bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
 220         uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
 221         uint32_t oldpll1 = NVReadRAMDAC(dev, 0, reg1);
 222         uint32_t oldpll2 = !nv3035 ? NVReadRAMDAC(dev, 0, reg2) : 0;
 223         uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
 224         uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
 225         uint32_t oldramdac580 = 0, ramdac580 = 0;
 226         bool single_stage = !pv->NM2 || pv->N2 == pv->M2;       /* nv41+ only */
 227         uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
 228         int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
 229
 230         /* model specific additions to generic pll1 and pll2 set up above */
 231         if (nv3035) {
 232                 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
 233                        (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
 234                 pll2 = 0;
 235         }
 236         if (chip_version > 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { /* !nv40 */
 237                 oldramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
 238                 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
 239                 if (oldramdac580 != ramdac580)
 240                         oldpll1 = ~0;   /* force mismatch */
 241                 if (single_stage)
 242                         /* magic value used by nvidia in single stage mode */
 243                         pll2 |= 0x011f;
 244         }
 245         if (chip_version > 0x70)
 246                 /* magic bits set by the blob (but not the bios) on g71-73 */
 247                 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
 248
 249         if (oldpll1 == pll1 && oldpll2 == pll2)
 250                 return; /* already set */
 251
 252         if (shift_powerctrl_1 >= 0) {
 253                 saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
 254                 nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
 255                         (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
 256                         1 << shift_powerctrl_1);
 257         }
 258
 259         if (chip_version >= 0x40) {
 260                 int shift_c040 = 14;
 261
 262                 switch (reg1) {
 263                 case NV_PRAMDAC_MPLL_COEFF:
 264                         shift_c040 += 2;
 265                 case NV_PRAMDAC_NVPLL_COEFF:
 266                         shift_c040 += 2;
 267                 case NV_RAMDAC_VPLL2:
 268                         shift_c040 += 2;
 269                 case NV_PRAMDAC_VPLL_COEFF:
 270                         shift_c040 += 2;
 271                 }
 272
 273                 savedc040 = nvReadMC(dev, 0xc040);
 274                 if (shift_c040 != 14)
 275                         nvWriteMC(dev, 0xc040, savedc040 & ~(3 << shift_c040));
 276         }
 277
 278         if (oldramdac580 != ramdac580)
 279                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_580, ramdac580);
 280
 281         if (!nv3035)
 282                 NVWriteRAMDAC(dev, 0, reg2, pll2);
 283         NVWriteRAMDAC(dev, 0, reg1, pll1);
 284
 285         if (shift_powerctrl_1 >= 0)
 286                 nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
 287         if (chip_version >= 0x40)
 288                 nvWriteMC(dev, 0xc040, savedc040);
 289 }
 290
 291 static void
 292 setPLL_double_lowregs(struct drm_device *dev, uint32_t NMNMreg,
 293                       struct nouveau_pll_vals *pv)
 294 {
 295         /* When setting PLLs, there is a merry game of disabling and enabling
 296          * various bits of hardware during the process. This function is a
 297          * synthesis of six nv4x traces, nearly each card doing a subtly
 298          * different thing. With luck all the necessary bits for each card are
 299          * combined herein. Without luck it deviates from each card's formula
 300          * so as to not work on any :)
 301          */
 302
 303         uint32_t Preg = NMNMreg - 4;
 304         bool mpll = Preg == 0x4020;
 305         uint32_t oldPval = nvReadMC(dev, Preg);
 306         uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
 307         uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
 308                         0xc << 28 | pv->log2P << 16;
 309         uint32_t saved4600 = 0;
 310         /* some cards have different maskc040s */
 311         uint32_t maskc040 = ~(3 << 14), savedc040;
 312         bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
 313
 314         if (nvReadMC(dev, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
 315                 return;
 316
 317         if (Preg == 0x4000)
 318                 maskc040 = ~0x333;
 319         if (Preg == 0x4058)
 320                 maskc040 = ~(0xc << 24);
 321
 322         if (mpll) {
 323                 struct pll_lims pll_lim;
 324                 uint8_t Pval2;
 325
 326                 if (get_pll_limits(dev, Preg, &pll_lim))
 327                         return;
 328
 329                 Pval2 = pv->log2P + pll_lim.log2p_bias;
 330                 if (Pval2 > pll_lim.max_log2p)
 331                         Pval2 = pll_lim.max_log2p;
 332                 Pval |= 1 << 28 | Pval2 << 20;
 333
 334                 saved4600 = nvReadMC(dev, 0x4600);
 335                 nvWriteMC(dev, 0x4600, saved4600 | 8 << 28);
 336         }
 337         if (single_stage)
 338                 Pval |= mpll ? 1 << 12 : 1 << 8;
 339
 340         nvWriteMC(dev, Preg, oldPval | 1 << 28);
 341         nvWriteMC(dev, Preg, Pval & ~(4 << 28));
 342         if (mpll) {
 343                 Pval |= 8 << 20;
 344                 nvWriteMC(dev, 0x4020, Pval & ~(0xc << 28));
 345                 nvWriteMC(dev, 0x4038, Pval & ~(0xc << 28));
 346         }
 347
 348         savedc040 = nvReadMC(dev, 0xc040);
 349         nvWriteMC(dev, 0xc040, savedc040 & maskc040);
 350
 351         nvWriteMC(dev, NMNMreg, NMNM);
 352         if (NMNMreg == 0x4024)
 353                 nvWriteMC(dev, 0x403c, NMNM);
 354
 355         nvWriteMC(dev, Preg, Pval);
 356         if (mpll) {
 357                 Pval &= ~(8 << 20);
 358                 nvWriteMC(dev, 0x4020, Pval);
 359                 nvWriteMC(dev, 0x4038, Pval);
 360                 nvWriteMC(dev, 0x4600, saved4600);
 361         }
 362
 363         nvWriteMC(dev, 0xc040, savedc040);
 364
 365         if (mpll) {
 366                 nvWriteMC(dev, 0x4020, Pval & ~(1 << 28));
 367                 nvWriteMC(dev, 0x4038, Pval & ~(1 << 28));
 368         }
 369 }
 370
 371 void
 372 nouveau_hw_setpll(struct drm_device *dev, uint32_t reg1,
 373                   struct nouveau_pll_vals *pv)
 374 {
 375         struct drm_nouveau_private *dev_priv = dev->dev_private;
 376         int cv = dev_priv->vbios.chip_version;
 377
 378         if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
 379             cv >= 0x40) {
 380                 if (reg1 > 0x405c)
 381                         setPLL_double_highregs(dev, reg1, pv);
 382                 else
 383                         setPLL_double_lowregs(dev, reg1, pv);
 384         } else
 385                 setPLL_single(dev, reg1, pv);
 386 }
 387
 388 /*
 389  * PLL getting
 390  */
 391
 392 static void
 393 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
 394                       uint32_t pll2, struct nouveau_pll_vals *pllvals)
 395 {
 396         struct drm_nouveau_private *dev_priv = dev->dev_private;
 397
 398         /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
 399
 400         /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
 401         pllvals->log2P = (pll1 >> 16) & 0x7;
 402         pllvals->N2 = pllvals->M2 = 1;
 403
 404         if (reg1 <= 0x405c) {
 405                 pllvals->NM1 = pll2 & 0xffff;
 406                 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
 407                 if (!(pll1 & 0x1100))
 408                         pllvals->NM2 = pll2 >> 16;
 409         } else {
 410                 pllvals->NM1 = pll1 & 0xffff;
 411                 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
 412                         pllvals->NM2 = pll2 & 0xffff;
 413                 else if (dev_priv->chipset == 0x30 || dev_priv->chipset == 0x35) {
 414                         pllvals->M1 &= 0xf; /* only 4 bits */
 415                         if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
 416                                 pllvals->M2 = (pll1 >> 4) & 0x7;
 417                                 pllvals->N2 = ((pll1 >> 21) & 0x18) |
 418                                               ((pll1 >> 19) & 0x7);
 419                         }
 420                 }
 421         }
 422 }
 423
 424 int
 425 nouveau_hw_get_pllvals(struct drm_device *dev, enum pll_types plltype,
 426                        struct nouveau_pll_vals *pllvals)
 427 {
 428         struct drm_nouveau_private *dev_priv = dev->dev_private;
 429         uint32_t reg1 = get_pll_register(dev, plltype), pll1, pll2 = 0;
 430         struct pll_lims pll_lim;
 431         int ret;
 432
 433         if (reg1 == 0)
 434                 return -ENOENT;
 435
 436         pll1 = nvReadMC(dev, reg1);
 437
 438         if (reg1 <= 0x405c)
 439                 pll2 = nvReadMC(dev, reg1 + 4);
 440         else if (nv_two_reg_pll(dev)) {
 441                 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
 442
 443                 pll2 = nvReadMC(dev, reg2);
 444         }
 445
 446         if (dev_priv->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
 447                 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
 448
 449                 /* check whether vpll has been forced into single stage mode */
 450                 if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
 451                         if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
 452                                 pll2 = 0;
 453                 } else
 454                         if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
 455                                 pll2 = 0;
 456         }
 457
 458         nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
 459
 460         ret = get_pll_limits(dev, plltype, &pll_lim);
 461         if (ret)
 462                 return ret;
 463
 464         pllvals->refclk = pll_lim.refclk;
 465
 466         return 0;
 467 }
 468
 469 int
 470 nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
 471 {
 472         /* Avoid divide by zero if called at an inappropriate time */
 473         if (!pv->M1 || !pv->M2)
 474                 return 0;
 475
 476         return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
 477 }
 478
 479 int
 480 nouveau_hw_get_clock(struct drm_device *dev, enum pll_types plltype)
 481 {
 482         struct nouveau_pll_vals pllvals;
 483         int ret;
 484
 485 #ifdef __linux__ // TODO?
 486         if (plltype == PLL_MEMORY &&
 487             (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) {
 488                 uint32_t mpllP;
 489
 490                 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
 491                 if (!mpllP)
 492                         mpllP = 4;
 493
 494                 return 400000 / mpllP;
 495         } else
 496         if (plltype == PLL_MEMORY &&
 497             (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) {
 498                 uint32_t clock;
 499
 500                 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
 501                 return clock;
 502         }
 503 #endif
 504
 505         ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
 506         if (ret)
 507                 return ret;
 508
 509         return nouveau_hw_pllvals_to_clk(&pllvals);
 510 }
 511
 512 static void
 513 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
 514 {
 515         /* the vpll on an unused head can come up with a random value, way
 516          * beyond the pll limits.  for some reason this causes the chip to
 517          * lock up when reading the dac palette regs, so set a valid pll here
 518          * when such a condition detected.  only seen on nv11 to date
 519          */
 520
 521         struct pll_lims pll_lim;
 522         struct nouveau_pll_vals pv;
 523         enum pll_types pll = head ? PLL_VPLL1 : PLL_VPLL0;
 524
 525         if (get_pll_limits(dev, pll, &pll_lim))
 526                 return;
 527         nouveau_hw_get_pllvals(dev, pll, &pv);
 528
 529         if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
 530             pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
 531             pv.log2P <= pll_lim.max_log2p)
 532                 return;
 533
 534         NV_WARN(dev, "VPLL %d outwith limits, attempting to fix\n", head + 1);
 535
 536         /* set lowest clock within static limits */
 537         pv.M1 = pll_lim.vco1.max_m;
 538         pv.N1 = pll_lim.vco1.min_n;
 539         pv.log2P = pll_lim.max_usable_log2p;
 540         nouveau_hw_setpll(dev, pll_lim.reg, &pv);
 541 }
 542
 543 /*
 544  * vga font save/restore
 545  */
 546
 547 static void nouveau_vga_font_io(struct drm_device *dev,
 548                                 struct drm_local_map *iovram,
 549                                 bool save, unsigned plane)
 550 {
 551         struct drm_nouveau_private *dev_priv = dev->dev_private;
 552         unsigned i;
 553
 554         NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
 555         NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
 556         for (i = 0; i < 16384; i++) {
 557                 if (save) {
 558                         dev_priv->saved_vga_font[plane][i] = DRM_READ32(iovram, i * 4);
 559                 } else {
 560                         DRM_WRITE32(iovram, i * 4, dev_priv->saved_vga_font[plane][i]);
 561                 }
 562         }
 563 }
 564
 565 void
 566 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
 567 {
 568         uint8_t misc, gr4, gr5, gr6, seq2, seq4;
 569         bool graphicsmode;
 570         unsigned plane;
 571         struct drm_local_map *iovram = NULL;
 572
 573         if (nv_two_heads(dev))
 574                 NVSetOwner(dev, 0);
 575
 576         NVSetEnablePalette(dev, 0, true);
 577         graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1;
 578         NVSetEnablePalette(dev, 0, false);
 579
 580         if (graphicsmode) /* graphics mode => framebuffer => no need to save */
 581                 return;
 582
 583         NV_INFO(dev, "%sing VGA fonts\n", save ? "Sav" : "Restor");
 584
 585         /* map first 64KiB of VRAM, holds VGA fonts etc */
 586         drm_addmap(dev, drm_get_resource_start(dev, 1), 65536, _DRM_FRAME_BUFFER, _DRM_KERNEL | _DRM_DRIVER, &iovram);
 587         if (!iovram) {
 588                 NV_ERROR(dev, "Failed to map VRAM, "
 589                                         "cannot save/restore VGA fonts.\n");
 590                 return;
 591         }
 592
 593         if (nv_two_heads(dev))
 594                 NVBlankScreen(dev, 1, true);
 595         NVBlankScreen(dev, 0, true);
 596
 597         /* save control regs */
 598         misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ);
 599         seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX);
 600         seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX);
 601         gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX);
 602         gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX);
 603         gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX);
 604
 605         NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67);
 606         NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
 607         NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0);
 608         NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5);
 609
 610         /* store font in planes 0..3 */
 611         for (plane = 0; plane < 4; plane++)
 612                 nouveau_vga_font_io(dev, iovram, save, plane);
 613
 614         /* restore control regs */
 615         NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc);
 616         NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
 617         NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5);
 618         NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6);
 619         NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
 620         NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
 621
 622         if (nv_two_heads(dev))
 623                 NVBlankScreen(dev, 1, false);
 624         NVBlankScreen(dev, 0, false);
 625
 626         drm_rmmap(dev, iovram);
 627 }
 628
 629 /*
 630  * mode state save/load
 631  */
 632
 633 static void
 634 rd_cio_state(struct drm_device *dev, int head,
 635              struct nv04_crtc_reg *crtcstate, int index)
 636 {
 637         crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
 638 }
 639
 640 static void
 641 wr_cio_state(struct drm_device *dev, int head,
 642              struct nv04_crtc_reg *crtcstate, int index)
 643 {
 644         NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
 645 }
 646
 647 static void
 648 nv_save_state_ramdac(struct drm_device *dev, int head,
 649                      struct nv04_mode_state *state)
 650 {
 651         struct drm_nouveau_private *dev_priv = dev->dev_private;
 652         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 653         int i;
 654
 655         if (dev_priv->card_type >= NV_10)
 656                 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
 657
 658         nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
 659         state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
 660         if (nv_two_heads(dev))
 661                 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
 662         if (dev_priv->chipset == 0x11)
 663                 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
 664
 665         regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
 666
 667         if (nv_gf4_disp_arch(dev))
 668                 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
 669         if (dev_priv->chipset >= 0x30)
 670                 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
 671
 672         regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
 673         regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
 674         regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
 675         regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
 676         regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
 677         regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
 678         regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
 679         regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
 680
 681         for (i = 0; i < 7; i++) {
 682                 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
 683                 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
 684                 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
 685         }
 686
 687         if (nv_gf4_disp_arch(dev)) {
 688                 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
 689                 for (i = 0; i < 3; i++) {
 690                         regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
 691                         regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
 692                 }
 693         }
 694
 695         regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 696         regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
 697         if (!nv_gf4_disp_arch(dev) && head == 0) {
 698                 /* early chips don't allow access to PRAMDAC_TMDS_* without
 699                  * the head A FPCLK on (nv11 even locks up) */
 700                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
 701                               ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
 702         }
 703         regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
 704         regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
 705
 706         regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
 707
 708         if (nv_gf4_disp_arch(dev))
 709                 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
 710
 711         if (dev_priv->card_type == NV_40) {
 712                 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
 713                 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
 714                 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
 715
 716                 for (i = 0; i < 38; i++)
 717                         regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
 718                                                          NV_PRAMDAC_CTV + 4*i);
 719         }
 720 }
 721
 722 static void
 723 nv_load_state_ramdac(struct drm_device *dev, int head,
 724                      struct nv04_mode_state *state)
 725 {
 726         struct drm_nouveau_private *dev_priv = dev->dev_private;
 727         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 728         uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
 729         int i;
 730
 731         if (dev_priv->card_type >= NV_10)
 732                 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
 733
 734         nouveau_hw_setpll(dev, pllreg, &regp->pllvals);
 735         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
 736         if (nv_two_heads(dev))
 737                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
 738         if (dev_priv->chipset == 0x11)
 739                 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
 740
 741         NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
 742
 743         if (nv_gf4_disp_arch(dev))
 744                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
 745         if (dev_priv->chipset >= 0x30)
 746                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
 747
 748         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
 749         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
 750         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
 751         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
 752         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
 753         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
 754         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
 755         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
 756
 757         for (i = 0; i < 7; i++) {
 758                 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
 759
 760                 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
 761                 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
 762         }
 763
 764         if (nv_gf4_disp_arch(dev)) {
 765                 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
 766                 for (i = 0; i < 3; i++) {
 767                         NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
 768                         NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
 769                 }
 770         }
 771
 772         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
 773         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
 774         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
 775         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
 776
 777         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
 778
 779         if (nv_gf4_disp_arch(dev))
 780                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
 781
 782         if (dev_priv->card_type == NV_40) {
 783                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
 784                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
 785                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
 786
 787                 for (i = 0; i < 38; i++)
 788                         NVWriteRAMDAC(dev, head,
 789                                       NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
 790         }
 791 }
 792
 793 static void
 794 nv_save_state_vga(struct drm_device *dev, int head,
 795                   struct nv04_mode_state *state)
 796 {
 797         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 798         int i;
 799
 800         regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
 801
 802         for (i = 0; i < 25; i++)
 803                 rd_cio_state(dev, head, regp, i);
 804
 805         NVSetEnablePalette(dev, head, true);
 806         for (i = 0; i < 21; i++)
 807                 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
 808         NVSetEnablePalette(dev, head, false);
 809
 810         for (i = 0; i < 9; i++)
 811                 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
 812
 813         for (i = 0; i < 5; i++)
 814                 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
 815 }
 816
 817 static void
 818 nv_load_state_vga(struct drm_device *dev, int head,
 819                   struct nv04_mode_state *state)
 820 {
 821         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 822         int i;
 823
 824         NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
 825
 826         for (i = 0; i < 5; i++)
 827                 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
 828
 829         nv_lock_vga_crtc_base(dev, head, false);
 830         for (i = 0; i < 25; i++)
 831                 wr_cio_state(dev, head, regp, i);
 832         nv_lock_vga_crtc_base(dev, head, true);
 833
 834         for (i = 0; i < 9; i++)
 835                 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
 836
 837         NVSetEnablePalette(dev, head, true);
 838         for (i = 0; i < 21; i++)
 839                 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
 840         NVSetEnablePalette(dev, head, false);
 841 }
 842
 843 static void
 844 nv_save_state_ext(struct drm_device *dev, int head,
 845                   struct nv04_mode_state *state)
 846 {
 847         struct drm_nouveau_private *dev_priv = dev->dev_private;
 848         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 849         int i;
 850
 851         rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
 852         rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
 853         rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
 854         rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
 855         rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
 856         rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
 857         rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
 858
 859         rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
 860         rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
 861         rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
 862
 863         if (dev_priv->card_type >= NV_20)
 864                 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
 865
 866         if (dev_priv->card_type >= NV_30)
 867                 rd_cio_state(dev, head, regp, 0x9f);
 868
 869         rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
 870         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
 871         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
 872         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
 873         rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
 874
 875         if (dev_priv->card_type >= NV_10) {
 876                 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
 877                 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
 878
 879                 if (dev_priv->card_type >= NV_30)
 880                         regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
 881
 882                 if (dev_priv->card_type == NV_40)
 883                         regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
 884
 885                 if (nv_two_heads(dev))
 886                         regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
 887                 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
 888         }
 889
 890         regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
 891
 892         rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
 893         rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
 894         if (dev_priv->card_type >= NV_10) {
 895                 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
 896                 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
 897                 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
 898                 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
 899         }
 900         /* NV11 and NV20 don't have this, they stop at 0x52. */
 901         if (nv_gf4_disp_arch(dev)) {
 902                 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
 903                 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
 904
 905                 for (i = 0; i < 0x10; i++)
 906                         regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
 907                 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
 908                 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
 909
 910                 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
 911                 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
 912         }
 913
 914         regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
 915 }
 916
 917 static void
 918 nv_load_state_ext(struct drm_device *dev, int head,
 919                   struct nv04_mode_state *state)
 920 {
 921         struct drm_nouveau_private *dev_priv = dev->dev_private;
 922         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 923         uint32_t reg900;
 924         int i;
 925
 926         if (dev_priv->card_type >= NV_10) {
 927                 if (nv_two_heads(dev))
 928                         /* setting ENGINE_CTRL (EC) *must* come before
 929                          * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
 930                          * EC that should not be overwritten by writing stale EC
 931                          */
 932                         NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
 933
 934                 nvWriteVIDEO(dev, NV_PVIDEO_STOP, 1);
 935                 nvWriteVIDEO(dev, NV_PVIDEO_INTR_EN, 0);
 936                 nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(0), 0);
 937                 nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(1), 0);
 938 #if 0
 939                 nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(0), dev_priv->fb_available_size - 1);
 940                 nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(1), dev_priv->fb_available_size - 1);
 941                 nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(0), dev_priv->fb_available_size - 1);
 942                 nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(1), dev_priv->fb_available_size - 1);
 943 #endif
 944                 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
 945
 946                 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
 947                 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
 948                 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
 949
 950                 if (dev_priv->card_type >= NV_30)
 951                         NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
 952
 953                 if (dev_priv->card_type == NV_40) {
 954                         NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
 955
 956                         reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
 957                         if (regp->crtc_cfg == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
 958                                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
 959                         else
 960                                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
 961                 }
 962         }
 963
 964         NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
 965
 966         wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
 967         wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
 968         wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
 969         wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
 970         wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
 971         wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
 972         wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
 973         wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
 974         wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
 975
 976         if (dev_priv->card_type >= NV_20)
 977                 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
 978
 979         if (dev_priv->card_type >= NV_30)
 980                 wr_cio_state(dev, head, regp, 0x9f);
 981
 982         wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
 983         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
 984         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
 985         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
 986         if (dev_priv->card_type == NV_40)
 987                 nv_fix_nv40_hw_cursor(dev, head);
 988         wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
 989
 990         wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
 991         wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
 992         if (dev_priv->card_type >= NV_10) {
 993                 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
 994                 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
 995                 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
 996                 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
 997         }
 998         /* NV11 and NV20 stop at 0x52. */
 999         if (nv_gf4_disp_arch(dev)) {
1000                 if (dev_priv->card_type == NV_10) {
1001                         /* Not waiting for vertical retrace before modifying
1002                            CRE_53/CRE_54 causes lockups. */
1003                         nouveau_wait_until(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
1004                         nouveau_wait_until(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
1005                 }
1006
1007                 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
1008                 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
1009
1010                 for (i = 0; i < 0x10; i++)
1011                         NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
1012                 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
1013                 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
1014
1015                 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
1016                 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
1017         }
1018
1019         NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
1020
1021         /* Setting 1 on this value gives you interrupts for every vblank period. */
1022         NVWriteCRTC(dev, head, NV_PCRTC_INTR_EN_0, 0);
1023         NVWriteCRTC(dev, head, NV_PCRTC_INTR_0, NV_PCRTC_INTR_0_VBLANK);
1024 }
1025
1026 static void
1027 nv_save_state_palette(struct drm_device *dev, int head,
1028                       struct nv04_mode_state *state)
1029 {
1030         int head_offset = head * NV_PRMDIO_SIZE, i;
1031
1032         nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
1033                                 NV_PRMDIO_PIXEL_MASK_MASK);
1034         nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
1035
1036         for (i = 0; i < 768; i++) {
1037                 state->crtc_reg[head].DAC[i] = nv_rd08(dev,
1038                                 NV_PRMDIO_PALETTE_DATA + head_offset);
1039         }
1040
1041         NVSetEnablePalette(dev, head, false);
1042 }
1043
1044 void
1045 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
1046                               struct nv04_mode_state *state)
1047 {
1048         int head_offset = head * NV_PRMDIO_SIZE, i;
1049
1050         nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
1051                                 NV_PRMDIO_PIXEL_MASK_MASK);
1052         nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
1053
1054         for (i = 0; i < 768; i++) {
1055                 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA + head_offset,
1056                                 state->crtc_reg[head].DAC[i]);
1057         }
1058
1059         NVSetEnablePalette(dev, head, false);
1060 }
1061
1062 void nouveau_hw_save_state(struct drm_device *dev, int head,
1063                            struct nv04_mode_state *state)
1064 {
1065         struct drm_nouveau_private *dev_priv = dev->dev_private;
1066
1067         if (dev_priv->chipset == 0x11)
1068                 /* NB: no attempt is made to restore the bad pll later on */
1069                 nouveau_hw_fix_bad_vpll(dev, head);
1070         nv_save_state_ramdac(dev, head, state);
1071         nv_save_state_vga(dev, head, state);
1072         nv_save_state_palette(dev, head, state);
1073         nv_save_state_ext(dev, head, state);
1074 }
1075
1076 void nouveau_hw_load_state(struct drm_device *dev, int head,
1077                            struct nv04_mode_state *state)
1078 {
1079         NVVgaProtect(dev, head, true);
1080         nv_load_state_ramdac(dev, head, state);
1081         nv_load_state_ext(dev, head, state);
1082         nouveau_hw_load_state_palette(dev, head, state);
1083         nv_load_state_vga(dev, head, state);
1084         NVVgaProtect(dev, head, false);
1085 }