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[pscnv.git] / pscnv / nouveau_irq.c
blob2d8c199e2e89cd22877e63df6bf57ebafa4713b1
1 /*
2 * Copyright (C) 2006 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /*
29 * Authors:
30 * Ben Skeggs <darktama@iinet.net.au>
31 */
32
33 #include "drm.h"
34 #include "pscnv_drm.h"
35 #include "nouveau_drv.h"
36 #include "nouveau_reg.h"
37
38 /* needed for hotplug irq */
39 #include "nouveau_connector.h"
40 #include "nv50_display.h"
41 #include "pscnv_engine.h"
42 #include "pscnv_fifo.h"
43
44 void
45 nouveau_irq_preinstall(struct drm_device *dev)
46 {
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48
49 /* Master disable */
50 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
51
52 if (dev_priv->card_type >= NV_50) {
53 if (dev_priv->card_type < NV_D0)
54 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
55 else
56 INIT_WORK(&dev_priv->irq_work, nvd0_display_bh);
57 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
58 // INIT_LIST_HEAD(&dev_priv->vbl_waiting);
59 }
60 }
61
62 int
63 nouveau_irq_postinstall(struct drm_device *dev)
64 {
65 /* Master enable */
66 nv_wr32(dev, NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
67 return 0;
68 }
69
70 void
71 nouveau_irq_uninstall(struct drm_device *dev)
72 {
73 /* Master disable */
74 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
75 }
76
77 #if 0
78 #include <linux/ratelimit.h>
79
80 static DEFINE_RATELIMIT_STATE(nouveau_ratelimit_state, 3 * HZ, 20);
81
82 static inline int nouveau_ratelimit(void)
83 {
84 return __ratelimit(&nouveau_ratelimit_state);
85 }
86
87 static int
88 nouveau_call_method(struct nouveau_channel *chan, int class, int mthd, int data)
89 {
90 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
91 struct nouveau_pgraph_object_method *grm;
92 struct nouveau_pgraph_object_class *grc;
93
94 grc = dev_priv->engine.graph.grclass;
95 while (grc->id) {
96 if (grc->id == class)
97 break;
98 grc++;
99 }
100
101 if (grc->id != class || !grc->methods)
102 return -ENOENT;
103
104 grm = grc->methods;
105 while (grm->id) {
106 if (grm->id == mthd)
107 return grm->exec(chan, class, mthd, data);
108 grm++;
109 }
110
111 return -ENOENT;
112 }
113
114 static bool
115 nouveau_fifo_swmthd(struct nouveau_channel *chan, uint32_t addr, uint32_t data)
116 {
117 struct drm_device *dev = chan->dev;
118 const int subc = (addr >> 13) & 0x7;
119 const int mthd = addr & 0x1ffc;
120
121 if (mthd == 0x0000) {
122 struct nouveau_gpuobj_ref *ref = NULL;
123
124 if (nouveau_gpuobj_ref_find(chan, data, &ref))
125 return false;
126
127 if (ref->gpuobj->engine != NVOBJ_ENGINE_SW)
128 return false;
129
130 chan->sw_subchannel[subc] = ref->gpuobj->class;
131 nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_rd32(dev,
132 NV04_PFIFO_CACHE1_ENGINE) & ~(0xf << subc * 4));
133 return true;
134 }
135
136 /* hw object */
137 if (nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE) & (1 << (subc*4)))
138 return false;
139
140 if (nouveau_call_method(chan, chan->sw_subchannel[subc], mthd, data))
141 return false;
142
143 return true;
144 }
145
146 static void
147 nouveau_fifo_irq_handler(struct drm_device *dev)
148 {
149 struct drm_nouveau_private *dev_priv = dev->dev_private;
150 struct nouveau_engine *engine = &dev_priv->engine;
151 uint32_t status, reassign;
152 int cnt = 0;
153
154 reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
155 while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
156 struct nouveau_channel *chan = NULL;
157 uint32_t chid, get;
158
159 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
160
161 chid = engine->fifo.channel_id(dev);
162 if (chid >= 0 && chid < engine->fifo.channels)
163 chan = dev_priv->fifos[chid];
164 get = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
165
166 if (status & NV_PFIFO_INTR_CACHE_ERROR) {
167 uint32_t mthd, data;
168 int ptr;
169
170 /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
171 * wrapping on my G80 chips, but CACHE1 isn't big
172 * enough for this much data.. Tests show that it
173 * wraps around to the start at GET=0x800.. No clue
174 * as to why..
175 */
176 ptr = (get & 0x7ff) >> 2;
177
178 if (dev_priv->card_type < NV_40) {
179 mthd = nv_rd32(dev,
180 NV04_PFIFO_CACHE1_METHOD(ptr));
181 data = nv_rd32(dev,
182 NV04_PFIFO_CACHE1_DATA(ptr));
183 } else {
184 mthd = nv_rd32(dev,
185 NV40_PFIFO_CACHE1_METHOD(ptr));
186 data = nv_rd32(dev,
187 NV40_PFIFO_CACHE1_DATA(ptr));
188 }
189
190 if (!chan || !nouveau_fifo_swmthd(chan, mthd, data)) {
191 NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
192 "Mthd 0x%04x Data 0x%08x\n",
193 chid, (mthd >> 13) & 7, mthd & 0x1ffc,
194 data);
195 }
196
197 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
198 nv_wr32(dev, NV03_PFIFO_INTR_0,
199 NV_PFIFO_INTR_CACHE_ERROR);
200
201 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
202 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
203 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
204 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
205 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
206 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
207
208 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
209 nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
210 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
211
212 status &= ~NV_PFIFO_INTR_CACHE_ERROR;
213 }
214
215 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
216 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d\n", chid);
217
218 status &= ~NV_PFIFO_INTR_DMA_PUSHER;
219 nv_wr32(dev, NV03_PFIFO_INTR_0,
220 NV_PFIFO_INTR_DMA_PUSHER);
221
222 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
223 if (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT) != get)
224 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET,
225 get + 4);
226 }
227
228 if (status & NV_PFIFO_INTR_SEMAPHORE) {
229 uint32_t sem;
230
231 status &= ~NV_PFIFO_INTR_SEMAPHORE;
232 nv_wr32(dev, NV03_PFIFO_INTR_0,
233 NV_PFIFO_INTR_SEMAPHORE);
234
235 sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
236 nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
237
238 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
239 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
240 }
241
242 if (status) {
243 NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
244 status, chid);
245 nv_wr32(dev, NV03_PFIFO_INTR_0, status);
246 status = 0;
247 }
248
249 nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
250 }
251
252 if (status) {
253 NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
254 nv_wr32(dev, 0x2140, 0);
255 nv_wr32(dev, 0x140, 0);
256 }
257
258 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
259 }
260
261 struct nouveau_bitfield_names {
262 uint32_t mask;
263 const char *name;
264 };
265
266 static struct nouveau_bitfield_names nstatus_names[] =
267 {
268 { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
269 { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
270 { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
271 { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }
272 };
273
274 static struct nouveau_bitfield_names nstatus_names_nv10[] =
275 {
276 { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
277 { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
278 { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
279 { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }
280 };
281
282 static struct nouveau_bitfield_names nsource_names[] =
283 {
284 { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
285 { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
286 { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
287 { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
288 { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
289 { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
290 { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
291 { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
292 { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
293 { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
294 { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
295 { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
296 { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
297 { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
298 { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
299 { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
300 { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
301 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
302 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
303 };
304
305 static void
306 nouveau_print_bitfield_names_(uint32_t value,
307 const struct nouveau_bitfield_names *namelist,
308 const int namelist_len)
309 {
310 /*
311 * Caller must have already printed the KERN_* log level for us.
312 * Also the caller is responsible for adding the newline.
313 */
314 int i;
315 for (i = 0; i < namelist_len; ++i) {
316 uint32_t mask = namelist[i].mask;
317 if (value & mask) {
318 printk(" %s", namelist[i].name);
319 value &= ~mask;
320 }
321 }
322 if (value)
323 printk(" (unknown bits 0x%08x)", value);
324 }
325 #define nouveau_print_bitfield_names(val, namelist) \
326 nouveau_print_bitfield_names_((val), (namelist), DRM_ARRAY_SIZE(namelist))
327
328 struct nouveau_enum_names {
329 uint32_t value;
330 const char *name;
331 };
332
333 static void
334 nouveau_print_enum_names_(uint32_t value,
335 const struct nouveau_enum_names *namelist,
336 const int namelist_len)
337 {
338 /*
339 * Caller must have already printed the KERN_* log level for us.
340 * Also the caller is responsible for adding the newline.
341 */
342 int i;
343 for (i = 0; i < namelist_len; ++i) {
344 if (value == namelist[i].value) {
345 printk("%s", namelist[i].name);
346 return;
347 }
348 }
349 printk("unknown value 0x%08x", value);
350 }
351 #define nouveau_print_enum_names(val, namelist) \
352 nouveau_print_enum_names_((val), (namelist), DRM_ARRAY_SIZE(namelist))
353
354 static int
355 nouveau_graph_chid_from_grctx(struct drm_device *dev)
356 {
357 struct drm_nouveau_private *dev_priv = dev->dev_private;
358 uint32_t inst;
359 int i;
360
361 if (dev_priv->card_type < NV_40)
362 return dev_priv->engine.fifo.channels;
363 else
364 if (dev_priv->card_type < NV_50) {
365 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 4;
366
367 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
368 struct nouveau_channel *chan = dev_priv->fifos[i];
369
370 if (!chan || !chan->ramin_grctx)
371 continue;
372
373 if (inst == chan->ramin_grctx->instance)
374 break;
375 }
376 } else {
377 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 12;
378
379 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
380 struct nouveau_channel *chan = dev_priv->fifos[i];
381
382 if (!chan || !chan->ramin)
383 continue;
384
385 if (inst == chan->ramin->instance)
386 break;
387 }
388 }
389
390
391 return i;
392 }
393
394 static int
395 nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
396 {
397 struct drm_nouveau_private *dev_priv = dev->dev_private;
398 struct nouveau_engine *engine = &dev_priv->engine;
399 int channel;
400
401 if (dev_priv->card_type < NV_10)
402 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
403 else
404 if (dev_priv->card_type < NV_40)
405 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
406 else
407 channel = nouveau_graph_chid_from_grctx(dev);
408
409 if (channel >= engine->fifo.channels || !dev_priv->fifos[channel]) {
410 NV_ERROR(dev, "AIII, invalid/inactive channel id %d\n", channel);
411 return -EINVAL;
412 }
413
414 *channel_ret = channel;
415 return 0;
416 }
417
418 struct nouveau_pgraph_trap {
419 int channel;
420 int class;
421 int subc, mthd, size;
422 uint32_t data, data2;
423 uint32_t nsource, nstatus;
424 };
425
426 static void
427 nouveau_graph_trap_info(struct drm_device *dev,
428 struct nouveau_pgraph_trap *trap)
429 {
430 struct drm_nouveau_private *dev_priv = dev->dev_private;
431 uint32_t address;
432
433 trap->nsource = trap->nstatus = 0;
434 if (dev_priv->card_type < NV_50) {
435 trap->nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
436 trap->nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
437 }
438
439 if (nouveau_graph_trapped_channel(dev, &trap->channel))
440 trap->channel = -1;
441 address = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
442
443 trap->mthd = address & 0x1FFC;
444 trap->data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
445 if (dev_priv->card_type < NV_10) {
446 trap->subc = (address >> 13) & 0x7;
447 } else {
448 trap->subc = (address >> 16) & 0x7;
449 trap->data2 = nv_rd32(dev, NV10_PGRAPH_TRAPPED_DATA_HIGH);
450 }
451
452 if (dev_priv->card_type < NV_10)
453 trap->class = nv_rd32(dev, 0x400180 + trap->subc*4) & 0xFF;
454 else if (dev_priv->card_type < NV_40)
455 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFF;
456 else if (dev_priv->card_type < NV_50)
457 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFFF;
458 else
459 trap->class = nv_rd32(dev, 0x400814);
460 }
461
462 static void
463 nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
464 struct nouveau_pgraph_trap *trap)
465 {
466 struct drm_nouveau_private *dev_priv = dev->dev_private;
467 uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
468
469 if (dev_priv->card_type < NV_50) {
470 NV_INFO(dev, "%s - nSource:", id);
471 nouveau_print_bitfield_names(nsource, nsource_names);
472 printk(", nStatus:");
473 if (dev_priv->card_type < NV_10)
474 nouveau_print_bitfield_names(nstatus, nstatus_names);
475 else
476 nouveau_print_bitfield_names(nstatus, nstatus_names_nv10);
477 printk("\n");
478 }
479
480 NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
481 "Data 0x%08x:0x%08x\n",
482 id, trap->channel, trap->subc,
483 trap->class, trap->mthd,
484 trap->data2, trap->data);
485 }
486
487 static int
488 nouveau_pgraph_intr_swmthd(struct drm_device *dev,
489 struct nouveau_pgraph_trap *trap)
490 {
491 struct drm_nouveau_private *dev_priv = dev->dev_private;
492
493 if (trap->channel < 0 ||
494 trap->channel >= dev_priv->engine.fifo.channels ||
495 !dev_priv->fifos[trap->channel])
496 return -ENODEV;
497
498 return nouveau_call_method(dev_priv->fifos[trap->channel],
499 trap->class, trap->mthd, trap->data);
500 }
501
502 static inline void
503 nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
504 {
505 struct nouveau_pgraph_trap trap;
506 int unhandled = 0;
507
508 nouveau_graph_trap_info(dev, &trap);
509
510 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
511 if (nouveau_pgraph_intr_swmthd(dev, &trap))
512 unhandled = 1;
513 } else {
514 unhandled = 1;
515 }
516
517 if (unhandled)
518 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
519 }
520
521
522 static inline void
523 nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
524 {
525 struct nouveau_pgraph_trap trap;
526 int unhandled = 0;
527
528 nouveau_graph_trap_info(dev, &trap);
529 trap.nsource = nsource;
530
531 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
532 if (nouveau_pgraph_intr_swmthd(dev, &trap))
533 unhandled = 1;
534 } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
535 uint32_t v = nv_rd32(dev, 0x402000);
536 nv_wr32(dev, 0x402000, v);
537
538 /* dump the error anyway for now: it's useful for
539 Gallium development */
540 unhandled = 1;
541 } else {
542 unhandled = 1;
543 }
544
545 if (unhandled && nouveau_ratelimit())
546 nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
547 }
548
549 static inline void
550 nouveau_pgraph_intr_context_switch(struct drm_device *dev)
551 {
552 struct drm_nouveau_private *dev_priv = dev->dev_private;
553 struct nouveau_engine *engine = &dev_priv->engine;
554 uint32_t chid;
555
556 chid = engine->fifo.channel_id(dev);
557 NV_DEBUG(dev, "PGRAPH context switch interrupt channel %x\n", chid);
558
559 switch (dev_priv->card_type) {
560 case NV_04:
561 nv04_graph_context_switch(dev);
562 break;
563 case NV_10:
564 nv10_graph_context_switch(dev);
565 break;
566 default:
567 NV_ERROR(dev, "Context switch not implemented\n");
568 break;
569 }
570 }
571
572 static void
573 nouveau_pgraph_irq_handler(struct drm_device *dev)
574 {
575 uint32_t status;
576
577 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
578 uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
579
580 if (status & NV_PGRAPH_INTR_NOTIFY) {
581 nouveau_pgraph_intr_notify(dev, nsource);
582
583 status &= ~NV_PGRAPH_INTR_NOTIFY;
584 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
585 }
586
587 if (status & NV_PGRAPH_INTR_ERROR) {
588 nouveau_pgraph_intr_error(dev, nsource);
589
590 status &= ~NV_PGRAPH_INTR_ERROR;
591 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
592 }
593
594 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
595 nouveau_pgraph_intr_context_switch(dev);
596
597 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
598 nv_wr32(dev, NV03_PGRAPH_INTR,
599 NV_PGRAPH_INTR_CONTEXT_SWITCH);
600 }
601
602 if (status) {
603 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status);
604 nv_wr32(dev, NV03_PGRAPH_INTR, status);
605 }
606
607 if ((nv_rd32(dev, NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
608 nv_wr32(dev, NV04_PGRAPH_FIFO, 1);
609 }
610
611 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
612 }
613
614 static void
615 nv50_pfb_vm_trap(struct drm_device *dev, int display, const char *name)
616 {
617 struct drm_nouveau_private *dev_priv = dev->dev_private;
618 uint32_t trap[6];
619 int i, ch;
620 uint32_t idx = nv_rd32(dev, 0x100c90);
621 if (idx & 0x80000000) {
622 idx &= 0xffffff;
623 if (display) {
624 for (i = 0; i < 6; i++) {
625 nv_wr32(dev, 0x100c90, idx | i << 24);
626 trap[i] = nv_rd32(dev, 0x100c94);
627 }
628 for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
629 struct nouveau_channel *chan = dev_priv->fifos[ch];
630
631 if (!chan || !chan->ramin)
632 continue;
633
634 if (trap[1] == chan->ramin->instance >> 12)
635 break;
636 }
637 NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d\n",
638 name, (trap[5]&0x100?"read":"write"),
639 trap[5]&0xff, trap[4]&0xffff,
640 trap[3]&0xffff, trap[0], trap[2], ch);
641 }
642 nv_wr32(dev, 0x100c90, idx | 0x80000000);
643 } else if (display) {
644 NV_INFO(dev, "%s - no VM fault?\n", name);
645 }
646 }
647
648 static struct nouveau_enum_names nv50_mp_exec_error_names[] =
649 {
650 { 3, "STACK_UNDERFLOW" },
651 { 4, "QUADON_ACTIVE" },
652 { 8, "TIMEOUT" },
653 { 0x10, "INVALID_OPCODE" },
654 { 0x40, "BREAKPOINT" },
655 };
656
657 static void
658 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
659 {
660 struct drm_nouveau_private *dev_priv = dev->dev_private;
661 uint32_t units = nv_rd32(dev, 0x1540);
662 uint32_t addr, mp10, status, pc, oplow, ophigh;
663 int i;
664 int mps = 0;
665 for (i = 0; i < 4; i++) {
666 if (!(units & 1 << (i+24)))
667 continue;
668 if (dev_priv->chipset < 0xa0)
669 addr = 0x408200 + (tpid << 12) + (i << 7);
670 else
671 addr = 0x408100 + (tpid << 11) + (i << 7);
672 mp10 = nv_rd32(dev, addr + 0x10);
673 status = nv_rd32(dev, addr + 0x14);
674 if (!status)
675 continue;
676 if (display) {
677 nv_rd32(dev, addr + 0x20);
678 pc = nv_rd32(dev, addr + 0x24);
679 oplow = nv_rd32(dev, addr + 0x70);
680 ophigh= nv_rd32(dev, addr + 0x74);
681 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
682 "TP %d MP %d: ", tpid, i);
683 nouveau_print_enum_names(status,
684 nv50_mp_exec_error_names);
685 printk(" at %06x warp %d, opcode %08x %08x\n",
686 pc&0xffffff, pc >> 24,
687 oplow, ophigh);
688 }
689 nv_wr32(dev, addr + 0x10, mp10);
690 nv_wr32(dev, addr + 0x14, 0);
691 mps++;
692 }
693 if (!mps && display)
694 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
695 "No MPs claiming errors?\n", tpid);
696 }
697
698 static void
699 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
700 uint32_t ustatus_new, int display, const char *name)
701 {
702 struct drm_nouveau_private *dev_priv = dev->dev_private;
703 int tps = 0;
704 uint32_t units = nv_rd32(dev, 0x1540);
705 int i, r;
706 uint32_t ustatus_addr, ustatus;
707 for (i = 0; i < 16; i++) {
708 if (!(units & (1 << i)))
709 continue;
710 if (dev_priv->chipset < 0xa0)
711 ustatus_addr = ustatus_old + (i << 12);
712 else
713 ustatus_addr = ustatus_new + (i << 11);
714 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
715 if (!ustatus)
716 continue;
717 tps++;
718 switch (type) {
719 case 6: /* texture error... unknown for now */
720 nv50_pfb_vm_trap(dev, display, name);
721 if (display) {
722 NV_ERROR(dev, "magic set %d:\n", i);
723 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
724 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
725 nv_rd32(dev, r));
726 }
727 break;
728 case 7: /* MP error */
729 if (ustatus & 0x00010000) {
730 nv50_pgraph_mp_trap(dev, i, display);
731 ustatus &= ~0x00010000;
732 }
733 break;
734 case 8: /* TPDMA error */
735 {
736 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
737 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
738 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
739 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
740 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
741 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
742 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
743 nv50_pfb_vm_trap(dev, display, name);
744 /* 2d engine destination */
745 if (ustatus & 0x00000010) {
746 if (display) {
747 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
748 i, e14, e10);
749 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
750 i, e0c, e18, e1c, e20, e24);
751 }
752 ustatus &= ~0x00000010;
753 }
754 /* Render target */
755 if (ustatus & 0x00000040) {
756 if (display) {
757 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
758 i, e14, e10);
759 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
760 i, e0c, e18, e1c, e20, e24);
761 }
762 ustatus &= ~0x00000040;
763 }
764 /* CUDA memory: l[], g[] or stack. */
765 if (ustatus & 0x00000080) {
766 if (display) {
767 if (e18 & 0x80000000) {
768 /* g[] read fault? */
769 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
770 i, e14, e10 | ((e18 >> 24) & 0x1f));
771 e18 &= ~0x1f000000;
772 } else if (e18 & 0xc) {
773 /* g[] write fault? */
774 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
775 i, e14, e10 | ((e18 >> 7) & 0x1f));
776 e18 &= ~0x00000f80;
777 } else {
778 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
779 i, e14, e10);
780 }
781 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
782 i, e0c, e18, e1c, e20, e24);
783 }
784 ustatus &= ~0x00000080;
785 }
786 }
787 break;
788 }
789 if (ustatus) {
790 if (display)
791 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
792 }
793 nv_wr32(dev, ustatus_addr, 0xc0000000);
794 }
795
796 if (!tps && display)
797 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
798 }
799
800 static void
801 nv50_pgraph_trap_handler(struct drm_device *dev)
802 {
803 struct nouveau_pgraph_trap trap;
804 uint32_t status = nv_rd32(dev, 0x400108);
805 uint32_t ustatus;
806 int display = nouveau_ratelimit();
807
808
809 if (!status && display) {
810 nouveau_graph_trap_info(dev, &trap);
811 nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
812 NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
813 }
814
815 /* DISPATCH: Relays commands to other units and handles NOTIFY,
816 * COND, QUERY. If you get a trap from it, the command is still stuck
817 * in DISPATCH and you need to do something about it. */
818 if (status & 0x001) {
819 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
820 if (!ustatus && display) {
821 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
822 }
823
824 /* Known to be triggered by screwed up NOTIFY and COND... */
825 if (ustatus & 0x00000001) {
826 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
827 nv_wr32(dev, 0x400500, 0);
828 if (nv_rd32(dev, 0x400808) & 0x80000000) {
829 if (display) {
830 if (nouveau_graph_trapped_channel(dev, &trap.channel))
831 trap.channel = -1;
832 trap.class = nv_rd32(dev, 0x400814);
833 trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
834 trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
835 trap.data = nv_rd32(dev, 0x40080c);
836 trap.data2 = nv_rd32(dev, 0x400810);
837 nouveau_graph_dump_trap_info(dev,
838 "PGRAPH_TRAP_DISPATCH_FAULT", &trap);
839 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
840 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
841 }
842 nv_wr32(dev, 0x400808, 0);
843 } else if (display) {
844 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
845 }
846 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
847 nv_wr32(dev, 0x400848, 0);
848 ustatus &= ~0x00000001;
849 }
850 if (ustatus & 0x00000002) {
851 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
852 nv_wr32(dev, 0x400500, 0);
853 if (nv_rd32(dev, 0x40084c) & 0x80000000) {
854 if (display) {
855 if (nouveau_graph_trapped_channel(dev, &trap.channel))
856 trap.channel = -1;
857 trap.class = nv_rd32(dev, 0x400814);
858 trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
859 trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
860 trap.data = nv_rd32(dev, 0x40085c);
861 trap.data2 = 0;
862 nouveau_graph_dump_trap_info(dev,
863 "PGRAPH_TRAP_DISPATCH_QUERY", &trap);
864 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
865 }
866 nv_wr32(dev, 0x40084c, 0);
867 } else if (display) {
868 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
869 }
870 ustatus &= ~0x00000002;
871 }
872 if (ustatus && display)
873 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
874 nv_wr32(dev, 0x400804, 0xc0000000);
875 nv_wr32(dev, 0x400108, 0x001);
876 status &= ~0x001;
877 }
878
879 /* TRAPs other than dispatch use the "normal" trap regs. */
880 if (status && display) {
881 nouveau_graph_trap_info(dev, &trap);
882 nouveau_graph_dump_trap_info(dev,
883 "PGRAPH_TRAP", &trap);
884 }
885
886 /* M2MF: Memory to memory copy engine. */
887 if (status & 0x002) {
888 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
889 if (!ustatus && display) {
890 NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
891 }
892 if (ustatus & 0x00000001) {
893 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
894 ustatus &= ~0x00000001;
895 }
896 if (ustatus & 0x00000002) {
897 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
898 ustatus &= ~0x00000002;
899 }
900 if (ustatus & 0x00000004) {
901 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
902 ustatus &= ~0x00000004;
903 }
904 NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
905 nv_rd32(dev, 0x406804),
906 nv_rd32(dev, 0x406808),
907 nv_rd32(dev, 0x40680c),
908 nv_rd32(dev, 0x406810));
909 if (ustatus && display)
910 NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
911 /* No sane way found yet -- just reset the bugger. */
912 nv_wr32(dev, 0x400040, 2);
913 nv_wr32(dev, 0x400040, 0);
914 nv_wr32(dev, 0x406800, 0xc0000000);
915 nv_wr32(dev, 0x400108, 0x002);
916 status &= ~0x002;
917 }
918
919 /* VFETCH: Fetches data from vertex buffers. */
920 if (status & 0x004) {
921 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
922 if (!ustatus && display) {
923 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
924 }
925 if (ustatus & 0x00000001) {
926 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
927 NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
928 nv_rd32(dev, 0x400c00),
929 nv_rd32(dev, 0x400c08),
930 nv_rd32(dev, 0x400c0c),
931 nv_rd32(dev, 0x400c10));
932 ustatus &= ~0x00000001;
933 }
934 if (ustatus && display)
935 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
936 nv_wr32(dev, 0x400c04, 0xc0000000);
937 nv_wr32(dev, 0x400108, 0x004);
938 status &= ~0x004;
939 }
940
941 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
942 if (status & 0x008) {
943 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
944 if (!ustatus && display) {
945 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
946 }
947 if (ustatus & 0x00000001) {
948 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
949 NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
950 nv_rd32(dev, 0x401804),
951 nv_rd32(dev, 0x401808),
952 nv_rd32(dev, 0x40180c),
953 nv_rd32(dev, 0x401810));
954 ustatus &= ~0x00000001;
955 }
956 if (ustatus && display)
957 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
958 /* No sane way found yet -- just reset the bugger. */
959 nv_wr32(dev, 0x400040, 0x80);
960 nv_wr32(dev, 0x400040, 0);
961 nv_wr32(dev, 0x401800, 0xc0000000);
962 nv_wr32(dev, 0x400108, 0x008);
963 status &= ~0x008;
964 }
965
966 /* CCACHE: Handles code and c[] caches and fills them. */
967 if (status & 0x010) {
968 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
969 if (!ustatus && display) {
970 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
971 }
972 if (ustatus & 0x00000001) {
973 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
974 NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
975 nv_rd32(dev, 0x405800),
976 nv_rd32(dev, 0x405804),
977 nv_rd32(dev, 0x405808),
978 nv_rd32(dev, 0x40580c),
979 nv_rd32(dev, 0x405810),
980 nv_rd32(dev, 0x405814),
981 nv_rd32(dev, 0x40581c));
982 ustatus &= ~0x00000001;
983 }
984 if (ustatus && display)
985 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
986 nv_wr32(dev, 0x405018, 0xc0000000);
987 nv_wr32(dev, 0x400108, 0x010);
988 status &= ~0x010;
989 }
990
991 /* Unknown, not seen yet... 0x402000 is the only trap status reg
992 * remaining, so try to handle it anyway. Perhaps related to that
993 * unknown DMA slot on tesla? */
994 if (status & 0x20) {
995 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
996 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
997 if (display)
998 NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
999 nv_wr32(dev, 0x402000, 0xc0000000);
1000 /* no status modifiction on purpose */
1001 }
1002
1003 /* TEXTURE: CUDA texturing units */
1004 if (status & 0x040) {
1005 nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
1006 "PGRAPH_TRAP_TEXTURE");
1007 nv_wr32(dev, 0x400108, 0x040);
1008 status &= ~0x040;
1009 }
1010
1011 /* MP: CUDA execution engines. */
1012 if (status & 0x080) {
1013 nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
1014 "PGRAPH_TRAP_MP");
1015 nv_wr32(dev, 0x400108, 0x080);
1016 status &= ~0x080;
1017 }
1018
1019 /* TPDMA: Handles TP-initiated uncached memory accesses:
1020 * l[], g[], stack, 2d surfaces, render targets. */
1021 if (status & 0x100) {
1022 nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
1023 "PGRAPH_TRAP_TPDMA");
1024 nv_wr32(dev, 0x400108, 0x100);
1025 status &= ~0x100;
1026 }
1027
1028 if (status) {
1029 if (display)
1030 NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
1031 status);
1032 nv_wr32(dev, 0x400108, status);
1033 }
1034 }
1035
1036 /* There must be a *lot* of these. Will take some time to gather them up. */
1037 static struct nouveau_enum_names nv50_data_error_names[] =
1038 {
1039 { 4, "INVALID_VALUE" },
1040 { 5, "INVALID_ENUM" },
1041 { 8, "INVALID_OBJECT" },
1042 { 0xc, "INVALID_BITFIELD" },
1043 { 0x28, "MP_NO_REG_SPACE" },
1044 { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
1045 };
1046
1047 static void
1048 nv50_pgraph_irq_handler(struct drm_device *dev)
1049 {
1050 struct nouveau_pgraph_trap trap;
1051 int unhandled = 0;
1052 uint32_t status;
1053
1054 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1055 /* NOTIFY: You've set a NOTIFY an a command and it's done. */
1056 if (status & 0x00000001) {
1057 nouveau_graph_trap_info(dev, &trap);
1058 if (nouveau_ratelimit())
1059 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
1060 status &= ~0x00000001;
1061 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
1062 }
1063
1064 /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
1065 * when you write 0x200 to 0x50c0 method 0x31c. */
1066 if (status & 0x00000002) {
1067 nouveau_graph_trap_info(dev, &trap);
1068 if (nouveau_ratelimit())
1069 nouveau_graph_dump_trap_info(dev,
1070 "PGRAPH_COMPUTE_QUERY", &trap);
1071 status &= ~0x00000002;
1072 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
1073 }
1074
1075 /* Unknown, never seen: 0x4 */
1076
1077 /* ILLEGAL_MTHD: You used a wrong method for this class. */
1078 if (status & 0x00000010) {
1079 nouveau_graph_trap_info(dev, &trap);
1080 if (nouveau_pgraph_intr_swmthd(dev, &trap))
1081 unhandled = 1;
1082 if (unhandled && nouveau_ratelimit())
1083 nouveau_graph_dump_trap_info(dev,
1084 "PGRAPH_ILLEGAL_MTHD", &trap);
1085 status &= ~0x00000010;
1086 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
1087 }
1088
1089 /* ILLEGAL_CLASS: You used a wrong class. */
1090 if (status & 0x00000020) {
1091 nouveau_graph_trap_info(dev, &trap);
1092 if (nouveau_ratelimit())
1093 nouveau_graph_dump_trap_info(dev,
1094 "PGRAPH_ILLEGAL_CLASS", &trap);
1095 status &= ~0x00000020;
1096 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
1097 }
1098
1099 /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
1100 if (status & 0x00000040) {
1101 nouveau_graph_trap_info(dev, &trap);
1102 if (nouveau_ratelimit())
1103 nouveau_graph_dump_trap_info(dev,
1104 "PGRAPH_DOUBLE_NOTIFY", &trap);
1105 status &= ~0x00000040;
1106 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
1107 }
1108
1109 /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
1110 if (status & 0x00001000) {
1111 nv_wr32(dev, 0x400500, 0x00000000);
1112 nv_wr32(dev, NV03_PGRAPH_INTR,
1113 NV_PGRAPH_INTR_CONTEXT_SWITCH);
1114 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
1115 NV40_PGRAPH_INTR_EN) &
1116 ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
1117 nv_wr32(dev, 0x400500, 0x00010001);
1118
1119 nv50_graph_context_switch(dev);
1120
1121 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1122 }
1123
1124 /* BUFFER_NOTIFY: Your m2mf transfer finished */
1125 if (status & 0x00010000) {
1126 nouveau_graph_trap_info(dev, &trap);
1127 if (nouveau_ratelimit())
1128 nouveau_graph_dump_trap_info(dev,
1129 "PGRAPH_BUFFER_NOTIFY", &trap);
1130 status &= ~0x00010000;
1131 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
1132 }
1133
1134 /* DATA_ERROR: Invalid value for this method, or invalid
1135 * state in current PGRAPH context for this operation */
1136 if (status & 0x00100000) {
1137 nouveau_graph_trap_info(dev, &trap);
1138 if (nouveau_ratelimit()) {
1139 nouveau_graph_dump_trap_info(dev,
1140 "PGRAPH_DATA_ERROR", &trap);
1141 NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
1142 nouveau_print_enum_names(nv_rd32(dev, 0x400110),
1143 nv50_data_error_names);
1144 printk("\n");
1145 }
1146 status &= ~0x00100000;
1147 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
1148 }
1149
1150 /* TRAP: Something bad happened in the middle of command
1151 * execution. Has a billion types, subtypes, and even
1152 * subsubtypes. */
1153 if (status & 0x00200000) {
1154 nv50_pgraph_trap_handler(dev);
1155 status &= ~0x00200000;
1156 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
1157 }
1158
1159 /* Unknown, never seen: 0x00400000 */
1160
1161 /* SINGLE_STEP: Happens on every method if you turned on
1162 * single stepping in 40008c */
1163 if (status & 0x01000000) {
1164 nouveau_graph_trap_info(dev, &trap);
1165 if (nouveau_ratelimit())
1166 nouveau_graph_dump_trap_info(dev,
1167 "PGRAPH_SINGLE_STEP", &trap);
1168 status &= ~0x01000000;
1169 nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
1170 }
1171
1172 /* 0x02000000 happens when you pause a ctxprog...
1173 * but the only way this can happen that I know is by
1174 * poking the relevant MMIO register, and we don't
1175 * do that. */
1176
1177 if (status) {
1178 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
1179 status);
1180 nv_wr32(dev, NV03_PGRAPH_INTR, status);
1181 }
1182
1183 {
1184 const int isb = (1 << 16) | (1 << 0);
1185
1186 if ((nv_rd32(dev, 0x400500) & isb) != isb)
1187 nv_wr32(dev, 0x400500,
1188 nv_rd32(dev, 0x400500) | isb);
1189 }
1190 }
1191
1192 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
1193 if (nv_rd32(dev, 0x400824) & (1 << 31))
1194 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1195 }
1196 #endif
1197
1198 static void
1199 nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
1200 {
1201 if (crtc & 1)
1202 nv_wr32(dev, NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
1203
1204 if (crtc & 2)
1205 nv_wr32(dev, NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
1206 }
1207
1208 static void
1209 nouveau_pbus_irq_handler(struct drm_device *dev) {
1210 struct drm_nouveau_private *dev_priv = dev->dev_private;
1211 uint32_t status = nv_rd32(dev, 0x1100);
1212 uint32_t mask = (dev_priv->chipset >= 0xc0) ? 0xf : 0x8;
1213
1214 if (status & mask) {
1215 uint32_t addr = nv_rd32(dev, 0x9084);
1216 uint32_t data = nv_rd32(dev, 0x9088);
1217
1218 if (!(addr & 1)) {
1219 NV_ERROR(dev, "PBUS: Unknown MMIO problem %06x %08x\n", addr, data);
1220 } else if (addr & 0x2) {
1221 NV_ERROR(dev, "PBUS: MMIO write fault, addr %06x data %08x\n", addr & ~3, data);
1222 } else {
1223 NV_ERROR(dev, "PBUS: MMIO read fault, addr %06x\n", addr & ~3);
1224 }
1225 if (status & 1)
1226 NV_ERROR(dev, "PBUS: accessed disabled PSUBFIFO\n");
1227 if (status & 2)
1228 NV_ERROR(dev, "PBUS: accessed wrong address inside unit\n");
1229 if (status & 4)
1230 NV_ERROR(dev, "PBUS: accessed address is outside unit\n");
1231
1232 if (dev_priv->chipset >= 0xc0) {
1233 nv_wr32(dev, 0x9084, 0);
1234 nv_wr32(dev, 0x9088, 0);
1235 }
1236 nv_wr32(dev, 0x1100, status & mask);
1237 status &= ~mask;
1238 }
1239
1240 if (status) {
1241 NV_ERROR(dev, "PBUS: unknown interrupt %08x\n", status);
1242 nv_wr32(dev, 0x1100, status);
1243 }
1244 }
1245
1246 void nouveau_irq_register(struct drm_device *dev, int irq, nouveau_irqhandler_t handler) {
1247 struct drm_nouveau_private *dev_priv = dev->dev_private;
1248 unsigned long flags;
1249 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
1250 BUG_ON(dev_priv->irq_handler[irq]);
1251 dev_priv->irq_handler[irq] = handler;
1252 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
1253 }
1254
1255 void nouveau_irq_unregister(struct drm_device *dev, int irq) {
1256 struct drm_nouveau_private *dev_priv = dev->dev_private;
1257 unsigned long flags;
1258 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
1259 BUG_ON(!dev_priv->irq_handler[irq]);
1260 dev_priv->irq_handler[irq] = 0;
1261 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
1262 }
1263
1264 irqreturn_t
1265 nouveau_irq_handler(DRM_IRQ_ARGS)
1266 {
1267 struct drm_device *dev = (struct drm_device *)arg;
1268 struct drm_nouveau_private *dev_priv = dev->dev_private;
1269 uint32_t status;
1270 #if 0
1271 uint32_t fbdev_flags = 0;
1272 #endif
1273 unsigned long flags;
1274 int i;
1275
1276 status = nv_rd32(dev, NV03_PMC_INTR_0);
1277 if (!status)
1278 return IRQ_NONE;
1279 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
1280
1281 if (status & 0x80000000) {
1282 NV_ERROR(dev, "Got a SOFTWARE interrupt for no good reason.\n");
1283 nv_wr32(dev, NV03_PMC_INTR_0, 0);
1284 status &= ~0x80000000;
1285 }
1286
1287 if (status & 0x10000000) {
1288 nouveau_pbus_irq_handler(dev);
1289 status &= ~0x10000000;
1290 }
1291
1292 for (i = 0; i < 32; i++) {
1293 if (status & 1 << i) {
1294 if (dev_priv->irq_handler[i]) {
1295 dev_priv->irq_handler[i](dev, i);
1296 status &= ~(1 << i);
1297 }
1298 }
1299 }
1300
1301 #if 0
1302 if (dev_priv->fbdev_info) {
1303 fbdev_flags = dev_priv->fbdev_info->flags;
1304 dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
1305 }
1306 #endif
1307
1308 if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
1309 nouveau_crtc_irq_handler(dev, (status>>24)&3);
1310 status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
1311 }
1312
1313 if (status & (NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1314 NV_PMC_INTR_0_NV50_I2C_PENDING)) {
1315 nv50_display_irq_handler(dev);
1316 status &= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1317 NV_PMC_INTR_0_NV50_I2C_PENDING);
1318 }
1319
1320 if (status)
1321 NV_ERROR(dev, "Unhandled PMC INTR status bits 0x%08x\n", status);
1322
1323 #if 0
1324 if (dev_priv->fbdev_info)
1325 dev_priv->fbdev_info->flags = fbdev_flags;
1326 #endif
1327
1328 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
1329
1330 return IRQ_HANDLED;
1331 }
pscnv is an open-source NVIDIA graphics driver developed by PathScale.