pscnv/nv04_timer.c

   1 #include "drm.h"
   2 #include "nouveau_drv.h"
   3 #include "nouveau_reg.h"
   4
   5 int
   6 nv04_timer_init(struct drm_device *dev)
   7 {
   8         nv_wr32(dev, NV04_PTIMER_INTR_EN_0, 0x00000000);
   9         nv_wr32(dev, NV04_PTIMER_INTR_0, 0xFFFFFFFF);
  10
  11         /* Just use the pre-existing values when possible for now; these regs
  12          * are not written in nv (driver writer missed a /4 on the address), and
  13          * writing 8 and 3 to the correct regs breaks the timings on the LVDS
  14          * hardware sequencing microcode.
  15          * A correct solution (involving calculations with the GPU PLL) can
  16          * be done when kernel modesetting lands
  17          */
  18         if (!nv_rd32(dev, NV04_PTIMER_NUMERATOR) ||
  19                                 !nv_rd32(dev, NV04_PTIMER_DENOMINATOR)) {
  20                 nv_wr32(dev, NV04_PTIMER_NUMERATOR, 0x00000008);
  21                 nv_wr32(dev, NV04_PTIMER_DENOMINATOR, 0x00000003);
  22         }
  23
  24         return 0;
  25 }
  26
  27 uint64_t
  28 nv04_timer_read(struct drm_device *dev)
  29 {
  30         uint32_t low;
  31         /* From kmmio dumps on nv28 this looks like how the blob does this.
  32          * It reads the high dword twice, before and after.
  33          * The only explanation seems to be that the 64-bit timer counter
  34          * advances between high and low dword reads and may corrupt the
  35          * result. Not confirmed.
  36          */
  37         uint32_t high2 = nv_rd32(dev, NV04_PTIMER_TIME_1);
  38         uint32_t high1;
  39         do {
  40                 high1 = high2;
  41                 low = nv_rd32(dev, NV04_PTIMER_TIME_0);
  42                 high2 = nv_rd32(dev, NV04_PTIMER_TIME_1);
  43         } while (high1 != high2);
  44         return (((uint64_t)high2) << 32) | (uint64_t)low;
  45 }