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[pscnv.git] / pscnv / nv50_display.c
blobb3ee6c040bd9bc1d19862551b9954cc2384b00ae
1 /*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "nv50_display.h"
28 #include "nouveau_crtc.h"
29 #include "nouveau_encoder.h"
30 #include "nouveau_connector.h"
31 #include "nouveau_fb.h"
32 #include "nouveau_dma.h"
33 #include "nouveau_fbcon.h"
34 #include "drm_crtc_helper.h"
35 #include "pscnv_vm.h"
36
37 static inline int
38 nv50_sor_nr(struct drm_device *dev)
39 {
40 struct drm_nouveau_private *dev_priv = dev->dev_private;
41
42 if (dev_priv->chipset < 0x90 ||
43 dev_priv->chipset == 0x92 ||
44 dev_priv->chipset == 0xa0)
45 return 2;
46
47 return 4;
48 }
49
50 u32
51 nv50_display_active_crtcs(struct drm_device *dev)
52 {
53 struct drm_nouveau_private *dev_priv = dev->dev_private;
54 u32 mask = 0;
55 int i;
56
57 if (dev_priv->chipset < 0x90 ||
58 dev_priv->chipset == 0x92 ||
59 dev_priv->chipset == 0xa0) {
60 for (i = 0; i < 2; i++)
61 mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
62 } else {
63 for (i = 0; i < 4; i++)
64 mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
65 }
66
67 for (i = 0; i < 3; i++)
68 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
69
70 return mask & 3;
71 }
72
73 static void
74 nv50_evo_channel_del(struct nouveau_channel **pchan)
75 {
76 struct nouveau_channel *chan = *pchan;
77
78 if (!chan)
79 return;
80 *pchan = NULL;
81
82 if (chan->pushbuf)
83 pscnv_mem_free(chan->pushbuf);
84 if (chan->evo_obj)
85 pscnv_mem_free(chan->evo_obj);
86
87 kfree(chan);
88 }
89
90 static int
91 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
92 uint32_t tile_flags, uint32_t magic_flags,
93 uint32_t offset, uint32_t limit)
94 {
95 struct drm_device *dev = evo->dev;
96 struct drm_nouveau_private *dev_priv = dev->dev_private;
97 int ret;
98
99 uint32_t inst = evo->evo_inst;
100 if (inst+0x20 > evo->evo_obj->size)
101 return -ENOMEM;
102 evo->evo_inst += 0x20;
103
104 if ((ret = pscnv_ramht_insert(&evo->evo_ramht, name, inst << 10 | 2))) {
105 return ret;
106 evo->evo_inst -= 0x20;
107 }
108
109 nv_wv32(evo->evo_obj, inst + 0x00, (tile_flags << 22) | (magic_flags << 16) | class);
110 nv_wv32(evo->evo_obj, inst + 0x04, limit);
111 nv_wv32(evo->evo_obj, inst + 0x08, offset);
112 nv_wv32(evo->evo_obj, inst + 0x0c, 0x00000000);
113 if (dev_priv->card_type >= NV_C0) {
114 nv_wv32(evo->evo_obj, inst + 0x10, 0x00000010);
115 nv_wv32(evo->evo_obj, inst + 0x14, tile_flags ? 0 : 0x20000);
116 } else {
117 nv_wv32(evo->evo_obj, inst + 0x10, 0x00000000);
118 nv_wv32(evo->evo_obj, inst + 0x14, 0x00010000);
119 }
120 dev_priv->vm->bar_flush(dev);
121
122 return 0;
123 }
124
125 static int
126 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
127 {
128 struct drm_nouveau_private *dev_priv = dev->dev_private;
129 struct nouveau_channel *chan;
130 int ret;
131 int i;
132
133 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
134 if (!chan)
135 return -ENOMEM;
136 *pchan = chan;
137
138 chan->id = -1;
139 chan->dev = dev;
140 chan->user_put = NV50_PDISPLAY_USER_PUT(0);
141 chan->user_get = NV50_PDISPLAY_USER_GET(0);
142
143 chan->evo_obj = pscnv_mem_alloc(dev, 0x2000, PSCNV_GEM_CONTIG | PSCNV_GEM_VRAM_LARGE, 0, 0xd1501a7);
144 if (!chan->evo_obj) {
145 nv50_evo_channel_del(pchan);
146 NV_ERROR(dev, "Error allocating EVO channel memory\n");
147 return -ENOMEM;
148 }
149 spin_lock_init(&chan->evo_ramht.lock);
150 chan->evo_ramht.bo = chan->evo_obj;
151 chan->evo_ramht.bits = 9;
152 chan->evo_ramht.offset = 0;
153 chan->evo_inst = 0x1000;
154 dev_priv->vm->map_kernel(chan->evo_obj);
155 for (i = 0; i < 0x1000; i += 4)
156 nv_wv32(chan->evo_obj, i, 0);
157
158 if (dev_priv->chipset >= 0xc0) {
159 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFE, 0xfe, 0x19,
160 0, 0xffffffff);
161 if (ret) {
162 nv50_evo_channel_del(pchan);
163 return ret;
164 }
165 } else
166 if (dev_priv->chipset > 0x50) {
167 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
168 0, 0xffffffff);
169 if (ret) {
170 nv50_evo_channel_del(pchan);
171 return ret;
172 }
173
174
175 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
176 0, 0xffffffff);
177 if (ret) {
178 nv50_evo_channel_del(pchan);
179 return ret;
180 }
181 }
182
183 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
184 0, dev_priv->vram_size);
185 if (ret) {
186 nv50_evo_channel_del(pchan);
187 return ret;
188 }
189
190 chan->pushbuf = pscnv_mem_alloc(dev, 0x1000, PSCNV_GEM_CONTIG, 0, 0xd15f1f0);
191 if (!chan->pushbuf) {
192 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
193 nv50_evo_channel_del(pchan);
194 return -ENOMEM;
195 }
196 dev_priv->vm->map_kernel(chan->pushbuf);
197 chan->pushbuf_base = 0;
198
199 return 0;
200 }
201
202 int
203 nv50_display_early_init(struct drm_device *dev)
204 {
205 return 0;
206 }
207
208 void
209 nv50_display_late_takedown(struct drm_device *dev)
210 {
211 }
212
213 int
214 nv50_display_init(struct drm_device *dev)
215 {
216 struct drm_nouveau_private *dev_priv = dev->dev_private;
217 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
218 struct nouveau_channel *evo = dev_priv->evo;
219 struct drm_connector *connector;
220 uint32_t val, ram_amount;
221 uint64_t start;
222 int ret, i;
223
224 NV_DEBUG_KMS(dev, "\n");
225
226 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
227 /*
228 * I think the 0x006101XX range is some kind of main control area
229 * that enables things.
230 */
231 /* CRTC? */
232 for (i = 0; i < 2; i++) {
233 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
234 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
235 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
236 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
237 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
238 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
239 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
240 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
241 }
242 /* DAC */
243 for (i = 0; i < 3; i++) {
244 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
245 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
246 }
247 /* SOR */
248 for (i = 0; i < nv50_sor_nr(dev); i++) {
249 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
250 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
251 }
252 /* EXT */
253 for (i = 0; i < 3; i++) {
254 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
255 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
256 }
257
258 for (i = 0; i < 3; i++) {
259 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
260 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
261 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
262 }
263
264 /* This used to be in crtc unblank, but seems out of place there. */
265 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
266 /* RAM is clamped to 256 MiB. */
267 ram_amount = dev_priv->vram_size;
268 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
269 if (ram_amount > 256*1024*1024)
270 ram_amount = 256*1024*1024;
271
272 if (dev_priv->card_type < NV_C0) {
273 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
274 nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
275 nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
276 }
277
278 /* The precise purpose is unknown, i suspect it has something to do
279 * with text mode.
280 */
281 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
282 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
283 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
284 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
285 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
286 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
287 nv_rd32(dev, 0x6194e8));
288 return -EBUSY;
289 }
290 }
291
292 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
293 * stuck in some unspecified state
294 */
295 start = nv04_timer_read(dev);
296 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
297 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
298 if ((val & 0x9f0000) == 0x20000)
299 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
300 val | 0x800000);
301
302 if ((val & 0x3f0000) == 0x30000)
303 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
304 val | 0x200000);
305
306 if (nv04_timer_read(dev) - start > 1000000000ULL) {
307 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
308 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
309 return -EBUSY;
310 }
311 }
312
313 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
314 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
315 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
316 0x40000000, 0x40000000)) {
317 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
318 NV_ERROR(dev, "0x610200 = 0x%08x\n",
319 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
320 return -EBUSY;
321 }
322
323 for (i = 0; i < 2; i++) {
324 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
325 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
326 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
327 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
328 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
329 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
330 return -EBUSY;
331 }
332
333 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
334 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
335 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
336 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
337 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
338 NV_ERROR(dev, "timeout: "
339 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
340 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
341 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
342 return -EBUSY;
343 }
344 }
345
346 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->evo_obj->start >> 8) | 9);
347
348 /* initialise fifo */
349 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
350 ((evo->pushbuf->start) >> 8) |
351 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
352 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
353 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
354 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
355 if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) {
356 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
357 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
358 return -EBUSY;
359 }
360 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
361 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
362 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
363 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
364 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
365 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
366 nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
367
368 evo->dma.max = (4096/4) - 2;
369 evo->dma.put = 0;
370 evo->dma.cur = evo->dma.put;
371 evo->dma.free = evo->dma.max - evo->dma.cur;
372
373 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
374 if (ret)
375 return ret;
376
377 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
378 OUT_RING(evo, 0);
379
380 ret = RING_SPACE(evo, 11);
381 if (ret)
382 return ret;
383 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
384 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
385 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
386 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
387 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
388 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
389 OUT_RING(evo, 0);
390 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
391 OUT_RING(evo, 0);
392 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
393 OUT_RING(evo, 0);
394 FIRE_RING(evo);
395 if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
396 NV_ERROR(dev, "evo pushbuf stalled\n");
397
398 /* enable clock change interrupts. */
399 nv_wr32(dev, 0x610028, 0x00010001);
400 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
401 NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
402 NV50_PDISPLAY_INTR_EN_CLK_UNK40));
403
404 /* enable hotplug interrupts */
405 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
406 struct nouveau_connector *conn = nouveau_connector(connector);
407
408 if (conn->dcb->gpio_tag == 0xff)
409 continue;
410
411 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
412 }
413
414 return 0;
415 }
416
417 static int nv50_display_disable(struct drm_device *dev)
418 {
419 struct drm_nouveau_private *dev_priv = dev->dev_private;
420 struct drm_crtc *drm_crtc;
421 int ret, i;
422
423 NV_DEBUG_KMS(dev, "\n");
424
425 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
426 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
427
428 nv50_crtc_blank(crtc, true);
429 }
430
431 ret = RING_SPACE(dev_priv->evo, 2);
432 if (ret == 0) {
433 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
434 OUT_RING(dev_priv->evo, 0);
435 }
436 FIRE_RING(dev_priv->evo);
437
438 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
439 * cleaning up?
440 */
441 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
442 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
443 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
444
445 if (!crtc->base.enabled)
446 continue;
447
448 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
449 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
450 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
451 "0x%08x\n", mask, mask);
452 NV_ERROR(dev, "0x610024 = 0x%08x\n",
453 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
454 }
455 }
456
457 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
458 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
459 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
460 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
461 NV_ERROR(dev, "0x610200 = 0x%08x\n",
462 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
463 }
464
465 for (i = 0; i < 3; i++) {
466 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
467 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
468 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
469 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
470 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
471 }
472 }
473
474 /* disable interrupts. */
475 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
476
477 /* disable hotplug interrupts */
478 nv_wr32(dev, 0xe054, 0xffffffff);
479 nv_wr32(dev, 0xe050, 0x00000000);
480 if (dev_priv->chipset >= 0x90) {
481 nv_wr32(dev, 0xe074, 0xffffffff);
482 nv_wr32(dev, 0xe070, 0x00000000);
483 }
484 return 0;
485 }
486
487 int nv50_display_create(struct drm_device *dev)
488 {
489 struct drm_nouveau_private *dev_priv = dev->dev_private;
490 struct dcb_table *dcb = &dev_priv->vbios.dcb;
491 struct drm_connector *connector, *ct;
492 int ret, i;
493
494 NV_DEBUG_KMS(dev, "\n");
495
496 /* Create EVO channel */
497 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
498 if (ret) {
499 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
500 return ret;
501 }
502
503 /* Create CRTC objects */
504 for (i = 0; i < 2; i++)
505 nv50_crtc_create(dev, i);
506
507 /* We setup the encoders from the BIOS table */
508 for (i = 0 ; i < dcb->entries; i++) {
509 struct dcb_entry *entry = &dcb->entry[i];
510
511 if (entry->location != DCB_LOC_ON_CHIP) {
512 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
513 entry->type, ffs(entry->or) - 1);
514 continue;
515 }
516
517 connector = nouveau_connector_create(dev, entry->connector);
518 if (IS_ERR(connector))
519 continue;
520
521 switch (entry->type) {
522 case OUTPUT_TMDS:
523 case OUTPUT_LVDS:
524 case OUTPUT_DP:
525 nv50_sor_create(connector, entry);
526 break;
527 case OUTPUT_ANALOG:
528 nv50_dac_create(connector, entry);
529 break;
530 default:
531 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
532 continue;
533 }
534 }
535
536 list_for_each_entry_safe(connector, ct,
537 &dev->mode_config.connector_list, head) {
538 if (!connector->encoder_ids[0]) {
539 NV_WARN(dev, "%s has no encoders, removing\n",
540 drm_get_connector_name(connector));
541 connector->funcs->destroy(connector);
542 }
543 }
544
545 ret = nv50_display_init(dev);
546 if (ret) {
547 nv50_display_destroy(dev);
548 return ret;
549 }
550
551 return 0;
552 }
553
554 void
555 nv50_display_destroy(struct drm_device *dev)
556 {
557 struct drm_nouveau_private *dev_priv = dev->dev_private;
558
559 NV_DEBUG_KMS(dev, "\n");
560
561 nv50_display_disable(dev);
562 nv50_evo_channel_del(&dev_priv->evo);
563 }
564
565 static u16
566 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
567 u32 mc, int pxclk)
568 {
569 struct drm_nouveau_private *dev_priv = dev->dev_private;
570 struct nouveau_connector *nv_connector = NULL;
571 struct drm_encoder *encoder;
572 struct nvbios *bios = &dev_priv->vbios;
573 u32 script = 0, or;
574
575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
576 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
577
578 if (nv_encoder->dcb != dcb)
579 continue;
580
581 nv_connector = nouveau_encoder_connector_get(nv_encoder);
582 break;
583 }
584
585 or = ffs(dcb->or) - 1;
586 switch (dcb->type) {
587 case OUTPUT_LVDS:
588 script = (mc >> 8) & 0xf;
589 if (bios->fp_no_ddc) {
590 if (bios->fp.dual_link)
591 script |= 0x0100;
592 if (bios->fp.if_is_24bit)
593 script |= 0x0200;
594 } else {
595 if (pxclk >= bios->fp.duallink_transition_clk) {
596 script |= 0x0100;
597 if (bios->fp.strapless_is_24bit & 2)
598 script |= 0x0200;
599 } else
600 if (bios->fp.strapless_is_24bit & 1)
601 script |= 0x0200;
602
603 if (nv_connector && nv_connector->edid &&
604 (nv_connector->edid->revision >= 4) &&
605 (nv_connector->edid->input & 0x70) >= 0x20)
606 script |= 0x0200;
607 }
608
609 if (nouveau_uscript_lvds >= 0) {
610 NV_INFO(dev, "override script 0x%04x with 0x%04x "
611 "for output LVDS-%d\n", script,
612 nouveau_uscript_lvds, or);
613 script = nouveau_uscript_lvds;
614 }
615 break;
616 case OUTPUT_TMDS:
617 script = (mc >> 8) & 0xf;
618 if (pxclk >= 165000)
619 script |= 0x0100;
620
621 if (nouveau_uscript_tmds >= 0) {
622 NV_INFO(dev, "override script 0x%04x with 0x%04x "
623 "for output TMDS-%d\n", script,
624 nouveau_uscript_tmds, or);
625 script = nouveau_uscript_tmds;
626 }
627 break;
628 case OUTPUT_DP:
629 script = (mc >> 8) & 0xf;
630 break;
631 case OUTPUT_ANALOG:
632 script = 0xff;
633 break;
634 default:
635 NV_ERROR(dev, "modeset on unsupported output type!\n");
636 break;
637 }
638
639 return script;
640 }
641
642 static void
643 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
644 {
645 #if 0
646 struct drm_nouveau_private *dev_priv = dev->dev_private;
647 struct nouveau_channel *chan;
648 struct list_head *entry, *tmp;
649
650 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
651 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
652
653 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
654 chan->nvsw.vblsem_rval);
655 list_del(&chan->nvsw.vbl_wait);
656 }
657 #endif
658 }
659
660 static void
661 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
662 {
663 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
664
665 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
666 nv50_display_vblank_crtc_handler(dev, 0);
667
668 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
669 nv50_display_vblank_crtc_handler(dev, 1);
670
671 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
672 NV50_PDISPLAY_INTR_EN) & ~intr);
673 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
674 }
675
676 static void
677 nv50_display_unk10_handler(struct drm_device *dev)
678 {
679 struct drm_nouveau_private *dev_priv = dev->dev_private;
680 u32 unk30 = nv_rd32(dev, 0x610030), mc;
681 int i, crtc, or = 0, type = OUTPUT_ANY;
682
683 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
684 dev_priv->evo_irq.dcb = NULL;
685
686 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
687
688 /* Determine which CRTC we're dealing with, only 1 ever will be
689 * signalled at the same time with the current nouveau code.
690 */
691 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
692 if (crtc < 0)
693 goto ack;
694
695 /* Nothing needs to be done for the encoder */
696 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
697 if (crtc < 0)
698 goto ack;
699
700 /* Find which encoder was connected to the CRTC */
701 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
702 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
703 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
704 if (!(mc & (1 << crtc)))
705 continue;
706
707 switch ((mc & 0x00000f00) >> 8) {
708 case 0: type = OUTPUT_ANALOG; break;
709 case 1: type = OUTPUT_TV; break;
710 default:
711 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
712 goto ack;
713 }
714
715 or = i;
716 }
717
718 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
719 if (dev_priv->chipset < 0x90 ||
720 dev_priv->chipset == 0x92 ||
721 dev_priv->chipset == 0xa0)
722 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
723 else
724 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
725
726 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
727 if (!(mc & (1 << crtc)))
728 continue;
729
730 switch ((mc & 0x00000f00) >> 8) {
731 case 0: type = OUTPUT_LVDS; break;
732 case 1: type = OUTPUT_TMDS; break;
733 case 2: type = OUTPUT_TMDS; break;
734 case 5: type = OUTPUT_TMDS; break;
735 case 8: type = OUTPUT_DP; break;
736 case 9: type = OUTPUT_DP; break;
737 default:
738 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
739 goto ack;
740 }
741
742 or = i;
743 }
744
745 /* There was no encoder to disable */
746 if (type == OUTPUT_ANY)
747 goto ack;
748
749 /* Disable the encoder */
750 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
751 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
752
753 if (dcb->type == type && (dcb->or & (1 << or))) {
754 nouveau_bios_run_display_table(dev, dcb, -1, 0, -1);
755 dev_priv->evo_irq.dcb = dcb;
756 goto ack;
757 }
758 }
759
760 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
761 ack:
762 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
763 nv_wr32(dev, 0x610030, 0x80000000);
764 }
765
766 static void
767 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
768 {
769 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
770 struct drm_encoder *encoder;
771 uint32_t tmp, unk0 = 0, unk1 = 0;
772
773 if (dcb->type != OUTPUT_DP)
774 return;
775
776 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
777 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
778
779 if (nv_encoder->dcb == dcb) {
780 unk0 = nv_encoder->dp.unk0;
781 unk1 = nv_encoder->dp.unk1;
782 break;
783 }
784 }
785
786 if (unk0 || unk1) {
787 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
788 tmp &= 0xfffffe03;
789 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
790
791 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
792 tmp &= 0xfef080c0;
793 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
794 }
795 }
796
797 static void
798 nv50_display_unk20_handler(struct drm_device *dev)
799 {
800 struct drm_nouveau_private *dev_priv = dev->dev_private;
801 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
802 struct dcb_entry *dcb;
803 int i, crtc, or = 0, type = OUTPUT_ANY;
804
805 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
806 dcb = dev_priv->evo_irq.dcb;
807 if (dcb) {
808 nouveau_bios_run_display_table(dev, dcb, -1, 0, -2);
809 dev_priv->evo_irq.dcb = NULL;
810 }
811
812 /* CRTC clock change requested? */
813 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
814 if (crtc >= 0) {
815 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
816 pclk &= 0x003fffff;
817
818 nv50_crtc_set_clock(dev, crtc, pclk);
819
820 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
821 tmp &= ~0x000000f;
822 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
823 }
824
825 /* Nothing needs to be done for the encoder */
826 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
827 if (crtc < 0)
828 goto ack;
829 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
830
831 /* Find which encoder is connected to the CRTC */
832 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
833 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
834 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
835 if (!(mc & (1 << crtc)))
836 continue;
837
838 switch ((mc & 0x00000f00) >> 8) {
839 case 0: type = OUTPUT_ANALOG; break;
840 case 1: type = OUTPUT_TV; break;
841 default:
842 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
843 goto ack;
844 }
845
846 or = i;
847 }
848
849 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
850 if (dev_priv->chipset < 0x90 ||
851 dev_priv->chipset == 0x92 ||
852 dev_priv->chipset == 0xa0)
853 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
854 else
855 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
856
857 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
858 if (!(mc & (1 << crtc)))
859 continue;
860
861 switch ((mc & 0x00000f00) >> 8) {
862 case 0: type = OUTPUT_LVDS; break;
863 case 1: type = OUTPUT_TMDS; break;
864 case 2: type = OUTPUT_TMDS; break;
865 case 5: type = OUTPUT_TMDS; break;
866 case 8: type = OUTPUT_DP; break;
867 case 9: type = OUTPUT_DP; break;
868 default:
869 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
870 goto ack;
871 }
872
873 or = i;
874 }
875
876 if (type == OUTPUT_ANY)
877 goto ack;
878
879 /* Enable the encoder */
880 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
881 dcb = &dev_priv->vbios.dcb.entry[i];
882 if (dcb->type == type && (dcb->or & (1 << or)))
883 break;
884 }
885
886 if (i == dev_priv->vbios.dcb.entries) {
887 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
888 goto ack;
889 }
890
891 script = nv50_display_script_select(dev, dcb, mc, pclk);
892 nouveau_bios_run_display_table(dev, dcb, -1, script, pclk);
893
894 nv50_display_unk20_dp_hack(dev, dcb);
895
896 if (dcb->type != OUTPUT_ANALOG) {
897 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
898 tmp &= ~0x00000f0f;
899 if (script & 0x0100)
900 tmp |= 0x00000101;
901 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
902 } else {
903 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
904 }
905
906 dev_priv->evo_irq.dcb = dcb;
907 dev_priv->evo_irq.pclk = pclk;
908 dev_priv->evo_irq.script = script;
909
910 ack:
911 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
912 nv_wr32(dev, 0x610030, 0x80000000);
913 }
914
915 /* If programming a TMDS output on a SOR that can also be configured for
916 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
917 *
918 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
919 * the VBIOS scripts on at least one board I have only switch it off on
920 * link 0, causing a blank display if the output has previously been
921 * programmed for DisplayPort.
922 */
923 static void
924 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
925 {
926 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
927 struct drm_encoder *encoder;
928 u32 tmp;
929
930 if (dcb->type != OUTPUT_TMDS)
931 return;
932
933 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
934 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
935
936 if (nv_encoder->dcb->type == OUTPUT_DP &&
937 nv_encoder->dcb->or & (1 << or)) {
938 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
939 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
940 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
941 break;
942 }
943 }
944 }
945
946 static void
947 nv50_display_unk40_handler(struct drm_device *dev)
948 {
949 struct drm_nouveau_private *dev_priv = dev->dev_private;
950 struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
951 u16 script = dev_priv->evo_irq.script;
952 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
953
954 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
955 dev_priv->evo_irq.dcb = NULL;
956 if (!dcb)
957 goto ack;
958
959 nouveau_bios_run_display_table(dev, dcb, -1, script, -pclk);
960 nv50_display_unk40_dp_set_tmds(dev, dcb);
961
962 ack:
963 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
964 nv_wr32(dev, 0x610030, 0x80000000);
965 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
966 }
967
968 void
969 nv50_display_irq_handler_bh(struct work_struct *work)
970 {
971 struct drm_nouveau_private *dev_priv =
972 container_of(work, struct drm_nouveau_private, irq_work);
973 struct drm_device *dev = dev_priv->dev;
974 BUG_ON(dev_priv->card_type >= NV_D0);
975
976 for (;;) {
977 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
978 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
979
980 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
981
982 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
983 nv50_display_unk10_handler(dev);
984 else
985 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
986 nv50_display_unk20_handler(dev);
987 else
988 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
989 nv50_display_unk40_handler(dev);
990 else
991 break;
992 }
993
994 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
995 }
996
997 static void
998 nv50_display_error_handler(struct drm_device *dev)
999 {
1000 uint32_t addr, data;
1001
1002 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
1003 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
1004 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
1005
1006 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
1007 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
1008
1009 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
1010 }
1011
1012 void
1013 nv50_display_irq_hotplug_bh(struct work_struct *work)
1014 {
1015 struct drm_nouveau_private *dev_priv =
1016 container_of(work, struct drm_nouveau_private, hpd_work);
1017 struct drm_device *dev = dev_priv->dev;
1018 struct drm_connector *connector;
1019 uint32_t unplug_mask, plug_mask, change_mask;
1020 uint32_t hpd0, hpd1 = 0, changed = 0;
1021
1022 hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1023 if (dev_priv->chipset >= 0x90)
1024 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1025
1026 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1027 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1028 change_mask = plug_mask | unplug_mask;
1029
1030 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1031 struct drm_encoder_helper_funcs *helper;
1032 struct nouveau_connector *nv_connector =
1033 nouveau_connector(connector);
1034 struct nouveau_encoder *nv_encoder;
1035 struct dcb_gpio_entry *gpio;
1036 bool plugged;
1037 uint32_t mode;
1038
1039 if (!nv_connector->dcb)
1040 continue;
1041
1042 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1043 if (!gpio || !(change_mask & (1 << gpio->line)))
1044 continue;
1045
1046 plugged = dev_priv->engine.gpio.get(dev, nv_connector->dcb->gpio_tag);
1047 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1048 drm_get_connector_name(connector)) ;
1049
1050 if (!connector->encoder || !connector->encoder->crtc ||
1051 !connector->encoder->crtc->enabled)
1052 continue;
1053 nv_encoder = nouveau_encoder(connector->encoder);
1054 helper = connector->encoder->helper_private;
1055
1056 if (nv_encoder->dcb->type != OUTPUT_DP)
1057 continue;
1058
1059 if (plugged)
1060 mode = DRM_MODE_DPMS_ON;
1061 else
1062 mode = DRM_MODE_DPMS_OFF;
1063 if (mode != nv_encoder->last_dpms) {
1064 changed = 1;
1065 helper->dpms(connector->encoder, mode);
1066 }
1067 }
1068
1069 nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1070 if (dev_priv->chipset >= 0x90)
1071 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
1072
1073 if (changed)
1074 drm_helper_hpd_irq_event(dev);
1075 }
1076
1077 void
1078 nv50_display_irq_handler(struct drm_device *dev)
1079 {
1080 struct drm_nouveau_private *dev_priv = dev->dev_private;
1081 uint32_t delayed = 0;
1082 BUG_ON(dev_priv->card_type >= NV_D0);
1083
1084 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1085 if (!work_pending(&dev_priv->hpd_work))
1086 queue_work(dev_priv->wq, &dev_priv->hpd_work);
1087 }
1088
1089 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1090 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1091 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1092 uint32_t clock;
1093
1094 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1095
1096 if (!intr0 && !(intr1 & ~delayed))
1097 break;
1098
1099 if (intr0 & 0x00010000) {
1100 nv50_display_error_handler(dev);
1101 intr0 &= ~0x00010000;
1102 }
1103
1104 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1105 nv50_display_vblank_handler(dev, intr1);
1106 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1107 }
1108
1109 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1110 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1111 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1112 if (clock) {
1113 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1114 if (!work_pending(&dev_priv->irq_work))
1115 queue_work(dev_priv->wq, &dev_priv->irq_work);
1116 delayed |= clock;
1117 intr1 &= ~clock;
1118 }
1119
1120 if (intr0) {
1121 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1122 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1123 }
1124
1125 if (intr1) {
1126 NV_ERROR(dev,
1127 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1128 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1129 }
1130 }
1131 }
1132
pscnv is an open-source NVIDIA graphics driver developed by PathScale.