Set memory attributes on page

[pscnv.git] / pscnv / nvc0_pgraph.xml.h

#ifndef ___RNNDB____RNNDB_NVC0_PGRAPH_XML
#define ___RNNDB____RNNDB_NVC0_PGRAPH_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng

The rules-ng-ng source files this header was generated from are:
- ../rnndb/../rnndb/nvc0_pgraph.xml (  29811 bytes, from 2011-07-24 02:11:42)
- ../rnndb/copyright.xml            (   6452 bytes, from 2011-07-24 02:11:42)
- ../rnndb/nvchipsets.xml           (   3617 bytes, from 2011-07-24 02:11:42)
- ../rnndb/nv98_fuc.xml             (   8546 bytes, from 2011-10-22 19:16:00)
- ../rnndb/nv50_defs.xml            (   5468 bytes, from 2011-07-24 02:11:42)
- ../rnndb/nv50_pgraph.xml          (  48756 bytes, from 2011-09-20 22:17:16)

Copyright (C) 2006-2011 by the following authors:
- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
- Ben Skeggs (darktama, darktama_)
- B. R. <koala_br@users.sourceforge.net> (koala_br)
- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
- Dmitry Baryshkov
- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
- EdB <edb_@users.sf.net> (edb_)
- Erik Waling <erikwailing@users.sf.net> (erikwaling)
- Francisco Jerez <currojerez@riseup.net> (curro)
- imirkin <imirkin@users.sf.net> (imirkin)
- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
- Mark Carey <mark.carey@gmail.com> (careym)
- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
- Peter Popov <ironpeter@users.sf.net> (ironpeter)
- Richard Hughes <hughsient@users.sf.net> (hughsient)
- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
- Serge Martin
- Simon Raffeiner
- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
- sturmflut <sturmflut@users.sf.net> (sturmflut)
- Sylvain Munaut <tnt@246tNt.com>
- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
- Younes Manton <younes.m@gmail.com> (ymanton)

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


#define NVC0_PGRAPH                                             0x00400000
#define NVC0_PGRAPH__ESIZE                                      0x00200000

#define NVC0_PGRAPH_INTR                                        0x00400100
#define NVC0_PGRAPH_INTR_NOTIFY                                 0x00000001
#define NVC0_PGRAPH_INTR_QUERY                                  0x00000002
#define NVC0_PGRAPH_INTR_SYNC                                   0x00000004
#define NVC0_PGRAPH_INTR_ILLEGAL_MTHD                           0x00000010
#define NVC0_PGRAPH_INTR_ILLEGAL_CLASS                          0x00000020
#define NVC0_PGRAPH_INTR_DOUBLE_NOTIFY                          0x00000040
#define NVC0_PGRAPH_INTR_UNK7                                   0x00000080
#define NVC0_PGRAPH_INTR_FIRMWARE_MTHD                          0x00000100
#define NVC0_PGRAPH_INTR_BUFFER_NOTIFY                          0x00010000
#define NVC0_PGRAPH_INTR_CTXCTL_UP                              0x00080000
#define NVC0_PGRAPH_INTR_DATA_ERROR                             0x00100000
#define NVC0_PGRAPH_INTR_TRAP                                   0x00200000
#define NVC0_PGRAPH_INTR_SINGLE_STEP                            0x01000000

#define NVC0_PGRAPH_TRAP                                        0x00400108
#define NVC0_PGRAPH_TRAP_DISPATCH                               0x00000001
#define NVC0_PGRAPH_TRAP_M2MF                                   0x00000002
#define NVC0_PGRAPH_TRAP_UNK2                                   0x00000004
#define NVC0_PGRAPH_TRAP_CCACHE                                 0x00000008
#define NVC0_PGRAPH_TRAP_UNK4                                   0x00000010
#define NVC0_PGRAPH_TRAP_UNK5                                   0x00000020
#define NVC0_PGRAPH_TRAP_UNK6                                   0x00000040
#define NVC0_PGRAPH_TRAP_MACRO                                  0x00000080
#define NVC0_PGRAPH_TRAP_GPC                                    0x01000000
#define NVC0_PGRAPH_TRAP_ROPC                                   0x02000000

#define NVC0_PGRAPH_DATA_ERROR                                  0x00400110

#define NVC0_PGRAPH_TRAP_GPCS                                   0x00400118

#define NVC0_PGRAPH_TRAP_ROPCS                                  0x0040011c

#define NVC0_PGRAPH_INTR_UNK1                                   0x00400120
#define NVC0_PGRAPH_INTR_UNK1_QUERY                             0x00000002

#define NVC0_PGRAPH_INTR_EN_UNK1                                0x00400124
#define NVC0_PGRAPH_INTR_EN_UNK1_QUERY                          0x00000002

#define NVC0_PGRAPH_TRAP_GPCS_EN                                0x00400130

#define NVC0_PGRAPH_TRAP_ROPCS_EN                               0x00400134

#define NVC0_PGRAPH_TRAP_EN                                     0x00400138
#define NVC0_PGRAPH_TRAP_EN_DISPATCH                            0x00000001
#define NVC0_PGRAPH_TRAP_EN_M2MF                                0x00000002
#define NVC0_PGRAPH_TRAP_EN_UNK2                                0x00000004
#define NVC0_PGRAPH_TRAP_EN_CCACHE                              0x00000008
#define NVC0_PGRAPH_TRAP_EN_UNK4                                0x00000010
#define NVC0_PGRAPH_TRAP_EN_UNK5                                0x00000020
#define NVC0_PGRAPH_TRAP_EN_UNK6                                0x00000040
#define NVC0_PGRAPH_TRAP_EN_MACRO                               0x00000080
#define NVC0_PGRAPH_TRAP_EN_GPC                                 0x01000000
#define NVC0_PGRAPH_TRAP_EN_ROPC                                0x02000000

#define NVC0_PGRAPH_INTR_EN                                     0x0040013c
#define NVC0_PGRAPH_INTR_EN_NOTIFY                              0x00000001
#define NVC0_PGRAPH_INTR_EN_QUERY                               0x00000002
#define NVC0_PGRAPH_INTR_EN_SYNC                                0x00000004
#define NVC0_PGRAPH_INTR_EN_ILLEGAL_MTHD                        0x00000010
#define NVC0_PGRAPH_INTR_EN_ILLEGAL_CLASS                       0x00000020
#define NVC0_PGRAPH_INTR_EN_DOUBLE_NOTIFY                       0x00000040
#define NVC0_PGRAPH_INTR_EN_UNK7                                0x00000080
#define NVC0_PGRAPH_INTR_EN_FIRMWARE_MTHD                       0x00000100
#define NVC0_PGRAPH_INTR_EN_BUFFER_NOTIFY                       0x00010000
#define NVC0_PGRAPH_INTR_EN_CTXCTL_UP                           0x00080000
#define NVC0_PGRAPH_INTR_EN_DATA_ERROR                          0x00100000
#define NVC0_PGRAPH_INTR_EN_TRAP                                0x00200000
#define NVC0_PGRAPH_INTR_EN_SINGLE_STEP                         0x01000000

#define NVC0_PGRAPH_INTR_DISPATCH_CTXCTL_DOWN                   0x00400140
#define NVC0_PGRAPH_INTR_DISPATCH_CTXCTL_DOWN_ILLEGAL_MTHD      0x00000010
#define NVC0_PGRAPH_INTR_DISPATCH_CTXCTL_DOWN_FIRMWARE_MTHD     0x00000100

#define NVC0_PGRAPH_INTR_CTXCTL_DOWN                            0x00400144
#define NVC0_PGRAPH_INTR_CTXCTL_DOWN_ILLEGAL_MTHD               0x00000010
#define NVC0_PGRAPH_INTR_CTXCTL_DOWN_FIRMWARE_MTHD              0x00000100

#define NVC0_PGRAPH_INTR_EN_CTXCTL_DOWN                         0x00400148
#define NVC0_PGRAPH_INTR_EN_CTXCTL_DOWN_ILLEGAL_MTHD            0x00000010
#define NVC0_PGRAPH_INTR_EN_CTXCTL_DOWN_FIRMWARE_MTHD           0x00000100

#define NVC0_PGRAPH_ICMD_CMD                                    0x00400200

#define NVC0_PGRAPH_ICMD_DATA                                   0x00400204

#define NVC0_PGRAPH_FIFO                                        0x00400500

#define NVC0_PGRAPH_FIFO_CONTROL                                0x00400500
#define NVC0_PGRAPH_FIFO_CONTROL_PULL                           0x00000001
#define NVC0_PGRAPH_FIFO_CONTROL_UNK8                           0x00000100
#define NVC0_PGRAPH_FIFO_CONTROL_UNK16                          0x00010000
#define NVC0_PGRAPH_FIFO_CONTROL_LIMIT__MASK                    0x1ff00000
#define NVC0_PGRAPH_FIFO_CONTROL_LIMIT__SHIFT                   20

#define NVC0_PGRAPH_FIFO_STATUS                                 0x00400504
#define NVC0_PGRAPH_FIFO_STATUS_EMPTY                           0x00000001
#define NVC0_PGRAPH_FIFO_STATUS_FULL                            0x00000002
#define NVC0_PGRAPH_FIFO_STATUS_OCCUPIED__MASK                  0x0000fff0
#define NVC0_PGRAPH_FIFO_STATUS_OCCUPIED__SHIFT                 4
#define NVC0_PGRAPH_FIFO_STATUS_GET__MASK                       0x00ff0000
#define NVC0_PGRAPH_FIFO_STATUS_GET__SHIFT                      16
#define NVC0_PGRAPH_FIFO_STATUS_PUT__MASK                       0xff000000
#define NVC0_PGRAPH_FIFO_STATUS_PUT__SHIFT                      24

#define NVC0_PGRAPH_STATUS                                      0x00400700
#define NVC0_PGRAPH_STATUS_ALL                                  0x00000001
#define NVC0_PGRAPH_STATUS_M2MF                                 0x00000040
#define NVC0_PGRAPH_STATUS_CTXCTL                               0x00000080
#define NVC0_PGRAPH_STATUS_GPC                                  0x01000000
#define NVC0_PGRAPH_STATUS_ROPC                                 0x02000000

#define NVC0_PGRAPH_TRAPPED_ADDR                                0x00400704
#define NVC0_PGRAPH_TRAPPED_ADDR_MTHD__MASK                     0x00003ffc
#define NVC0_PGRAPH_TRAPPED_ADDR_MTHD__SHIFT                    2
#define NVC0_PGRAPH_TRAPPED_ADDR_MTHD__SHR                      2
#define NVC0_PGRAPH_TRAPPED_ADDR_SUBCH__MASK                    0x00070000
#define NVC0_PGRAPH_TRAPPED_ADDR_SUBCH__SHIFT                   16

#define NVC0_PGRAPH_TRAPPED_DATA_LOW                            0x00400708

#define NVC0_PGRAPH_TRAPPED_DATA_HIGH                           0x0040070c

#define NVC0_PGRAPH_DISPATCH                                    0x00404000
#define NVC0_PGRAPH_DISPATCH__ESIZE                             0x00000400

#define NVC0_PGRAPH_DISPATCH_TRAP                               0x00404000
#define NVC0_PGRAPH_DISPATCH_TRAP_CLEAR                         0x40000000
#define NVC0_PGRAPH_DISPATCH_TRAP_ENABLE                        0x80000000

#define NVC0_PGRAPH_DISPATCH_CMD_ADDR                           0x00404004
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_MTHD__MASK                0x00001ffc
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_MTHD__SHIFT               2
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_MTHD__SHR                 2
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_SUBCH__MASK               0x00070000
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_SUBCH__SHIFT              16
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_NONINCR                   0x00100000
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_UNK1                      0x00200000
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_SINGLE_STEP_DONE          0x00400000
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_DOUBLE                    0x02000000
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_CURRENT_SUBCH             0x20000000
#define NVC0_PGRAPH_DISPATCH_CMD_ADDR_VALID                     0x80000000

#define NVC0_PGRAPH_DISPATCH_CMD_DATA_LOW                       0x00404008

#define NVC0_PGRAPH_DISPATCH_CMD_DATA_HIGH                      0x0040400c

#define NVC0_PGRAPH_DISPATCH_CTX_SWITCH                         0x00404010

#define NVC0_PGRAPH_DISPATCH_SUBCH                              0x00404024
#define NVC0_PGRAPH_DISPATCH_SUBCH_SUBCH__MASK                  0x0000e000
#define NVC0_PGRAPH_DISPATCH_SUBCH_SUBCH__SHIFT                 13

#define NVC0_PGRAPH_DISPATCH_MISC                               0x00404028
#define NVC0_PGRAPH_DISPATCH_MISC_NOTIFY_PENDING                0x00000100
#define NVC0_PGRAPH_DISPATCH_MISC_NOTIFY_AWAKEN                 0x00010000

#define NVC0_PGRAPH_DISPATCH_ST2_ADDR                           0x0040402c
#define NVC0_PGRAPH_DISPATCH_ST2_ADDR_MTHD__MASK                0x00001ffc
#define NVC0_PGRAPH_DISPATCH_ST2_ADDR_MTHD__SHIFT               2
#define NVC0_PGRAPH_DISPATCH_ST2_ADDR_MTHD__SHR                 2
#define NVC0_PGRAPH_DISPATCH_ST2_ADDR_ILLEGAL_CLASS             0x20000000
#define NVC0_PGRAPH_DISPATCH_ST2_ADDR_ILLEGAL_MTHD              0x40000000
#define NVC0_PGRAPH_DISPATCH_ST2_ADDR_VALID                     0x80000000

#define NVC0_PGRAPH_DISPATCH_ST2_DATA_LOW                       0x0040403c

#define NVC0_PGRAPH_DISPATCH_ST2_DATA_HIGH                      0x00404040

#define NVC0_PGRAPH_DISPATCH_ST3_ADDR                           0x00404048
#define NVC0_PGRAPH_DISPATCH_ST3_ADDR_MTHD__MASK                0x00001ffc
#define NVC0_PGRAPH_DISPATCH_ST3_ADDR_MTHD__SHIFT               2
#define NVC0_PGRAPH_DISPATCH_ST3_ADDR_MTHD__SHR                 2
#define NVC0_PGRAPH_DISPATCH_ST3_ADDR_VALID                     0x80000000

#define NVC0_PGRAPH_DISPATCH_ST3_DATA_LOW                       0x00404050

#define NVC0_PGRAPH_DISPATCH_ST3_DATA_HIGH                      0x00404054

#define NVC0_PGRAPH_DISPATCH_COND_ADDRESS_HIGH                  0x004040c0

#define NVC0_PGRAPH_DISPATCH_COND_ADDRESS_LOW                   0x004040c4

#define NVC0_PGRAPH_DISPATCH_NOTIFY_3D_ADDRESS_HIGH             0x004040d0

#define NVC0_PGRAPH_DISPATCH_NOTIFY_3D_ADDRESS_LOW              0x004040d4

#define NVC0_PGRAPH_DISPATCH_NOTIFY_2D_ADDRESS_HIGH             0x004040d8

#define NVC0_PGRAPH_DISPATCH_NOTIFY_2D_ADDRESS_LOW              0x004040dc

#define NVC0_PGRAPH_DISPATCH_NOTIFY_M2MF_ADDRESS_HIGH           0x004040e0

#define NVC0_PGRAPH_DISPATCH_NOTIFY_M2MF_ADDRESS_LOW            0x004040e4

#define NVC0_PGRAPH_DISPATCH_CTX_CACHE(i0)                     (0x00404200 + 0x4*(i0))
#define NVC0_PGRAPH_DISPATCH_CTX_CACHE__ESIZE                   0x00000004
#define NVC0_PGRAPH_DISPATCH_CTX_CACHE__LEN                     0x00000008

#define NVC0_PGRAPH_MACRO                                       0x00404400
#define NVC0_PGRAPH_MACRO__ESIZE                                0x00000100

#define NVC0_PGRAPH_MACRO_REG(i0)                              (0x00404400 + 0x4*(i0))
#define NVC0_PGRAPH_MACRO_REG__ESIZE                            0x00000004
#define NVC0_PGRAPH_MACRO_REG__LEN                              0x00000008

#define NVC0_PGRAPH_MACRO_MCACHE_CTRL                           0x00404488
#define NVC0_PGRAPH_MACRO_MCACHE_CTRL_CLASS__MASK               0x0000ffff
#define NVC0_PGRAPH_MACRO_MCACHE_CTRL_CLASS__SHIFT              0
#define NVC0_PGRAPH_MACRO_MCACHE_CTRL_MTHD__MASK                0x0fff0000
#define NVC0_PGRAPH_MACRO_MCACHE_CTRL_MTHD__SHIFT               16
#define NVC0_PGRAPH_MACRO_MCACHE_CTRL_MTHD__SHR                 2
#define NVC0_PGRAPH_MACRO_MCACHE_CTRL_READ_TRIGGER              0x40000000
#define NVC0_PGRAPH_MACRO_MCACHE_CTRL_WRITE_TRIGGER             0x80000000

#define NVC0_PGRAPH_MACRO_MCACHE_DATA                           0x0040448c

#define NVC0_PGRAPH_MACRO_TRAP                                  0x00404490
#define NVC0_PGRAPH_MACRO_TRAP_TOO_FEW_PARAMS                   0x00000001
#define NVC0_PGRAPH_MACRO_TRAP_TOO_MANY_PARAMS                  0x00000002
#define NVC0_PGRAPH_MACRO_TRAP_ILLEGAL_OPCODE                   0x00000004
#define NVC0_PGRAPH_MACRO_TRAP_DOUBLE_BRANCH                    0x00000008
#define NVC0_PGRAPH_MACRO_TRAP_CLEAR                            0x40000000
#define NVC0_PGRAPH_MACRO_TRAP_ENABLE                           0x80000000

#define NVC0_PGRAPH_M2MF                                        0x00404600
#define NVC0_PGRAPH_M2MF__ESIZE                                 0x00000200

#define NVC0_PGRAPH_M2MF_TRAP                                   0x00404600
#define NVC0_PGRAPH_M2MF_TRAP_PUSH_TOO_MUCH_DATA                0x00000001
#define NVC0_PGRAPH_M2MF_TRAP_PUSH_NOT_ENOUGH_DATA              0x00000002
#define NVC0_PGRAPH_M2MF_TRAP_CLEAR                             0x40000000
#define NVC0_PGRAPH_M2MF_TRAP_ENABLE                            0x80000000

#define NVC0_PGRAPH_DDATA                                       0x00404800
#define NVC0_PGRAPH_DDATA__ESIZE                                0x00000800

#define NVC0_PGRAPH_UNK5800                                     0x00405800
#define NVC0_PGRAPH_UNK5800__ESIZE                              0x00000800

#define NVC0_PGRAPH_UNK5800_TRAP                                0x00405840
#define NVC0_PGRAPH_UNK5800_TRAP_CLEAR                          0x40000000
#define NVC0_PGRAPH_UNK5800_TRAP_ENABLE                         0x80000000

#define NVC0_PGRAPH_UNK5800_TRAP_UNK44                          0x00405844

#define NVC0_PGRAPH_UNK5800_GPC_TPCNT(i0)                      (0x00405870 + 0x4*(i0))
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT__ESIZE                    0x00000004
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT__LEN                      0x00000004
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_0__MASK                   0x0000000f
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_0__SHIFT                  0
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_1__MASK                   0x000000f0
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_1__SHIFT                  4
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_2__MASK                   0x00000f00
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_2__SHIFT                  8
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_3__MASK                   0x0000f000
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_3__SHIFT                  12
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_4__MASK                   0x000f0000
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_4__SHIFT                  16
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_5__MASK                   0x00f00000
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_5__SHIFT                  20
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_6__MASK                   0x0f000000
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_6__SHIFT                  24
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_7__MASK                   0xf0000000
#define NVC0_PGRAPH_UNK5800_GPC_TPCNT_7__SHIFT                  28

#define NVC0_PGRAPH_UNK6000                                     0x00406000
#define NVC0_PGRAPH_UNK6000__ESIZE                              0x00000800

#define NVC0_PGRAPH_UNK6000_TRAP_UNK0                           0x00406018
#define NVC0_PGRAPH_UNK6000_TRAP_UNK0_CLEAR                     0x40000000
#define NVC0_PGRAPH_UNK6000_TRAP_UNK0_ENABLE                    0x80000000

#define NVC0_PGRAPH_UNK6000_TRAP_UNK1                           0x0040601c
#define NVC0_PGRAPH_UNK6000_TRAP_UNK1_TEMP_TOO_SMALL            0x00000001
#define NVC0_PGRAPH_UNK6000_TRAP_UNK1_CLEAR                     0x40000000
#define NVC0_PGRAPH_UNK6000_TRAP_UNK1_ENABLE                    0x80000000

#define NVC0_PGRAPH_UNK6000_GPC_TPCNT(i0)                      (0x00406028 + 0x4*(i0))
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT__ESIZE                    0x00000004
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT__LEN                      0x00000004
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_0__MASK                   0x0000000f
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_0__SHIFT                  0
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_1__MASK                   0x000000f0
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_1__SHIFT                  4
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_2__MASK                   0x00000f00
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_2__SHIFT                  8
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_3__MASK                   0x0000f000
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_3__SHIFT                  12
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_4__MASK                   0x000f0000
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_4__SHIFT                  16
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_5__MASK                   0x00f00000
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_5__SHIFT                  20
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_6__MASK                   0x0f000000
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_6__SHIFT                  24
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_7__MASK                   0xf0000000
#define NVC0_PGRAPH_UNK6000_GPC_TPCNT_7__SHIFT                  28

#define NVC0_PGRAPH_UNK6000_TP_GPCID(i0)                       (0x004060a8 + 0x4*(i0))
#define NVC0_PGRAPH_UNK6000_TP_GPCID__ESIZE                     0x00000004
#define NVC0_PGRAPH_UNK6000_TP_GPCID__LEN                       0x00000040
#define NVC0_PGRAPH_UNK6000_TP_GPCID_0__MASK                    0x0000001f
#define NVC0_PGRAPH_UNK6000_TP_GPCID_0__SHIFT                   0
#define NVC0_PGRAPH_UNK6000_TP_GPCID_1__MASK                    0x00001f00
#define NVC0_PGRAPH_UNK6000_TP_GPCID_1__SHIFT                   8
#define NVC0_PGRAPH_UNK6000_TP_GPCID_2__MASK                    0x001f0000
#define NVC0_PGRAPH_UNK6000_TP_GPCID_2__SHIFT                   16
#define NVC0_PGRAPH_UNK6000_TP_GPCID_3__MASK                    0x1f000000
#define NVC0_PGRAPH_UNK6000_TP_GPCID_3__SHIFT                   24

#define NVC0_PGRAPH_UNK6000_TEMP_SIZE_PER_MP                    0x004064b0
#define NVC0_PGRAPH_UNK6000_TEMP_SIZE_PER_MP__SHR               8


#define NVC0_PGRAPH_TPGRAD(i0, i1)                             (0x00406800 + 0x400*(i0) + 0x20*(i1))
#define NVC0_PGRAPH_TPGRAD__ESIZE                               0x00000020
#define NVC0_PGRAPH_TPGRAD__LEN                                 0x00000020

#define NVC0_PGRAPH_TPGRAD_MASK(i0, i1, i2)                    (0x00406800 + 0x400*(i0) + 0x20*(i1) + 0x4*(i2))
#define NVC0_PGRAPH_TPGRAD_MASK__ESIZE                          0x00000004
#define NVC0_PGRAPH_TPGRAD_MASK__LEN                            0x00000008

#define NVC0_PGRAPH_TPBUS                                       0x00407800
#define NVC0_PGRAPH_TPBUS__ESIZE                                0x00000800

#define NVC0_PGRAPH_TPBUS_TP_GPCID(i0)                         (0x0040780c + 0x4*(i0))
#define NVC0_PGRAPH_TPBUS_TP_GPCID__ESIZE                       0x00000004
#define NVC0_PGRAPH_TPBUS_TP_GPCID__LEN                         0x0000002c
#define NVC0_PGRAPH_TPBUS_TP_GPCID_0__MASK                      0x0000001f
#define NVC0_PGRAPH_TPBUS_TP_GPCID_0__SHIFT                     0
#define NVC0_PGRAPH_TPBUS_TP_GPCID_1__MASK                      0x000003e0
#define NVC0_PGRAPH_TPBUS_TP_GPCID_1__SHIFT                     5
#define NVC0_PGRAPH_TPBUS_TP_GPCID_2__MASK                      0x00007c00
#define NVC0_PGRAPH_TPBUS_TP_GPCID_2__SHIFT                     10
#define NVC0_PGRAPH_TPBUS_TP_GPCID_3__MASK                      0x000f8000
#define NVC0_PGRAPH_TPBUS_TP_GPCID_3__SHIFT                     15
#define NVC0_PGRAPH_TPBUS_TP_GPCID_4__MASK                      0x01f00000
#define NVC0_PGRAPH_TPBUS_TP_GPCID_4__SHIFT                     20
#define NVC0_PGRAPH_TPBUS_TP_GPCID_5__MASK                      0x3e000000
#define NVC0_PGRAPH_TPBUS_TP_GPCID_5__SHIFT                     25

#define NVC0_PGRAPH_TPBUS_TOTAL                                 0x004078bc
#define NVC0_PGRAPH_TPBUS_TOTAL_ROPC_COUNT__MASK                0x000000ff
#define NVC0_PGRAPH_TPBUS_TOTAL_ROPC_COUNT__SHIFT               0
#define NVC0_PGRAPH_TPBUS_TOTAL_GPC_COUNT__MASK                 0x0000ff00
#define NVC0_PGRAPH_TPBUS_TOTAL_GPC_COUNT__SHIFT                8

#define NVC0_PGRAPH_CCACHE                                      0x00408000
#define NVC0_PGRAPH_CCACHE__ESIZE                               0x00000800

#define NVC0_PGRAPH_CCACHE_HUB2GPC_ADDR                         0x00408004
#define NVC0_PGRAPH_CCACHE_HUB2GPC_ADDR__SHR                    8

#define NVC0_PGRAPH_CCACHE_HUB2GPC_CONF                         0x00408008
#define NVC0_PGRAPH_CCACHE_HUB2GPC_CONF_UNK0__MASK              0x000000ff
#define NVC0_PGRAPH_CCACHE_HUB2GPC_CONF_UNK0__SHIFT             0
#define NVC0_PGRAPH_CCACHE_HUB2GPC_CONF_UNK8__MASK              0x00000700
#define NVC0_PGRAPH_CCACHE_HUB2GPC_CONF_UNK8__SHIFT             8
#define NVC0_PGRAPH_CCACHE_HUB2GPC_CONF_UNK31                   0x80000000

#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_ADDR                      0x0040800c
#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_ADDR__SHR                 8

#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_CONF                      0x00408010
#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_CONF_UNK0__MASK           0x000007ff
#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_CONF_UNK0__SHIFT          0
#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_CONF_UNK11__MASK          0x0000f800
#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_CONF_UNK11__SHIFT         11
#define NVC0_PGRAPH_CCACHE_HUB2ESETUP_CONF_UNK31                0x80000000

#define NVC0_PGRAPH_CCACHE_TRAP                                 0x00408030
#define NVC0_PGRAPH_CCACHE_TRAP_CLEAR                           0x40000000
#define NVC0_PGRAPH_CCACHE_TRAP_ENABLE                          0x80000000

#define NVC0_PGRAPH_CTXCTL                                      0x00409000
#define NVC0_PGRAPH_CTXCTL__ESIZE                               0x00001000



#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER                         0x00409000
#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER_PERIODIC                0x00000001
#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER_WATCHDOG                0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER_FIFO_DATA               0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER_CHANNEL_SWITCH          0x00000008
#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER_EXIT                    0x00000010
#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER_USER1                   0x00000040
#define NVC0_PGRAPH_CTXCTL_INTR_TRIGGER_XFER_FAULT              0x00000200

#define NVC0_PGRAPH_CTXCTL_INTR_ACK                             0x00409004
#define NVC0_PGRAPH_CTXCTL_INTR_ACK_PERIODIC                    0x00000001
#define NVC0_PGRAPH_CTXCTL_INTR_ACK_WATCHDOG                    0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_ACK_FIFO_DATA                   0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_ACK_CHANNEL_SWITCH              0x00000008
#define NVC0_PGRAPH_CTXCTL_INTR_ACK_EXIT                        0x00000010
#define NVC0_PGRAPH_CTXCTL_INTR_ACK_USER1                       0x00000040
#define NVC0_PGRAPH_CTXCTL_INTR_ACK_XFER_FAULT                  0x00000200

#define NVC0_PGRAPH_CTXCTL_INTR                                 0x00409008
#define NVC0_PGRAPH_CTXCTL_INTR_PERIODIC                        0x00000001
#define NVC0_PGRAPH_CTXCTL_INTR_WATCHDOG                        0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_FIFO_DATA                       0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_CHANNEL_SWITCH                  0x00000008
#define NVC0_PGRAPH_CTXCTL_INTR_EXIT                            0x00000010
#define NVC0_PGRAPH_CTXCTL_INTR_USER1                           0x00000040
#define NVC0_PGRAPH_CTXCTL_INTR_XFER_FAULT                      0x00000200

#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET                          0x00409010
#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET_PERIODIC                 0x00000001
#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET_WATCHDOG                 0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET_FIFO_DATA                0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET_CHANNEL_SWITCH           0x00000008
#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET_EXIT                     0x00000010
#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET_USER1                    0x00000040
#define NVC0_PGRAPH_CTXCTL_INTR_EN_SET_XFER_FAULT               0x00000200

#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR                          0x00409014
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR_PERIODIC                 0x00000001
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR_WATCHDOG                 0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR_FIFO_DATA                0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR_CHANNEL_SWITCH           0x00000008
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR_EXIT                     0x00000010
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR_USER1                    0x00000040
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CLR_XFER_FAULT               0x00000200

#define NVC0_PGRAPH_CTXCTL_INTR_EN                              0x00409018
#define NVC0_PGRAPH_CTXCTL_INTR_EN_PERIODIC                     0x00000001
#define NVC0_PGRAPH_CTXCTL_INTR_EN_WATCHDOG                     0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_EN_FIFO_DATA                    0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_EN_CHANNEL_SWITCH               0x00000008
#define NVC0_PGRAPH_CTXCTL_INTR_EN_EXIT                         0x00000010
#define NVC0_PGRAPH_CTXCTL_INTR_EN_USER1                        0x00000040
#define NVC0_PGRAPH_CTXCTL_INTR_EN_XFER_FAULT                   0x00000200

#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING                         0x0040901c
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1__MASK                0x0000ffff
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1__SHIFT               0
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1_PERIODIC             0x00000001
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1_WATCHDOG             0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1_FIFO_DATA            0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1_CHANNEL_SWITCH       0x00000008
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1_EXIT                 0x00000010
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1_USER1                0x00000040
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M1_XFER_FAULT           0x00000200
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2__MASK                0xffff0000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2__SHIFT               16
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2_PERIODIC             0x00010000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2_WATCHDOG             0x00020000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2_FIFO_DATA            0x00040000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2_CHANNEL_SWITCH       0x00080000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2_EXIT                 0x00100000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2_USER1                0x00400000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTING_M2_XFER_FAULT           0x02000000

#define NVC0_PGRAPH_CTXCTL_PERIODIC_PERIOD                      0x00409020

#define NVC0_PGRAPH_CTXCTL_PERIODIC_TIME                        0x00409024

#define NVC0_PGRAPH_CTXCTL_PERIODIC_ENABLE                      0x00409028

#define NVC0_PGRAPH_CTXCTL_TIME_LOW                             0x0040902c

#define NVC0_PGRAPH_CTXCTL_TIME_HIGH                            0x00409030

#define NVC0_PGRAPH_CTXCTL_WATCHDOG_TIME                        0x00409034

#define NVC0_PGRAPH_CTXCTL_WATCHDOG_ENABLE                      0x00409038

#define NVC0_PGRAPH_CTXCTL_SCRATCH(i0)                         (0x00409040 + 0x4*(i0))
#define NVC0_PGRAPH_CTXCTL_SCRATCH__ESIZE                       0x00000004
#define NVC0_PGRAPH_CTXCTL_SCRATCH__LEN                         0x00000002

#define NVC0_PGRAPH_CTXCTL_ACCESS_EN                            0x00409048
#define NVC0_PGRAPH_CTXCTL_ACCESS_EN_CHANNEL_SWITCH             0x00000001
#define NVC0_PGRAPH_CTXCTL_ACCESS_EN_FIFO                       0x00000002

#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR                          0x00409050
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN__MASK               0x3fffffff
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN__SHIFT              0
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__MASK       0x0fffffff
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__SHIFT      0
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__SHR        12
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_TARGET__MASK        0x30000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_TARGET__SHIFT       28
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_TARGET_VRAM         0x00000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_TARGET_SYSRAM       0x20000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_CHAN_TARGET_SYSRAM_NO_SNOOP      0x30000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_CUR_VALID                    0x40000000

#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT                         0x00409054
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN__MASK              0x3fffffff
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN__SHIFT             0
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__MASK      0x0fffffff
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__SHIFT     0
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__SHR       12
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_TARGET__MASK       0x30000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_TARGET__SHIFT      28
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_VRAM        0x00000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_SYSRAM      0x20000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_SYSRAM_NO_SNOOP     0x30000000
#define NVC0_PGRAPH_CTXCTL_CHANNEL_NEXT_VALID                   0x40000000

#define NVC0_PGRAPH_CTXCTL_CHANNEL_TRIGGER                      0x00409054
#define NVC0_PGRAPH_CTXCTL_CHANNEL_TRIGGER_UNLOAD               0x00000001
#define NVC0_PGRAPH_CTXCTL_CHANNEL_TRIGGER_LOAD                 0x00000002

#define NVC0_PGRAPH_CTXCTL_FIFO_DATA                            0x00409064

#define NVC0_PGRAPH_CTXCTL_FIFO_CMD                             0x00409068
#define NVC0_PGRAPH_CTXCTL_FIFO_CMD_MTHD__MASK                  0x000007ff
#define NVC0_PGRAPH_CTXCTL_FIFO_CMD_MTHD__SHIFT                 0
#define NVC0_PGRAPH_CTXCTL_FIFO_CMD_MTHD__SHR                   2
#define NVC0_PGRAPH_CTXCTL_FIFO_CMD_SUBC__MASK                  0x00003800
#define NVC0_PGRAPH_CTXCTL_FIFO_CMD_SUBC__SHIFT                 11
#define NVC0_PGRAPH_CTXCTL_FIFO_CMD_NONINCR                     0x00004000

#define NVC0_PGRAPH_CTXCTL_FIFO_OCCUPIED                        0x00409070

#define NVC0_PGRAPH_CTXCTL_FIFO_ACK                             0x00409074

#define NVC0_PGRAPH_CTXCTL_FIFO_LIMIT                           0x00409078

#define NVC0_PGRAPH_CTXCTL_MISC_TRIGGER                         0x00409088
#define NVC0_PGRAPH_CTXCTL_MISC_TRIGGER_WRCACHE_FLUSH           0x00010000
#define NVC0_PGRAPH_CTXCTL_MISC_TRIGGER_PM_TRIGGER              0x00020000

#define NVC0_PGRAPH_CTXCTL_UC_CTRL                              0x00409100
#define NVC0_PGRAPH_CTXCTL_UC_CTRL_START_TRIGGER                0x00000002
#define NVC0_PGRAPH_CTXCTL_UC_CTRL_RESET_UNK2_TRIGGER           0x00000004
#define NVC0_PGRAPH_CTXCTL_UC_CTRL_RESET_UNK3_TRIGGER           0x00000008
#define NVC0_PGRAPH_CTXCTL_UC_CTRL_STOPPED                      0x00000010
#define NVC0_PGRAPH_CTXCTL_UC_CTRL_SLEEPING                     0x00000020

#define NVC0_PGRAPH_CTXCTL_ENTRY                                0x00409104

#define NVC0_PGRAPH_CTXCTL_CAPS                                 0x00409108
#define NVC0_PGRAPH_CTXCTL_CAPS_CODE_SIZE__MASK                 0x000001ff
#define NVC0_PGRAPH_CTXCTL_CAPS_CODE_SIZE__SHIFT                0
#define NVC0_PGRAPH_CTXCTL_CAPS_CODE_SIZE__SHR                  8
#define NVC0_PGRAPH_CTXCTL_CAPS_DATA_SIZE__MASK                 0x0001fe00
#define NVC0_PGRAPH_CTXCTL_CAPS_DATA_SIZE__SHIFT                9
#define NVC0_PGRAPH_CTXCTL_CAPS_DATA_SIZE__SHR                  8

#define NVC0_PGRAPH_CTXCTL_XFER_EXT_BASE                        0x00409110
#define NVC0_PGRAPH_CTXCTL_XFER_EXT_BASE__SHR                   8

#define NVC0_PGRAPH_CTXCTL_XFER_FUC_ADDR                        0x00409114

#define NVC0_PGRAPH_CTXCTL_XFER_CTRL                            0x00409118
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_FULL                       0x00000001
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SEG__MASK                  0x00000010
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SEG__SHIFT                 4
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SEG_DATA                   0x00000000
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SEG_CODE                   0x00000010
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_DIR__MASK                  0x00000020
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_DIR__SHIFT                 5
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_DIR_LOAD                   0x00000000
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_DIR_STORE                  0x00000020
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SIZE__MASK                 0x00000700
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SIZE__SHIFT                8
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SIZE_16                    0x00000200
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SIZE_32                    0x00000300
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SIZE_64                    0x00000400
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SIZE_128                   0x00000500
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_SIZE_256                   0x00000600
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_TARGET__MASK               0x00007000
#define NVC0_PGRAPH_CTXCTL_XFER_CTRL_TARGET__SHIFT              12

#define NVC0_PGRAPH_CTXCTL_XFER_EXT_ADDR                        0x0040911c

#define NVC0_PGRAPH_CTXCTL_XFER_STATUS                          0x00409120
#define NVC0_PGRAPH_CTXCTL_XFER_STATUS_PENDING                  0x00000002
#define NVC0_PGRAPH_CTXCTL_XFER_STATUS_UNK4__MASK               0x00000030
#define NVC0_PGRAPH_CTXCTL_XFER_STATUS_UNK4__SHIFT              4
#define NVC0_PGRAPH_CTXCTL_XFER_STATUS_STORES_PENDING__MASK     0x00070000
#define NVC0_PGRAPH_CTXCTL_XFER_STATUS_STORES_PENDING__SHIFT    16
#define NVC0_PGRAPH_CTXCTL_XFER_STATUS_LOADS_PENDING__MASK      0x07000000
#define NVC0_PGRAPH_CTXCTL_XFER_STATUS_LOADS_PENDING__SHIFT     24

#define NVC0_PGRAPH_CTXCTL_UC_STATUS                            0x00409128
#define NVC0_PGRAPH_CTXCTL_UC_STATUS_XCLD_IDLE                  0x00000004
#define NVC0_PGRAPH_CTXCTL_UC_STATUS_CRYPT_IDLE                 0x00000008
#define NVC0_PGRAPH_CTXCTL_UC_STATUS_TRAP_ACTIVE                0x00000100
#define NVC0_PGRAPH_CTXCTL_UC_STATUS_XDST_IDLE                  0x00040000
#define NVC0_PGRAPH_CTXCTL_UC_STATUS_XDLD_IDLE                  0x00080000

#define NVC0_PGRAPH_CTXCTL_CAPS2                                0x0040912c
#define NVC0_PGRAPH_CTXCTL_CAPS2_UNK0__MASK                     0x0000000f
#define NVC0_PGRAPH_CTXCTL_CAPS2_UNK0__SHIFT                    0
#define NVC0_PGRAPH_CTXCTL_CAPS2_SECRETFUL__MASK                0x000000f0
#define NVC0_PGRAPH_CTXCTL_CAPS2_SECRETFUL__SHIFT               4
#define NVC0_PGRAPH_CTXCTL_CAPS2_CODE_PORTS__MASK               0x00000f00
#define NVC0_PGRAPH_CTXCTL_CAPS2_CODE_PORTS__SHIFT              8
#define NVC0_PGRAPH_CTXCTL_CAPS2_DATA_PORTS__MASK               0x0000f000
#define NVC0_PGRAPH_CTXCTL_CAPS2_DATA_PORTS__SHIFT              12
#define NVC0_PGRAPH_CTXCTL_CAPS2_VM_PAGES_LOG2__MASK            0x000f0000
#define NVC0_PGRAPH_CTXCTL_CAPS2_VM_PAGES_LOG2__SHIFT           16

#define NVC0_PGRAPH_CTXCTL_TLB_CMD                              0x00409140
#define NVC0_PGRAPH_CTXCTL_TLB_CMD_PARAM__MASK                  0x00ffffff
#define NVC0_PGRAPH_CTXCTL_TLB_CMD_PARAM__SHIFT                 0
#define NVC0_PGRAPH_CTXCTL_TLB_CMD_CMD__MASK                    0x03000000
#define NVC0_PGRAPH_CTXCTL_TLB_CMD_CMD__SHIFT                   24
#define NVC0_PGRAPH_CTXCTL_TLB_CMD_CMD_ITLB                     0x01000000
#define NVC0_PGRAPH_CTXCTL_TLB_CMD_CMD_PTLB                     0x02000000
#define NVC0_PGRAPH_CTXCTL_TLB_CMD_CMD_VTLB                     0x03000000

#define NVC0_PGRAPH_CTXCTL_TLB_CMD_RES                          0x00409144

#define NVC0_PGRAPH_CTXCTL_CODE_INDEX                           0x00409180
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_PHYS_ADDR__MASK           0x0000fffc
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_PHYS_ADDR__SHIFT          2
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_PHYS_ADDR__SHR            2
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_WRITE_AUTOINCR            0x01000000
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_READ_AUTOINCR             0x02000000
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_SECRET                    0x10000000
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_SECRET_LOCKDOWN           0x20000000
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_SECRET_FAIL               0x40000000
#define NVC0_PGRAPH_CTXCTL_CODE_INDEX_SECRET_SCRUBBER_ACTIVE    0x80000000

#define NVC0_PGRAPH_CTXCTL_CODE                                 0x00409184

#define NVC0_PGRAPH_CTXCTL_CODE_VIRT_ADDR                       0x00409188
#define NVC0_PGRAPH_CTXCTL_CODE_VIRT_ADDR__SHR                  8

#define NVC0_PGRAPH_CTXCTL_DATA_INDEX(i0)                      (0x004091c0 + 0x8*(i0))
#define NVC0_PGRAPH_CTXCTL_DATA_INDEX__ESIZE                    0x00000008
#define NVC0_PGRAPH_CTXCTL_DATA_INDEX__LEN                      0x00000008
#define NVC0_PGRAPH_CTXCTL_DATA_INDEX_ADDR__MASK                0x0000fffc
#define NVC0_PGRAPH_CTXCTL_DATA_INDEX_ADDR__SHIFT               2
#define NVC0_PGRAPH_CTXCTL_DATA_INDEX_ADDR__SHR                 2
#define NVC0_PGRAPH_CTXCTL_DATA_INDEX_WRITE_AUTOINCR            0x01000000
#define NVC0_PGRAPH_CTXCTL_DATA_INDEX_READ_AUTOINCR             0x02000000

#define NVC0_PGRAPH_CTXCTL_DATA(i0)                            (0x004091c4 + 0x8*(i0))
#define NVC0_PGRAPH_CTXCTL_DATA__ESIZE                          0x00000008
#define NVC0_PGRAPH_CTXCTL_DATA__LEN                            0x00000008

#define NVC0_PGRAPH_CTXCTL_PC                                   0x00409ff0

#define NVC0_PGRAPH_CTXCTL_UPLOAD                               0x00409ff4

#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR                          0x00409ff8
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_ADDR__MASK               0x0000fffc
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_ADDR__SHIFT              2
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_ADDR__SHR                2
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_SEG__MASK                0x00100000
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_SEG__SHIFT               20
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_SEG_DATA                 0x00000000
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_SEG_CODE                 0x00100000
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_READBACK                 0x00200000
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_XFER_BUSY                0x01000000
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_SECRET                   0x10000000
#define NVC0_PGRAPH_CTXCTL_UPLOAD_ADDR_CODE_BUSY                0x20000000

#define NVC0_PGRAPH_CTXCTL_HOST_IO_INDEX                        0x00409ffc

#define NVC0_PGRAPH_CTXCTL_DONE                                 0x00409400
#define NVC0_PGRAPH_CTXCTL_DONE_STRAND                          0x00000004
#define NVC0_PGRAPH_CTXCTL_DONE_MMCTX                           0x00000020
#define NVC0_PGRAPH_CTXCTL_DONE_MMIO_RD                         0x00000040
#define NVC0_PGRAPH_CTXCTL_DONE_MMIO_WRS                        0x00000080
#define NVC0_PGRAPH_CTXCTL_DONE_BAR                             0x00000100
#define NVC0_PGRAPH_CTXCTL_DONE_CC_WATCHDOG                     0x00000800
#define NVC0_PGRAPH_CTXCTL_DONE_UNK12                           0x00001000
#define NVC0_PGRAPH_CTXCTL_DONE_UNK13                           0x00002000

#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE                           0x00409404
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0__MASK                0x0000003f
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0__SHIFT               0
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_GPC_UNK2             0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_HUB_CHANNEL_SWITCH   0x00000003
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_HUB_UNK4             0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_HUB_CTXCTL_DOWN      0x0000000b
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_HUB_UNK12            0x0000000c
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_ZERO                 0x00000020
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_STRAND               0x00000022
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_MMCTX                0x00000025
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_MMIO_RD              0x00000026
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_MMIO_WRS             0x00000027
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_BAR                  0x00000028
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_CC_WATCHDOG          0x0000002b
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_UNK12                0x0000002c
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC0_UNK13                0x0000002d
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1__MASK                0x00003f00
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1__SHIFT               8
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_GPC_UNK2             0x00000200
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_HUB_CHANNEL_SWITCH   0x00000300
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_HUB_UNK4             0x00000400
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_HUB_CTXCTL_DOWN      0x00000b00
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_HUB_UNK12            0x00000c00
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_ZERO                 0x00002000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_STRAND               0x00002200
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_MMCTX                0x00002500
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_MMIO_RD              0x00002600
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_MMIO_WRS             0x00002700
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_BAR                  0x00002800
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_CC_WATCHDOG          0x00002b00
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_UNK12                0x00002c00
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_SRC1_UNK13                0x00002d00
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_FUN__MASK                 0x00010000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_FUN__SHIFT                16
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_FUN_OR                    0x00000000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_FUN_AND                   0x00010000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_NOT                       0x00020000
#define NVC0_PGRAPH_CTXCTL_INTR_ROUTE_LEVEL                     0x00040000

#define NVC0_PGRAPH_CTXCTL_BAR_REQMASK(i0)                     (0x0040940c + 0x4*(i0))
#define NVC0_PGRAPH_CTXCTL_BAR_REQMASK__ESIZE                   0x00000004
#define NVC0_PGRAPH_CTXCTL_BAR_REQMASK__LEN                     0x00000002

#define NVC0_PGRAPH_CTXCTL_BAR                                  0x00409414

#define NVC0_PGRAPH_CTXCTL_BAR_SET                              0x00409418

#define NVC0_PGRAPH_CTXCTL_CC_WATCHDOG                          0x00409430
#define NVC0_PGRAPH_CTXCTL_CC_WATCHDOG_TIME_REMAINING__MASK     0x3fffffff
#define NVC0_PGRAPH_CTXCTL_CC_WATCHDOG_TIME_REMAINING__SHIFT    0
#define NVC0_PGRAPH_CTXCTL_CC_WATCHDOG_ENABLE                   0x80000000

#define NVC0_PGRAPH_CTXCTL_WRCMD_DATA                           0x00409500

#define NVC0_PGRAPH_CTXCTL_WRCMD_CMD                            0x00409504

#define NVC0_PGRAPH_CTXCTL_NEW_CAPS                             0x00409620
#define NVC0_PGRAPH_CTXCTL_NEW_CAPS_CODE_SIZE__MASK             0x000000ff
#define NVC0_PGRAPH_CTXCTL_NEW_CAPS_CODE_SIZE__SHIFT            0
#define NVC0_PGRAPH_CTXCTL_NEW_CAPS_CODE_SIZE__SHR              8
#define NVC0_PGRAPH_CTXCTL_NEW_CAPS_DATA_SIZE__MASK             0x0000ff00
#define NVC0_PGRAPH_CTXCTL_NEW_CAPS_DATA_SIZE__SHIFT            8
#define NVC0_PGRAPH_CTXCTL_NEW_CAPS_DATA_SIZE__SHR              8

#define NVC0_PGRAPH_CTXCTL_MMCTX_SAVE_SWBASE                    0x00409700
#define NVC0_PGRAPH_CTXCTL_MMCTX_SAVE_SWBASE__SHR               8

#define NVC0_PGRAPH_CTXCTL_MMCTX_LOAD_SWBASE                    0x00409704
#define NVC0_PGRAPH_CTXCTL_MMCTX_LOAD_SWBASE__SHR               8

#define NVC0_PGRAPH_CTXCTL_MMCTX_BASE                           0x00409710

#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL                           0x00409714
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_QFREE__MASK               0x0000001f
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_QFREE__SHIFT              0
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_QLIMIT__MASK              0x00001f00
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_QLIMIT__SHIFT             8
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_DIR__MASK                 0x00010000
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_DIR__SHIFT                16
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_DIR_SAVE                  0x00000000
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_DIR_LOAD                  0x00010000
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_START_TRIGGER             0x00020000
#define NVC0_PGRAPH_CTXCTL_MMCTX_CTRL_STOP_TRIGGER              0x00040000

#define NVC0_PGRAPH_CTXCTL_MMCTX_MULTI_STRIDE                   0x00409718

#define NVC0_PGRAPH_CTXCTL_MMCTX_MULTI_MASK                     0x0040971c

#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE                          0x00409720
#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE_BASE_EN                  0x00000001
#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE_MULTI_EN                 0x00000002
#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE_ADDR__MASK               0x03fffffc
#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE_ADDR__SHIFT              2
#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE_ADDR__SHR                2
#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE_CNTM1__MASK              0xfc000000
#define NVC0_PGRAPH_CTXCTL_MMCTX_QUEUE_CNTM1__SHIFT             26

#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL                            0x00409728
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_UNK0                       0x00000001
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_ADDR__MASK                 0x03fffffc
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_ADDR__SHIFT                2
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_ADDR__SHR                  2
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_WRS                        0x20000000
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_ACCESS__MASK               0x40000000
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_ACCESS__SHIFT              30
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_ACCESS_READ                0x00000000
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_ACCESS_WRITE               0x40000000
#define NVC0_PGRAPH_CTXCTL_MMIO_CTRL_TRIGGER                    0x80000000

#define NVC0_PGRAPH_CTXCTL_MMIO_RDVAL                           0x0040972c

#define NVC0_PGRAPH_CTXCTL_MMIO_WRVAL                           0x00409730

#define NVC0_PGRAPH_CTXCTL_MMCTX_LOAD_COUNT                     0x0040974c

#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH(i0)                      (0x00409800 + 0x4*(i0))
#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH__ESIZE                    0x00000004
#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH__LEN                      0x00000008

#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH_SET(i0)                  (0x00409820 + 0x4*(i0))
#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH_SET__ESIZE                0x00000004
#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH_SET__LEN                  0x00000008

#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH_CLEAR(i0)                (0x00409840 + 0x4*(i0))
#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH_CLEAR__ESIZE              0x00000004
#define NVC0_PGRAPH_CTXCTL_CC_SCRATCH_CLEAR__LEN                0x00000008

#define NVC0_PGRAPH_CTXCTL_STRANDS                              0x00409880

#define NVC0_PGRAPH_CTXCTL_STRAND_SAVE_SWBASE                   0x00409908
#define NVC0_PGRAPH_CTXCTL_STRAND_SAVE_SWBASE__SHR              8

#define NVC0_PGRAPH_CTXCTL_STRAND_LOAD_SWBASE                   0x0040990c
#define NVC0_PGRAPH_CTXCTL_STRAND_LOAD_SWBASE__SHR              8

#define NVC0_PGRAPH_CTXCTL_STRAND_SIZE                          0x00409910

#define NVC0_PGRAPH_CTXCTL_STRAND_GENE_CNT                      0x00409918

#define NVC0_PGRAPH_CTXCTL_STRAND_FIRST_GENE                    0x0040991c

#define NVC0_PGRAPH_CTXCTL_STRAND_CMD                           0x00409928
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_LATCH_FIRST_GENE          0x00000001
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_LATCH_GENE_CNT            0x00000002
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_SAVE                      0x00000003
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_LOAD                      0x00000004
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_UNK5                      0x00000005
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_UNKA                      0x0000000a
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_UNKB                      0x0000000b
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_UNKC                      0x0000000c
#define NVC0_PGRAPH_CTXCTL_STRAND_CMD_UNKD                      0x0000000d

#define NVC0_PGRAPH_CTXCTL_MEM_BASE                             0x00409a04
#define NVC0_PGRAPH_CTXCTL_MEM_BASE__SHR                        8

#define NVC0_PGRAPH_CTXCTL_MEM_CHAN                             0x00409a0c
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_ADDRESS__MASK               0x0fffffff
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_ADDRESS__SHIFT              0
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_ADDRESS__SHR                12
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_TARGET__MASK                0x30000000
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_TARGET__SHIFT               28
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_TARGET_VRAM                 0x00000000
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_TARGET_SYSRAM               0x20000000
#define NVC0_PGRAPH_CTXCTL_MEM_CHAN_TARGET_SYSRAM_NO_SNOOP      0x30000000

#define NVC0_PGRAPH_CTXCTL_MEM_CMD                              0x00409a10
#define NVC0_PGRAPH_CTXCTL_MEM_CMD_LOAD_CHAN                    0x00000007

#define NVC0_PGRAPH_CTXCTL_MEM_TARGET                           0x00409a20
#define NVC0_PGRAPH_CTXCTL_MEM_TARGET_TARGET__MASK              0x0000001f
#define NVC0_PGRAPH_CTXCTL_MEM_TARGET_TARGET__SHIFT             0
#define NVC0_PGRAPH_CTXCTL_MEM_TARGET_TARGET_VM                 0x00000001
#define NVC0_PGRAPH_CTXCTL_MEM_TARGET_TARGET_VRAM               0x00000002
#define NVC0_PGRAPH_CTXCTL_MEM_TARGET_TARGET_SYSRAM_NOSNOOP     0x00000003
#define NVC0_PGRAPH_CTXCTL_MEM_TARGET_TARGET_SYSRAM             0x00000004
#define NVC0_PGRAPH_CTXCTL_MEM_TARGET_UNK31                     0x80000000

#define NVC0_PGRAPH_CTXCTL_UNITS                                0x00409604
#define NVC0_PGRAPH_CTXCTL_UNITS_GPC_COUNT__MASK                0x0000001f
#define NVC0_PGRAPH_CTXCTL_UNITS_GPC_COUNT__SHIFT               0
#define NVC0_PGRAPH_CTXCTL_UNITS_ROPC_COUNT__MASK               0x001f0000
#define NVC0_PGRAPH_CTXCTL_UNITS_ROPC_COUNT__SHIFT              16

#define NVC0_PGRAPH_CTXCTL_RED_SWITCH                           0x00409614
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_UNK0_MAIN                 0x00000001
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_UNK0_GPC                  0x00000002
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_POWER_MAIN                0x00000010
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_POWER_GPC                 0x00000020
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_POWER_ROPC                0x00000040
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_ENABLE_MAIN               0x00000100
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_ENABLE_GPC                0x00000200
#define NVC0_PGRAPH_CTXCTL_RED_SWITCH_ENABLE_ROPC               0x00000400

#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE                        0x00409c14
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0__MASK             0x0000003f
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0__SHIFT            0
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_GPC_UNK2          0x00000002
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_HUB_CHANNEL_SWITCH        0x00000003
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_HUB_UNK4          0x00000004
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_HUB_CTXCTL_DOWN   0x0000000b
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_HUB_UNK12         0x0000000c
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_ZERO              0x00000020
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_STRAND            0x00000022
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_MMCTX             0x00000025
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_MMIO_RD           0x00000026
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_MMIO_WRS          0x00000027
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_BAR               0x00000028
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_CC_WATCHDOG       0x0000002b
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_UNK12             0x0000002c
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC0_UNK13             0x0000002d
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1__MASK             0x00003f00
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1__SHIFT            8
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_GPC_UNK2          0x00000200
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_HUB_CHANNEL_SWITCH        0x00000300
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_HUB_UNK4          0x00000400
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_HUB_CTXCTL_DOWN   0x00000b00
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_HUB_UNK12         0x00000c00
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_ZERO              0x00002000
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_STRAND            0x00002200
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_MMCTX             0x00002500
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_MMIO_RD           0x00002600
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_MMIO_WRS          0x00002700
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_BAR               0x00002800
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_CC_WATCHDOG       0x00002b00
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_UNK12             0x00002c00
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_SRC1_UNK13             0x00002d00
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_FUN__MASK              0x00010000
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_FUN__SHIFT             16
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_FUN_OR                 0x00000000
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_FUN_AND                0x00010000
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_NOT                    0x00020000
#define NVC0_PGRAPH_CTXCTL_INTR_UP_ROUTE_LEVEL                  0x00040000

#define NVC0_PGRAPH_CTXCTL_INTR_UP_STATUS                       0x00409c18

#define NVC0_PGRAPH_CTXCTL_INTR_UP_SET                          0x00409c1c

#define NVC0_PGRAPH_CTXCTL_INTR_UP_CLEAR                        0x00409c20

#define NVC0_PGRAPH_CTXCTL_INTR_UP_ENABLE                       0x00409c24

#define NVC0_PGRAPH_ROPC_BROADCAST                              0x00408800
#define NVC0_PGRAPH_ROPC_BROADCAST__ESIZE                       0x00000400


#define NVC0_PGRAPH_ROPC_BROADCAST_ZROP                         0x00408800
#define NVC0_PGRAPH_ROPC_BROADCAST_ZROP__ESIZE                  0x00000100

#define NVC0_PGRAPH_ROPC_BROADCAST_ZROP_TRAP                    0x00408870
#define NVC0_PGRAPH_ROPC_BROADCAST_ZROP_TRAP_CLEAR              0x40000000
#define NVC0_PGRAPH_ROPC_BROADCAST_ZROP_TRAP_ENABLE             0x80000000

#define NVC0_PGRAPH_ROPC_BROADCAST_CROP                         0x00408900
#define NVC0_PGRAPH_ROPC_BROADCAST_CROP__ESIZE                  0x00000100

#define NVC0_PGRAPH_ROPC_BROADCAST_CROP_TRAP                    0x00408944
#define NVC0_PGRAPH_ROPC_BROADCAST_CROP_TRAP_CLEAR              0x40000000
#define NVC0_PGRAPH_ROPC_BROADCAST_CROP_TRAP_ENABLE             0x80000000

#define NVC0_PGRAPH_ROPC_BROADCAST_TRAP                         0x00408a04
#define NVC0_PGRAPH_ROPC_BROADCAST_TRAP_CROP                    0x00000001
#define NVC0_PGRAPH_ROPC_BROADCAST_TRAP_ZROP                    0x00000002

#define NVC0_PGRAPH_ROPC_BROADCAST_TRAP_EN                      0x00408a08
#define NVC0_PGRAPH_ROPC_BROADCAST_TRAP_EN_CROP                 0x00000001
#define NVC0_PGRAPH_ROPC_BROADCAST_TRAP_EN_ZROP                 0x00000002

#define NVC0_PGRAPH_ROPC_BROADCAST_RED_SWITCH                   0x00408a10
#define NVC0_PGRAPH_ROPC_BROADCAST_RED_SWITCH_UNK0_ROPC         0x00000004
#define NVC0_PGRAPH_ROPC_BROADCAST_RED_SWITCH_POWER_ROPC        0x00000040
#define NVC0_PGRAPH_ROPC_BROADCAST_RED_SWITCH_ENABLE_ROPC       0x00000400

#define NVC0_PGRAPH_ROPC(i0)                                   (0x00410000 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC__ESIZE                                 0x00000400
#define NVC0_PGRAPH_ROPC__LEN                                   0x00000008


#define NVC0_PGRAPH_ROPC_ZROP(i0)                              (0x00410000 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC_ZROP__ESIZE                            0x00000100

#define NVC0_PGRAPH_ROPC_ZROP_TRAP(i0)                         (0x00410070 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC_ZROP_TRAP_CLEAR                        0x40000000
#define NVC0_PGRAPH_ROPC_ZROP_TRAP_ENABLE                       0x80000000

#define NVC0_PGRAPH_ROPC_CROP(i0)                              (0x00410100 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC_CROP__ESIZE                            0x00000100

#define NVC0_PGRAPH_ROPC_CROP_TRAP(i0)                         (0x00410144 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC_CROP_TRAP_CLEAR                        0x40000000
#define NVC0_PGRAPH_ROPC_CROP_TRAP_ENABLE                       0x80000000

#define NVC0_PGRAPH_ROPC_TRAP(i0)                              (0x00410204 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC_TRAP_CROP                              0x00000001
#define NVC0_PGRAPH_ROPC_TRAP_ZROP                              0x00000002

#define NVC0_PGRAPH_ROPC_TRAP_EN(i0)                           (0x00410208 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC_TRAP_EN_CROP                           0x00000001
#define NVC0_PGRAPH_ROPC_TRAP_EN_ZROP                           0x00000002

#define NVC0_PGRAPH_ROPC_RED_SWITCH(i0)                        (0x00410210 + 0x400*(i0))
#define NVC0_PGRAPH_ROPC_RED_SWITCH_UNK0_ROPC                   0x00000004
#define NVC0_PGRAPH_ROPC_RED_SWITCH_POWER_ROPC                  0x00000040
#define NVC0_PGRAPH_ROPC_RED_SWITCH_ENABLE_ROPC                 0x00000400

#define NVC0_PGRAPH_GPC_BROADCAST                               0x00418000
#define NVC0_PGRAPH_GPC_BROADCAST__ESIZE                        0x00008000


#define NVC0_PGRAPH_GPC_BROADCAST_UNK380                        0x00418380
#define NVC0_PGRAPH_GPC_BROADCAST_UNK380__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_PROP                          0x00418400
#define NVC0_PGRAPH_GPC_BROADCAST_PROP__ESIZE                   0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP                     0x00418420
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_RT_PITCH_OVERRUN    0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_RT_WIDTH_OVERRUN    0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_RT_HEIGHT_OVERRUN   0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_ZETA_STORAGE_TYPE_MISMATCH  0x00000080
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_RT_STORAGE_TYPE_MISMATCH    0x00000100
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_RT_LINEAR_MISMATCH  0x00000400
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_CLEAR               0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_ENABLE              0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_5                   0x00418434
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_5_X__MASK           0x0000ffff
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_5_X__SHIFT          0
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_5_Y__MASK           0xffff0000
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_5_Y__SHIFT          16

#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_6                   0x00418438
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_6_FORMAT__MASK      0x00003f00
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_6_FORMAT__SHIFT     8

#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_7                   0x0041843c
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_7_STORAGE_TYPE__MASK        0x000000ff
#define NVC0_PGRAPH_GPC_BROADCAST_PROP_TRAP_7_STORAGE_TYPE__SHIFT       0

#define NVC0_PGRAPH_GPC_BROADCAST_UNK500                        0x00418500
#define NVC0_PGRAPH_GPC_BROADCAST_UNK500__ESIZE                 0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_UNK600                        0x00418600
#define NVC0_PGRAPH_GPC_BROADCAST_UNK600__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_UNK680                        0x00418680
#define NVC0_PGRAPH_GPC_BROADCAST_UNK680__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_UNK700                        0x00418700
#define NVC0_PGRAPH_GPC_BROADCAST_UNK700__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP                        0x00418800
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_HUB2ESETUP_ADDR        0x00418808
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_HUB2ESETUP_ADDR__SHR   8

#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_HUB2ESETUP_CONF        0x0041880c
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_HUB2ESETUP_CONF_UNK0__MASK     0x000007ff
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_HUB2ESETUP_CONF_UNK0__SHIFT    0
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_HUB2ESETUP_CONF_UNK31  0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_POLY2ESETUP            0x00418810
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_POLY2ESETUP_ADDRESS__MASK      0x0fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_POLY2ESETUP_ADDRESS__SHIFT     0
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_POLY2ESETUP_ADDRESS__SHR       12
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_POLY2ESETUP_UNK31      0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_TRAP                   0x00418824
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_TRAP_CLEAR             0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_ESETUP_TRAP_ENABLE            0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_FFB                           0x00418880
#define NVC0_PGRAPH_GPC_BROADCAST_FFB__ESIZE                    0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_FFB_PART_CONFIG               0x004188ac
#define NVC0_PGRAPH_GPC_BROADCAST_FFB_PART_CONFIG_PART_COUNT__MASK      0x0000000f
#define NVC0_PGRAPH_GPC_BROADCAST_FFB_PART_CONFIG_PART_COUNT__SHIFT     0
#define NVC0_PGRAPH_GPC_BROADCAST_FFB_PART_CONFIG_MEM_SPLIT_ENABLE      0x00000010

#define NVC0_PGRAPH_GPC_BROADCAST_FFB_UNK34_ADDR                0x004188b4
#define NVC0_PGRAPH_GPC_BROADCAST_FFB_UNK34_ADDR__SHR           8

#define NVC0_PGRAPH_GPC_BROADCAST_FFB_UNK38_ADDR                0x004188b8
#define NVC0_PGRAPH_GPC_BROADCAST_FFB_UNK38_ADDR__SHR           8

#define NVC0_PGRAPH_GPC_BROADCAST_ZCULL                         0x00418900
#define NVC0_PGRAPH_GPC_BROADCAST_ZCULL__ESIZE                  0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_ZCULL_TRAP                    0x00418900
#define NVC0_PGRAPH_GPC_BROADCAST_ZCULL_TRAP_CLEAR              0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_ZCULL_TRAP_ENABLE             0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_UNK980                        0x00418980
#define NVC0_PGRAPH_GPC_BROADCAST_UNK980__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_UNKA00                        0x00418a00
#define NVC0_PGRAPH_GPC_BROADCAST_UNKA00__ESIZE                 0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS                         0x00418b00
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS__ESIZE                  0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID(i0)           (0x00418b08 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID__ESIZE         0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID__LEN           0x0000002c
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_0__MASK        0x0000001f
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_0__SHIFT       0
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_1__MASK        0x000003e0
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_1__SHIFT       5
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_2__MASK        0x00007c00
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_2__SHIFT       10
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_3__MASK        0x000f8000
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_3__SHIFT       15
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_4__MASK        0x01f00000
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_4__SHIFT       20
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_5__MASK        0x3e000000
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TP_GPCID_5__SHIFT       25

#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TOTAL                   0x00418bb8
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TOTAL_ROPC_COUNT__MASK  0x000000ff
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TOTAL_ROPC_COUNT__SHIFT 0
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TOTAL_GPC_COUNT__MASK   0x0000ff00
#define NVC0_PGRAPH_GPC_BROADCAST_TPBUS_TOTAL_GPC_COUNT__SHIFT  8

#define NVC0_PGRAPH_GPC_BROADCAST_TPCONF                        0x00418c00
#define NVC0_PGRAPH_GPC_BROADCAST_TPCONF__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_TPCONF_TPCNT                  0x00418c08

#define NVC0_PGRAPH_GPC_BROADCAST_TPCONF_TPID(i0)              (0x00418c10 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TPCONF_TPID__ESIZE            0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TPCONF_TPID__LEN              0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_UNKC80                        0x00418c80
#define NVC0_PGRAPH_GPC_BROADCAST_UNKC80__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_UNKC80_TPCNT                  0x00418c8c

#define NVC0_PGRAPH_GPC_BROADCAST_UNKD00                        0x00418d00
#define NVC0_PGRAPH_GPC_BROADCAST_UNKD00__ESIZE                 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_UNKE00                        0x00418e00
#define NVC0_PGRAPH_GPC_BROADCAST_UNKE00__ESIZE                 0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_UNKF00                        0x00418f00
#define NVC0_PGRAPH_GPC_BROADCAST_UNKF00__ESIZE                 0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE                        0x00419000
#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE__ESIZE                 0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_HUB2GPC_ADDR           0x00419004
#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_HUB2GPC_ADDR__SHR      8

#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_HUB2GPC_CONF           0x00419008
#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_HUB2GPC_CONF_UNK0__MASK        0x000000ff
#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_HUB2GPC_CONF_UNK0__SHIFT       0

#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_TRAP                   0x00419028
#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_TRAP_CLEAR             0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_CCACHE_TRAP_ENABLE            0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST                  0x00419800
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST__ESIZE           0x00000800


#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY             0x00419800
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY__ESIZE      0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_POLY2ESETUP 0x00419848
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_POLY2ESETUP_ADDRESS__MASK   0x0fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_POLY2ESETUP_ADDRESS__SHIFT  0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_POLY2ESETUP_ADDRESS__SHR    12
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_POLY2ESETUP_UNK28   0x10000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_TRAP        0x00419884
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_TRAP_CLEAR  0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_TRAP_ENABLE 0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_POLY_TPID        0x00419888

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TEX              0x00419a00
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TEX__ESIZE       0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TEX_TRAP         0x00419a24
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TEX_TRAP_CLEAR   0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TEX_TRAP_ENABLE  0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS            0x00419b00
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS__ESIZE     0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID(i0)       (0x00419b00 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID__ESIZE    0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID__LEN      0x0000002c
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_0__MASK   0x0000001f
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_0__SHIFT  0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_1__MASK   0x000003e0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_1__SHIFT  5
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_2__MASK   0x00007c00
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_2__SHIFT  10
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_3__MASK   0x000f8000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_3__SHIFT  15
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_4__MASK   0x01f00000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_4__SHIFT  20
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_5__MASK   0x3e000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_TP_GPCID_5__SHIFT  25

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKD0      0x00419bd0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKD0_ROPC_COUNT__MASK     0x000000ff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKD0_ROPC_COUNT__SHIFT    0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKD0_GPC_COUNT__MASK      0x0000ff00
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKD0_GPC_COUNT__SHIFT     8
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKD0_UNK16__MASK  0x1fff0000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKD0_UNK16__SHIFT 16

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKE4      0x00419be4
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKE4_UNK0__MASK   0x3fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TPBUS_UNKE4_UNK0__SHIFT  0

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1               0x00419c80
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1__ESIZE        0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1_TRAP          0x00419c8c
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1_TRAP_GLOBAL_MAP_READ  0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1_TRAP_GLOBAL_MAP_WRITE 0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1_TRAP_CLEAR    0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1_TRAP_ENABLE   0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_L1_TPID          0x00419ce8

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP             0x00419d08
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_TEX         0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_MP          0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_POLY        0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_L1C         0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_EN          0x00419d0c
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_EN_TEX      0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_EN_MP       0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_EN_POLY     0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_TRAP_EN_L1C      0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP               0x00419e00
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP__ESIZE        0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_UNK44_TRAP    0x00419e44

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_UNK4C_TRAP    0x00419e4c

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_TRAP_HANDLER_PC       0x00419e58

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_OP(i0)    (0x00419e60 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_OP__ESIZE  0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_OP__LEN    0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_OP_0__MASK 0x0000ffff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_OP_0__SHIFT        0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_OP_1__MASK 0xffff0000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_OP_1__SHIFT        16

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW   0x00419e70
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_0 0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_1 0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_2 0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_3 0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_4 0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_5 0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_6 0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_7 0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER(i0)        (0x00419e74 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER__ESIZE     0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_PM_COUNTER__LEN       0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_TP_BROADCAST_MP_TPID          0x00419e98

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL                        0x0041a000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL__ESIZE                 0x00001000



#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER           0x0041a000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER_PERIODIC  0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER_WATCHDOG  0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER_FIFO_DATA 0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER_CHANNEL_SWITCH    0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER_EXIT      0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER_USER1     0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_TRIGGER_XFER_FAULT        0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK               0x0041a004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK_PERIODIC      0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK_WATCHDOG      0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK_FIFO_DATA     0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK_CHANNEL_SWITCH        0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK_EXIT          0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK_USER1         0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ACK_XFER_FAULT    0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR                   0x0041a008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_PERIODIC          0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_WATCHDOG          0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_FIFO_DATA         0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_CHANNEL_SWITCH    0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EXIT              0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_USER1             0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_XFER_FAULT        0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET            0x0041a010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET_PERIODIC   0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET_WATCHDOG   0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET_FIFO_DATA  0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET_CHANNEL_SWITCH     0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET_EXIT       0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET_USER1      0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_SET_XFER_FAULT 0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR            0x0041a014
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR_PERIODIC   0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR_WATCHDOG   0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR_FIFO_DATA  0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR_CHANNEL_SWITCH     0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR_EXIT       0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR_USER1      0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CLR_XFER_FAULT 0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN                0x0041a018
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_PERIODIC       0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_WATCHDOG       0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_FIFO_DATA      0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_CHANNEL_SWITCH 0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_EXIT           0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_USER1          0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_EN_XFER_FAULT     0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING           0x0041a01c
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1__MASK  0x0000ffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1__SHIFT 0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1_PERIODIC       0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1_WATCHDOG       0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1_FIFO_DATA      0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1_CHANNEL_SWITCH 0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1_EXIT   0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1_USER1  0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M1_XFER_FAULT     0x00000200
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2__MASK  0xffff0000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2__SHIFT 16
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2_PERIODIC       0x00010000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2_WATCHDOG       0x00020000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2_FIFO_DATA      0x00040000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2_CHANNEL_SWITCH 0x00080000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2_EXIT   0x00100000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2_USER1  0x00400000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTING_M2_XFER_FAULT     0x02000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_PERIODIC_PERIOD        0x0041a020

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_PERIODIC_TIME          0x0041a024

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_PERIODIC_ENABLE        0x0041a028

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TIME_LOW               0x0041a02c

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TIME_HIGH              0x0041a030

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_WATCHDOG_TIME          0x0041a034

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_WATCHDOG_ENABLE        0x0041a038

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_SCRATCH(i0)           (0x0041a040 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_SCRATCH__ESIZE         0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_SCRATCH__LEN           0x00000002

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_ACCESS_EN              0x0041a048
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_ACCESS_EN_CHANNEL_SWITCH       0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_ACCESS_EN_FIFO         0x00000002

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR            0x0041a050
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN__MASK 0x3fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN__SHIFT        0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__MASK 0x0fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__SHIFT        0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__SHR  12
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_TARGET__MASK  0x30000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_TARGET__SHIFT 28
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_TARGET_VRAM   0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_TARGET_SYSRAM 0x20000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_CHAN_TARGET_SYSRAM_NO_SNOOP        0x30000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_CUR_VALID      0x40000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT           0x0041a054
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN__MASK        0x3fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN__SHIFT       0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__MASK        0x0fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__SHIFT       0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__SHR 12
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_TARGET__MASK 0x30000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_TARGET__SHIFT        28
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_VRAM  0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_SYSRAM        0x20000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_SYSRAM_NO_SNOOP       0x30000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_NEXT_VALID     0x40000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_TRIGGER        0x0041a054
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_TRIGGER_UNLOAD 0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CHANNEL_TRIGGER_LOAD   0x00000002

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_DATA              0x0041a064

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_CMD               0x0041a068
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_CMD_MTHD__MASK    0x000007ff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_CMD_MTHD__SHIFT   0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_CMD_MTHD__SHR     2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_CMD_SUBC__MASK    0x00003800
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_CMD_SUBC__SHIFT   11
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_CMD_NONINCR       0x00004000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_OCCUPIED          0x0041a070

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_ACK               0x0041a074

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_FIFO_LIMIT             0x0041a078

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MISC_TRIGGER           0x0041a088
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MISC_TRIGGER_WRCACHE_FLUSH     0x00010000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MISC_TRIGGER_PM_TRIGGER        0x00020000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_CTRL                0x0041a100
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_CTRL_START_TRIGGER  0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_CTRL_RESET_UNK2_TRIGGER     0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_CTRL_RESET_UNK3_TRIGGER     0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_CTRL_STOPPED        0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_CTRL_SLEEPING       0x00000020

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_ENTRY                  0x0041a104

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS                   0x0041a108
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS_CODE_SIZE__MASK   0x000001ff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS_CODE_SIZE__SHIFT  0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS_CODE_SIZE__SHR    8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS_DATA_SIZE__MASK   0x0001fe00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS_DATA_SIZE__SHIFT  9
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS_DATA_SIZE__SHR    8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_EXT_BASE          0x0041a110
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_EXT_BASE__SHR     8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_FUC_ADDR          0x0041a114

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL              0x0041a118
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_FULL         0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SEG__MASK    0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SEG__SHIFT   4
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SEG_DATA     0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SEG_CODE     0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_DIR__MASK    0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_DIR__SHIFT   5
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_DIR_LOAD     0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_DIR_STORE    0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SIZE__MASK   0x00000700
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SIZE__SHIFT  8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SIZE_16      0x00000200
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SIZE_32      0x00000300
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SIZE_64      0x00000400
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SIZE_128     0x00000500
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_SIZE_256     0x00000600
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_TARGET__MASK 0x00007000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_CTRL_TARGET__SHIFT        12

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_EXT_ADDR          0x0041a11c

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS            0x0041a120
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS_PENDING    0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS_UNK4__MASK 0x00000030
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS_UNK4__SHIFT        4
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS_STORES_PENDING__MASK       0x00070000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS_STORES_PENDING__SHIFT      16
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS_LOADS_PENDING__MASK        0x07000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_XFER_STATUS_LOADS_PENDING__SHIFT       24

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_STATUS              0x0041a128
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_STATUS_XCLD_IDLE    0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_STATUS_CRYPT_IDLE   0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_STATUS_TRAP_ACTIVE  0x00000100
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_STATUS_XDST_IDLE    0x00040000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UC_STATUS_XDLD_IDLE    0x00080000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2                  0x0041a12c
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_UNK0__MASK       0x0000000f
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_UNK0__SHIFT      0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_SECRETFUL__MASK  0x000000f0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_SECRETFUL__SHIFT 4
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_CODE_PORTS__MASK 0x00000f00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_CODE_PORTS__SHIFT        8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_DATA_PORTS__MASK 0x0000f000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_DATA_PORTS__SHIFT        12
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_VM_PAGES_LOG2__MASK      0x000f0000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CAPS2_VM_PAGES_LOG2__SHIFT     16

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD                0x0041a140
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_PARAM__MASK    0x00ffffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_PARAM__SHIFT   0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_CMD__MASK      0x03000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_CMD__SHIFT     24
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_CMD_ITLB       0x01000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_CMD_PTLB       0x02000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_CMD_VTLB       0x03000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TLB_CMD_RES            0x0041a144

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX             0x0041a180
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_PHYS_ADDR__MASK     0x0000fffc
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_PHYS_ADDR__SHIFT    2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_PHYS_ADDR__SHR      2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_WRITE_AUTOINCR      0x01000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_READ_AUTOINCR       0x02000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_SECRET      0x10000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_SECRET_LOCKDOWN     0x20000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_SECRET_FAIL 0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_INDEX_SECRET_SCRUBBER_ACTIVE      0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE                   0x0041a184

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_VIRT_ADDR         0x0041a188
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CODE_VIRT_ADDR__SHR    8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX(i0)        (0x0041a1c0 + 0x8*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX__ESIZE      0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX__LEN        0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX_ADDR__MASK  0x0000fffc
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX_ADDR__SHIFT 2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX_ADDR__SHR   2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX_WRITE_AUTOINCR      0x01000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA_INDEX_READ_AUTOINCR       0x02000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA(i0)              (0x0041a1c4 + 0x8*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA__ESIZE            0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DATA__LEN              0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_PC                     0x0041aff0

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD                 0x0041aff4

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR            0x0041aff8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_ADDR__MASK 0x0000fffc
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_ADDR__SHIFT        2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_ADDR__SHR  2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_SEG__MASK  0x00100000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_SEG__SHIFT 20
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_SEG_DATA   0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_SEG_CODE   0x00100000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_READBACK   0x00200000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_XFER_BUSY  0x01000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_SECRET     0x10000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UPLOAD_ADDR_CODE_BUSY  0x20000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_HOST_IO_INDEX          0x0041affc

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE                   0x0041a400
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_STRAND            0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_MMCTX             0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_MMIO_RD           0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_MMIO_WRS          0x00000080
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_BAR               0x00000100
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_CC_WATCHDOG       0x00000800
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_UNK12             0x00001000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_DONE_UNK13             0x00002000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE             0x0041a404
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0__MASK  0x0000003f
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0__SHIFT 0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_GPC_UNK2       0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_HUB_CHANNEL_SWITCH     0x00000003
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_HUB_UNK4       0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_HUB_CTXCTL_DOWN        0x0000000b
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_HUB_UNK12      0x0000000c
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_ZERO   0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_STRAND 0x00000022
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_MMCTX  0x00000025
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_MMIO_RD        0x00000026
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_MMIO_WRS       0x00000027
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_BAR    0x00000028
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_CC_WATCHDOG    0x0000002b
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_UNK12  0x0000002c
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC0_UNK13  0x0000002d
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1__MASK  0x00003f00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1__SHIFT 8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_GPC_UNK2       0x00000200
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_HUB_CHANNEL_SWITCH     0x00000300
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_HUB_UNK4       0x00000400
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_HUB_CTXCTL_DOWN        0x00000b00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_HUB_UNK12      0x00000c00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_ZERO   0x00002000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_STRAND 0x00002200
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_MMCTX  0x00002500
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_MMIO_RD        0x00002600
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_MMIO_WRS       0x00002700
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_BAR    0x00002800
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_CC_WATCHDOG    0x00002b00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_UNK12  0x00002c00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_SRC1_UNK13  0x00002d00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_FUN__MASK   0x00010000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_FUN__SHIFT  16
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_FUN_OR      0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_FUN_AND     0x00010000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_NOT         0x00020000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_INTR_ROUTE_LEVEL       0x00040000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_BAR_REQMASK(i0)       (0x0041a40c + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_BAR_REQMASK__ESIZE     0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_BAR_REQMASK__LEN       0x00000002

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_BAR                    0x0041a414

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_BAR_SET                0x0041a418

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_WATCHDOG            0x0041a430
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_WATCHDOG_TIME_REMAINING__MASK       0x3fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_WATCHDOG_TIME_REMAINING__SHIFT      0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_WATCHDOG_ENABLE     0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_WRCMD_DATA             0x0041a500

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_WRCMD_CMD              0x0041a504

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_NEW_CAPS               0x0041a620
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_NEW_CAPS_CODE_SIZE__MASK       0x000000ff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_NEW_CAPS_CODE_SIZE__SHIFT      0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_NEW_CAPS_CODE_SIZE__SHR        8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_NEW_CAPS_DATA_SIZE__MASK       0x0000ff00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_NEW_CAPS_DATA_SIZE__SHIFT      8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_NEW_CAPS_DATA_SIZE__SHR        8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_SAVE_SWBASE      0x0041a700
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_SAVE_SWBASE__SHR 8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_LOAD_SWBASE      0x0041a704
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_LOAD_SWBASE__SHR 8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_BASE             0x0041a710

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL             0x0041a714
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_QFREE__MASK 0x0000001f
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_QFREE__SHIFT        0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_QLIMIT__MASK        0x00001f00
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_QLIMIT__SHIFT       8
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_DIR__MASK   0x00010000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_DIR__SHIFT  16
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_DIR_SAVE    0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_DIR_LOAD    0x00010000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_START_TRIGGER       0x00020000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_CTRL_STOP_TRIGGER        0x00040000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_MULTI_STRIDE     0x0041a718

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_MULTI_MASK       0x0041a71c

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE            0x0041a720
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE_BASE_EN    0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE_MULTI_EN   0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE_ADDR__MASK 0x03fffffc
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE_ADDR__SHIFT        2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE_ADDR__SHR  2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE_CNTM1__MASK        0xfc000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_QUEUE_CNTM1__SHIFT       26

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL              0x0041a728
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_UNK0         0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_ADDR__MASK   0x03fffffc
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_ADDR__SHIFT  2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_ADDR__SHR    2
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_WRS          0x20000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_ACCESS__MASK 0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_ACCESS__SHIFT        30
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_ACCESS_READ  0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_ACCESS_WRITE 0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_CTRL_TRIGGER      0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_RDVAL             0x0041a72c

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMIO_WRVAL             0x0041a730

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MMCTX_LOAD_COUNT       0x0041a74c

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH(i0)        (0x0041a800 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH__ESIZE      0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH__LEN        0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH_SET(i0)    (0x0041a820 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH_SET__ESIZE  0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH_SET__LEN    0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH_CLEAR(i0)  (0x0041a840 + 0x4*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH_CLEAR__ESIZE        0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_CC_SCRATCH_CLEAR__LEN  0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRANDS                0x0041a880

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_SAVE_SWBASE     0x0041a908
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_SAVE_SWBASE__SHR        8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_LOAD_SWBASE     0x0041a90c
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_LOAD_SWBASE__SHR        8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_SIZE            0x0041a910

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_GENE_CNT        0x0041a918

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_FIRST_GENE      0x0041a91c

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD             0x0041a928
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_LATCH_FIRST_GENE    0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_LATCH_GENE_CNT      0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_SAVE        0x00000003
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_LOAD        0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_UNK5        0x00000005
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_UNKA        0x0000000a
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_UNKB        0x0000000b
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_UNKC        0x0000000c
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_STRAND_CMD_UNKD        0x0000000d

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_BASE               0x0041aa04
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_BASE__SHR          8

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN               0x0041aa0c
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_ADDRESS__MASK 0x0fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_ADDRESS__SHIFT        0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_ADDRESS__SHR  12
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_TARGET__MASK  0x30000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_TARGET__SHIFT 28
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_TARGET_VRAM   0x00000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_TARGET_SYSRAM 0x20000000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CHAN_TARGET_SYSRAM_NO_SNOOP        0x30000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CMD                0x0041aa10
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_CMD_LOAD_CHAN      0x00000007

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET             0x0041aa20
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET_TARGET__MASK        0x0000001f
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET_TARGET__SHIFT       0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET_TARGET_VM   0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET_TARGET_VRAM 0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET_TARGET_SYSRAM_NOSNOOP       0x00000003
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET_TARGET_SYSRAM       0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MEM_TARGET_UNK31       0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UNITS                  0x0041a608
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UNITS_TP_COUNT__MASK   0x0000001f
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UNITS_TP_COUNT__SHIFT  0
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UNITS_UNK_ZCULL_COUNT__MASK    0x001f0000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_UNITS_UNK_ZCULL_COUNT__SHIFT   16

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_RED_SWITCH             0x0041a614
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_RED_SWITCH_UNK0_GPC    0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_RED_SWITCH_POWER_GPC   0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_RED_SWITCH_ENABLE_GPC  0x00000200
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_RED_SWITCH_UNK11       0x00000800

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_MYINDEX                0x0041a618

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP                   0x0041ac90
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_PROP              0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_ZCULL             0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_CCACHE            0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_ESETUP            0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_TP__MASK          0x00ff0000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_TP__SHIFT         16

#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_EN                0x0041ac94
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_EN_PROP           0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_EN_ZCULL          0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_EN_CCACHE         0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_EN_ESETUP         0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_EN_TP__MASK       0x00ff0000
#define NVC0_PGRAPH_GPC_BROADCAST_CTXCTL_TRAP_EN_TP__SHIFT      16

#define NVC0_PGRAPH_GPC_BROADCAST_TP(i0)                       (0x0041c000 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP__ESIZE                     0x00000800
#define NVC0_PGRAPH_GPC_BROADCAST_TP__LEN                       0x00000004


#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY(i0)                  (0x0041c000 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY__ESIZE                0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_POLY2ESETUP(i0)      (0x0041c048 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_POLY2ESETUP_ADDRESS__MASK     0x0fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_POLY2ESETUP_ADDRESS__SHIFT    0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_POLY2ESETUP_ADDRESS__SHR      12
#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_POLY2ESETUP_UNK28     0x10000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_TRAP(i0)             (0x0041c084 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_TRAP_CLEAR            0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_TRAP_ENABLE           0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_POLY_TPID(i0)             (0x0041c088 + 0x800*(i0))

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TEX(i0)                   (0x0041c200 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TEX__ESIZE                 0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TEX_TRAP(i0)              (0x0041c224 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TEX_TRAP_CLEAR             0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TEX_TRAP_ENABLE            0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS(i0)                 (0x0041c300 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS__ESIZE               0x00000100

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID(i0, i1)    (0x0041c300 + 0x800*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID__ESIZE      0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID__LEN        0x0000002c
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_0__MASK     0x0000001f
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_0__SHIFT    0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_1__MASK     0x000003e0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_1__SHIFT    5
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_2__MASK     0x00007c00
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_2__SHIFT    10
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_3__MASK     0x000f8000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_3__SHIFT    15
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_4__MASK     0x01f00000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_4__SHIFT    20
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_5__MASK     0x3e000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_TP_GPCID_5__SHIFT    25

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKD0(i0)           (0x0041c3d0 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKD0_ROPC_COUNT__MASK       0x000000ff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKD0_ROPC_COUNT__SHIFT      0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKD0_GPC_COUNT__MASK        0x0000ff00
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKD0_GPC_COUNT__SHIFT       8
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKD0_UNK16__MASK    0x1fff0000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKD0_UNK16__SHIFT   16

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKE4(i0)           (0x0041c3e4 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKE4_UNK0__MASK     0x3fffffff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TPBUS_UNKE4_UNK0__SHIFT    0

#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1(i0)                    (0x0041c480 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1__ESIZE                  0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1_TRAP(i0)               (0x0041c48c + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1_TRAP_GLOBAL_MAP_READ    0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1_TRAP_GLOBAL_MAP_WRITE   0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1_TRAP_CLEAR              0x40000000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1_TRAP_ENABLE             0x80000000

#define NVC0_PGRAPH_GPC_BROADCAST_TP_L1_TPID(i0)               (0x0041c4e8 + 0x800*(i0))

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP(i0)                  (0x0041c508 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_TEX                   0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_MP                    0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_POLY                  0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_L1C                   0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_EN(i0)               (0x0041c50c + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_EN_TEX                0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_EN_MP                 0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_EN_POLY               0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_TRAP_EN_L1C                0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP(i0)                    (0x0041c600 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP__ESIZE                  0x00000200

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_UNK44_TRAP(i0)         (0x0041c644 + 0x800*(i0))

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_UNK4C_TRAP(i0)         (0x0041c64c + 0x800*(i0))

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_TRAP_HANDLER_PC(i0)    (0x0041c658 + 0x800*(i0))

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_OP(i0, i1)          (0x0041c660 + 0x800*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_OP__ESIZE            0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_OP__LEN              0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_OP_0__MASK           0x0000ffff
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_OP_0__SHIFT          0
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_OP_1__MASK           0xffff0000
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_OP_1__SHIFT          16

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW(i0) (0x0041c670 + 0x800*(i0))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_0   0x00000001
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_1   0x00000002
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_2   0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_3   0x00000008
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_4   0x00000010
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_5   0x00000020
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_6   0x00000040
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER_OVERFLOW_7   0x00000080

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER(i0, i1)     (0x0041c674 + 0x800*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER__ESIZE       0x00000004
#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_PM_COUNTER__LEN         0x00000008

#define NVC0_PGRAPH_GPC_BROADCAST_TP_MP_TPID(i0)               (0x0041c698 + 0x800*(i0))

#define NVC0_PGRAPH_GPC(i0)                                    (0x00500000 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC__ESIZE                                  0x00008000
#define NVC0_PGRAPH_GPC__LEN                                    0x00000004


#define NVC0_PGRAPH_GPC_UNK380(i0)                             (0x00500380 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNK380__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_PROP(i0)                               (0x00500400 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_PROP__ESIZE                             0x00000100

#define NVC0_PGRAPH_GPC_PROP_TRAP(i0)                          (0x00500420 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_PROP_TRAP_RT_PITCH_OVERRUN              0x00000002
#define NVC0_PGRAPH_GPC_PROP_TRAP_RT_WIDTH_OVERRUN              0x00000010
#define NVC0_PGRAPH_GPC_PROP_TRAP_RT_HEIGHT_OVERRUN             0x00000020
#define NVC0_PGRAPH_GPC_PROP_TRAP_ZETA_STORAGE_TYPE_MISMATCH    0x00000080
#define NVC0_PGRAPH_GPC_PROP_TRAP_RT_STORAGE_TYPE_MISMATCH      0x00000100
#define NVC0_PGRAPH_GPC_PROP_TRAP_RT_LINEAR_MISMATCH            0x00000400
#define NVC0_PGRAPH_GPC_PROP_TRAP_CLEAR                         0x40000000
#define NVC0_PGRAPH_GPC_PROP_TRAP_ENABLE                        0x80000000

#define NVC0_PGRAPH_GPC_PROP_TRAP_5(i0)                        (0x00500434 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_PROP_TRAP_5_X__MASK                     0x0000ffff
#define NVC0_PGRAPH_GPC_PROP_TRAP_5_X__SHIFT                    0
#define NVC0_PGRAPH_GPC_PROP_TRAP_5_Y__MASK                     0xffff0000
#define NVC0_PGRAPH_GPC_PROP_TRAP_5_Y__SHIFT                    16

#define NVC0_PGRAPH_GPC_PROP_TRAP_6(i0)                        (0x00500438 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_PROP_TRAP_6_FORMAT__MASK                0x00003f00
#define NVC0_PGRAPH_GPC_PROP_TRAP_6_FORMAT__SHIFT               8

#define NVC0_PGRAPH_GPC_PROP_TRAP_7(i0)                        (0x0050043c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_PROP_TRAP_7_STORAGE_TYPE__MASK          0x000000ff
#define NVC0_PGRAPH_GPC_PROP_TRAP_7_STORAGE_TYPE__SHIFT         0

#define NVC0_PGRAPH_GPC_UNK500(i0)                             (0x00500500 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNK500__ESIZE                           0x00000100

#define NVC0_PGRAPH_GPC_UNK600(i0)                             (0x00500600 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNK600__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_UNK680(i0)                             (0x00500680 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNK680__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_UNK700(i0)                             (0x00500700 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNK700__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_ESETUP(i0)                             (0x00500800 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_ESETUP__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_ESETUP_HUB2ESETUP_ADDR(i0)             (0x00500808 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_ESETUP_HUB2ESETUP_ADDR__SHR             8

#define NVC0_PGRAPH_GPC_ESETUP_HUB2ESETUP_CONF(i0)             (0x0050080c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_ESETUP_HUB2ESETUP_CONF_UNK0__MASK       0x000007ff
#define NVC0_PGRAPH_GPC_ESETUP_HUB2ESETUP_CONF_UNK0__SHIFT      0
#define NVC0_PGRAPH_GPC_ESETUP_HUB2ESETUP_CONF_UNK31            0x80000000

#define NVC0_PGRAPH_GPC_ESETUP_POLY2ESETUP(i0)                 (0x00500810 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_ESETUP_POLY2ESETUP_ADDRESS__MASK        0x0fffffff
#define NVC0_PGRAPH_GPC_ESETUP_POLY2ESETUP_ADDRESS__SHIFT       0
#define NVC0_PGRAPH_GPC_ESETUP_POLY2ESETUP_ADDRESS__SHR         12
#define NVC0_PGRAPH_GPC_ESETUP_POLY2ESETUP_UNK31                0x80000000

#define NVC0_PGRAPH_GPC_ESETUP_TRAP(i0)                        (0x00500824 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_ESETUP_TRAP_CLEAR                       0x40000000
#define NVC0_PGRAPH_GPC_ESETUP_TRAP_ENABLE                      0x80000000

#define NVC0_PGRAPH_GPC_FFB(i0)                                (0x00500880 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_FFB__ESIZE                              0x00000080

#define NVC0_PGRAPH_GPC_FFB_PART_CONFIG(i0)                    (0x005008ac + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_FFB_PART_CONFIG_PART_COUNT__MASK        0x0000000f
#define NVC0_PGRAPH_GPC_FFB_PART_CONFIG_PART_COUNT__SHIFT       0
#define NVC0_PGRAPH_GPC_FFB_PART_CONFIG_MEM_SPLIT_ENABLE        0x00000010

#define NVC0_PGRAPH_GPC_FFB_UNK34_ADDR(i0)                     (0x005008b4 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_FFB_UNK34_ADDR__SHR                     8

#define NVC0_PGRAPH_GPC_FFB_UNK38_ADDR(i0)                     (0x005008b8 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_FFB_UNK38_ADDR__SHR                     8

#define NVC0_PGRAPH_GPC_ZCULL(i0)                              (0x00500900 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_ZCULL__ESIZE                            0x00000080

#define NVC0_PGRAPH_GPC_ZCULL_TRAP(i0)                         (0x00500900 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_ZCULL_TRAP_CLEAR                        0x40000000
#define NVC0_PGRAPH_GPC_ZCULL_TRAP_ENABLE                       0x80000000

#define NVC0_PGRAPH_GPC_UNK980(i0)                             (0x00500980 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNK980__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_UNKA00(i0)                             (0x00500a00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNKA00__ESIZE                           0x00000100

#define NVC0_PGRAPH_GPC_TPBUS(i0)                              (0x00500b00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TPBUS__ESIZE                            0x00000100

#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID(i0, i1)                 (0x00500b08 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID__ESIZE                   0x00000004
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID__LEN                     0x0000002c
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_0__MASK                  0x0000001f
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_0__SHIFT                 0
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_1__MASK                  0x000003e0
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_1__SHIFT                 5
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_2__MASK                  0x00007c00
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_2__SHIFT                 10
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_3__MASK                  0x000f8000
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_3__SHIFT                 15
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_4__MASK                  0x01f00000
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_4__SHIFT                 20
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_5__MASK                  0x3e000000
#define NVC0_PGRAPH_GPC_TPBUS_TP_GPCID_5__SHIFT                 25

#define NVC0_PGRAPH_GPC_TPBUS_TOTAL(i0)                        (0x00500bb8 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TPBUS_TOTAL_ROPC_COUNT__MASK            0x000000ff
#define NVC0_PGRAPH_GPC_TPBUS_TOTAL_ROPC_COUNT__SHIFT           0
#define NVC0_PGRAPH_GPC_TPBUS_TOTAL_GPC_COUNT__MASK             0x0000ff00
#define NVC0_PGRAPH_GPC_TPBUS_TOTAL_GPC_COUNT__SHIFT            8

#define NVC0_PGRAPH_GPC_TPCONF(i0)                             (0x00500c00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TPCONF__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_TPCONF_TPCNT(i0)                       (0x00500c08 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_TPCONF_TPID(i0, i1)                    (0x00500c10 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_TPCONF_TPID__ESIZE                      0x00000004
#define NVC0_PGRAPH_GPC_TPCONF_TPID__LEN                        0x00000008

#define NVC0_PGRAPH_GPC_UNKC80(i0)                             (0x00500c80 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNKC80__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_UNKC80_TPCNT(i0)                       (0x00500c8c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_UNKD00(i0)                             (0x00500d00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNKD00__ESIZE                           0x00000080

#define NVC0_PGRAPH_GPC_UNKE00(i0)                             (0x00500e00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNKE00__ESIZE                           0x00000100

#define NVC0_PGRAPH_GPC_UNKF00(i0)                             (0x00500f00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_UNKF00__ESIZE                           0x00000100

#define NVC0_PGRAPH_GPC_CCACHE(i0)                             (0x00501000 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CCACHE__ESIZE                           0x00000100

#define NVC0_PGRAPH_GPC_CCACHE_HUB2GPC_ADDR(i0)                (0x00501004 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CCACHE_HUB2GPC_ADDR__SHR                8

#define NVC0_PGRAPH_GPC_CCACHE_HUB2GPC_CONF(i0)                (0x00501008 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CCACHE_HUB2GPC_CONF_UNK0__MASK          0x000000ff
#define NVC0_PGRAPH_GPC_CCACHE_HUB2GPC_CONF_UNK0__SHIFT         0

#define NVC0_PGRAPH_GPC_CCACHE_TRAP(i0)                        (0x00501028 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CCACHE_TRAP_CLEAR                       0x40000000
#define NVC0_PGRAPH_GPC_CCACHE_TRAP_ENABLE                      0x80000000

#define NVC0_PGRAPH_GPC_TP_BROADCAST(i0)                       (0x00501800 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST__ESIZE                     0x00000800


#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY(i0)                  (0x00501800 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY__ESIZE                0x00000200

#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_POLY2ESETUP(i0)      (0x00501848 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_POLY2ESETUP_ADDRESS__MASK     0x0fffffff
#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_POLY2ESETUP_ADDRESS__SHIFT    0
#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_POLY2ESETUP_ADDRESS__SHR      12
#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_POLY2ESETUP_UNK28     0x10000000

#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_TRAP(i0)             (0x00501884 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_TRAP_CLEAR            0x40000000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_TRAP_ENABLE           0x80000000

#define NVC0_PGRAPH_GPC_TP_BROADCAST_POLY_TPID(i0)             (0x00501888 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TEX(i0)                   (0x00501a00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TEX__ESIZE                 0x00000100

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TEX_TRAP(i0)              (0x00501a24 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TEX_TRAP_CLEAR             0x40000000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TEX_TRAP_ENABLE            0x80000000

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS(i0)                 (0x00501b00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS__ESIZE               0x00000100

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID(i0, i1)    (0x00501b00 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID__ESIZE      0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID__LEN        0x0000002c
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_0__MASK     0x0000001f
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_0__SHIFT    0
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_1__MASK     0x000003e0
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_1__SHIFT    5
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_2__MASK     0x00007c00
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_2__SHIFT    10
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_3__MASK     0x000f8000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_3__SHIFT    15
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_4__MASK     0x01f00000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_4__SHIFT    20
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_5__MASK     0x3e000000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_TP_GPCID_5__SHIFT    25

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKD0(i0)           (0x00501bd0 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKD0_ROPC_COUNT__MASK       0x000000ff
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKD0_ROPC_COUNT__SHIFT      0
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKD0_GPC_COUNT__MASK        0x0000ff00
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKD0_GPC_COUNT__SHIFT       8
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKD0_UNK16__MASK    0x1fff0000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKD0_UNK16__SHIFT   16

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKE4(i0)           (0x00501be4 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKE4_UNK0__MASK     0x3fffffff
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TPBUS_UNKE4_UNK0__SHIFT    0

#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1(i0)                    (0x00501c80 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1__ESIZE                  0x00000080

#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1_TRAP(i0)               (0x00501c8c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1_TRAP_GLOBAL_MAP_READ    0x00000002
#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1_TRAP_GLOBAL_MAP_WRITE   0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1_TRAP_CLEAR              0x40000000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1_TRAP_ENABLE             0x80000000

#define NVC0_PGRAPH_GPC_TP_BROADCAST_L1_TPID(i0)               (0x00501ce8 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP(i0)                  (0x00501d08 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_TEX                   0x00000001
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_MP                    0x00000002
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_POLY                  0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_L1C                   0x00000008

#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_EN(i0)               (0x00501d0c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_EN_TEX                0x00000001
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_EN_MP                 0x00000002
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_EN_POLY               0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_TRAP_EN_L1C                0x00000008

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP(i0)                    (0x00501e00 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP__ESIZE                  0x00000200

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_UNK44_TRAP(i0)         (0x00501e44 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_UNK4C_TRAP(i0)         (0x00501e4c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_TRAP_HANDLER_PC(i0)    (0x00501e58 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_OP(i0, i1)          (0x00501e60 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_OP__ESIZE            0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_OP__LEN              0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_OP_0__MASK           0x0000ffff
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_OP_0__SHIFT          0
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_OP_1__MASK           0xffff0000
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_OP_1__SHIFT          16

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW(i0) (0x00501e70 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_0   0x00000001
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_1   0x00000002
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_2   0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_3   0x00000008
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_4   0x00000010
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_5   0x00000020
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_6   0x00000040
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER_OVERFLOW_7   0x00000080

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER(i0, i1)     (0x00501e74 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER__ESIZE       0x00000004
#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_PM_COUNTER__LEN         0x00000008

#define NVC0_PGRAPH_GPC_TP_BROADCAST_MP_TPID(i0)               (0x00501e98 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL(i0)                             (0x00502000 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL__ESIZE                           0x00001000



#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER(i0)                (0x00502000 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER_PERIODIC            0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER_WATCHDOG            0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER_FIFO_DATA           0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER_CHANNEL_SWITCH      0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER_EXIT                0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER_USER1               0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_TRIGGER_XFER_FAULT          0x00000200

#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK(i0)                    (0x00502004 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK_PERIODIC                0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK_WATCHDOG                0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK_FIFO_DATA               0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK_CHANNEL_SWITCH          0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK_EXIT                    0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK_USER1                   0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ACK_XFER_FAULT              0x00000200

#define NVC0_PGRAPH_GPC_CTXCTL_INTR(i0)                        (0x00502008 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_PERIODIC                    0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_WATCHDOG                    0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_FIFO_DATA                   0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_CHANNEL_SWITCH              0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EXIT                        0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_USER1                       0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_XFER_FAULT                  0x00000200

#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET(i0)                 (0x00502010 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET_PERIODIC             0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET_WATCHDOG             0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET_FIFO_DATA            0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET_CHANNEL_SWITCH       0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET_EXIT                 0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET_USER1                0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_SET_XFER_FAULT           0x00000200

#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR(i0)                 (0x00502014 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR_PERIODIC             0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR_WATCHDOG             0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR_FIFO_DATA            0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR_CHANNEL_SWITCH       0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR_EXIT                 0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR_USER1                0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CLR_XFER_FAULT           0x00000200

#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN(i0)                     (0x00502018 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_PERIODIC                 0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_WATCHDOG                 0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_FIFO_DATA                0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_CHANNEL_SWITCH           0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_EXIT                     0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_USER1                    0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_EN_XFER_FAULT               0x00000200

#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING(i0)                (0x0050201c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1__MASK            0x0000ffff
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1__SHIFT           0
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1_PERIODIC         0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1_WATCHDOG         0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1_FIFO_DATA        0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1_CHANNEL_SWITCH   0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1_EXIT             0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1_USER1            0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M1_XFER_FAULT       0x00000200
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2__MASK            0xffff0000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2__SHIFT           16
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2_PERIODIC         0x00010000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2_WATCHDOG         0x00020000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2_FIFO_DATA        0x00040000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2_CHANNEL_SWITCH   0x00080000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2_EXIT             0x00100000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2_USER1            0x00400000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTING_M2_XFER_FAULT       0x02000000

#define NVC0_PGRAPH_GPC_CTXCTL_PERIODIC_PERIOD(i0)             (0x00502020 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_PERIODIC_TIME(i0)               (0x00502024 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_PERIODIC_ENABLE(i0)             (0x00502028 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_TIME_LOW(i0)                    (0x0050202c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_TIME_HIGH(i0)                   (0x00502030 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_WATCHDOG_TIME(i0)               (0x00502034 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_WATCHDOG_ENABLE(i0)             (0x00502038 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_SCRATCH(i0, i1)                 (0x00502040 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_CTXCTL_SCRATCH__ESIZE                   0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_SCRATCH__LEN                     0x00000002

#define NVC0_PGRAPH_GPC_CTXCTL_ACCESS_EN(i0)                   (0x00502048 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_ACCESS_EN_CHANNEL_SWITCH         0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_ACCESS_EN_FIFO                   0x00000002

#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR(i0)                 (0x00502050 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN__MASK           0x3fffffff
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN__SHIFT          0
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__MASK   0x0fffffff
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__SHIFT  0
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_ADDRESS__SHR    12
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_TARGET__MASK    0x30000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_TARGET__SHIFT   28
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_TARGET_VRAM     0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_TARGET_SYSRAM   0x20000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_CHAN_TARGET_SYSRAM_NO_SNOOP  0x30000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_CUR_VALID                0x40000000

#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT(i0)                (0x00502054 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN__MASK          0x3fffffff
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN__SHIFT         0
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__MASK  0x0fffffff
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__SHIFT 0
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_ADDRESS__SHR   12
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_TARGET__MASK   0x30000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_TARGET__SHIFT  28
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_VRAM    0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_SYSRAM  0x20000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_CHAN_TARGET_SYSRAM_NO_SNOOP 0x30000000
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_NEXT_VALID               0x40000000

#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_TRIGGER(i0)             (0x00502054 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_TRIGGER_UNLOAD           0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_CHANNEL_TRIGGER_LOAD             0x00000002

#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_DATA(i0)                   (0x00502064 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_CMD(i0)                    (0x00502068 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_CMD_MTHD__MASK              0x000007ff
#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_CMD_MTHD__SHIFT             0
#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_CMD_MTHD__SHR               2
#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_CMD_SUBC__MASK              0x00003800
#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_CMD_SUBC__SHIFT             11
#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_CMD_NONINCR                 0x00004000

#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_OCCUPIED(i0)               (0x00502070 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_ACK(i0)                    (0x00502074 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_FIFO_LIMIT(i0)                  (0x00502078 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_MISC_TRIGGER(i0)                (0x00502088 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MISC_TRIGGER_WRCACHE_FLUSH       0x00010000
#define NVC0_PGRAPH_GPC_CTXCTL_MISC_TRIGGER_PM_TRIGGER          0x00020000

#define NVC0_PGRAPH_GPC_CTXCTL_UC_CTRL(i0)                     (0x00502100 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_UC_CTRL_START_TRIGGER            0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_UC_CTRL_RESET_UNK2_TRIGGER       0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_UC_CTRL_RESET_UNK3_TRIGGER       0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_UC_CTRL_STOPPED                  0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_UC_CTRL_SLEEPING                 0x00000020

#define NVC0_PGRAPH_GPC_CTXCTL_ENTRY(i0)                       (0x00502104 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_CAPS(i0)                        (0x00502108 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS_CODE_SIZE__MASK             0x000001ff
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS_CODE_SIZE__SHIFT            0
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS_CODE_SIZE__SHR              8
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS_DATA_SIZE__MASK             0x0001fe00
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS_DATA_SIZE__SHIFT            9
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS_DATA_SIZE__SHR              8

#define NVC0_PGRAPH_GPC_CTXCTL_XFER_EXT_BASE(i0)               (0x00502110 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_EXT_BASE__SHR               8

#define NVC0_PGRAPH_GPC_CTXCTL_XFER_FUC_ADDR(i0)               (0x00502114 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL(i0)                   (0x00502118 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_FULL                   0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SEG__MASK              0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SEG__SHIFT             4
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SEG_DATA               0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SEG_CODE               0x00000010
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_DIR__MASK              0x00000020
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_DIR__SHIFT             5
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_DIR_LOAD               0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_DIR_STORE              0x00000020
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SIZE__MASK             0x00000700
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SIZE__SHIFT            8
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SIZE_16                0x00000200
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SIZE_32                0x00000300
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SIZE_64                0x00000400
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SIZE_128               0x00000500
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_SIZE_256               0x00000600
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_TARGET__MASK           0x00007000
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_CTRL_TARGET__SHIFT          12

#define NVC0_PGRAPH_GPC_CTXCTL_XFER_EXT_ADDR(i0)               (0x0050211c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS(i0)                 (0x00502120 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS_PENDING              0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS_UNK4__MASK           0x00000030
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS_UNK4__SHIFT          4
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS_STORES_PENDING__MASK 0x00070000
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS_STORES_PENDING__SHIFT        16
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS_LOADS_PENDING__MASK  0x07000000
#define NVC0_PGRAPH_GPC_CTXCTL_XFER_STATUS_LOADS_PENDING__SHIFT 24

#define NVC0_PGRAPH_GPC_CTXCTL_UC_STATUS(i0)                   (0x00502128 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_UC_STATUS_XCLD_IDLE              0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_UC_STATUS_CRYPT_IDLE             0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_UC_STATUS_TRAP_ACTIVE            0x00000100
#define NVC0_PGRAPH_GPC_CTXCTL_UC_STATUS_XDST_IDLE              0x00040000
#define NVC0_PGRAPH_GPC_CTXCTL_UC_STATUS_XDLD_IDLE              0x00080000

#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2(i0)                       (0x0050212c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_UNK0__MASK                 0x0000000f
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_UNK0__SHIFT                0
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_SECRETFUL__MASK            0x000000f0
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_SECRETFUL__SHIFT           4
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_CODE_PORTS__MASK           0x00000f00
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_CODE_PORTS__SHIFT          8
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_DATA_PORTS__MASK           0x0000f000
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_DATA_PORTS__SHIFT          12
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_VM_PAGES_LOG2__MASK        0x000f0000
#define NVC0_PGRAPH_GPC_CTXCTL_CAPS2_VM_PAGES_LOG2__SHIFT       16

#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD(i0)                     (0x00502140 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_PARAM__MASK              0x00ffffff
#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_PARAM__SHIFT             0
#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_CMD__MASK                0x03000000
#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_CMD__SHIFT               24
#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_CMD_ITLB                 0x01000000
#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_CMD_PTLB                 0x02000000
#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_CMD_VTLB                 0x03000000

#define NVC0_PGRAPH_GPC_CTXCTL_TLB_CMD_RES(i0)                 (0x00502144 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX(i0)                  (0x00502180 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_PHYS_ADDR__MASK       0x0000fffc
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_PHYS_ADDR__SHIFT      2
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_PHYS_ADDR__SHR        2
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_WRITE_AUTOINCR        0x01000000
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_READ_AUTOINCR         0x02000000
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_SECRET                0x10000000
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_SECRET_LOCKDOWN       0x20000000
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_SECRET_FAIL           0x40000000
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_INDEX_SECRET_SCRUBBER_ACTIVE        0x80000000

#define NVC0_PGRAPH_GPC_CTXCTL_CODE(i0)                        (0x00502184 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_CODE_VIRT_ADDR(i0)              (0x00502188 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CODE_VIRT_ADDR__SHR              8

#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX(i0, i1)              (0x005021c0 + 0x8000*(i0) + 0x8*(i1))
#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX__ESIZE                0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX__LEN                  0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX_ADDR__MASK            0x0000fffc
#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX_ADDR__SHIFT           2
#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX_ADDR__SHR             2
#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX_WRITE_AUTOINCR        0x01000000
#define NVC0_PGRAPH_GPC_CTXCTL_DATA_INDEX_READ_AUTOINCR         0x02000000

#define NVC0_PGRAPH_GPC_CTXCTL_DATA(i0, i1)                    (0x005021c4 + 0x8000*(i0) + 0x8*(i1))
#define NVC0_PGRAPH_GPC_CTXCTL_DATA__ESIZE                      0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_DATA__LEN                        0x00000008

#define NVC0_PGRAPH_GPC_CTXCTL_PC(i0)                          (0x00502ff0 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD(i0)                      (0x00502ff4 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR(i0)                 (0x00502ff8 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_ADDR__MASK           0x0000fffc
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_ADDR__SHIFT          2
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_ADDR__SHR            2
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_SEG__MASK            0x00100000
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_SEG__SHIFT           20
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_SEG_DATA             0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_SEG_CODE             0x00100000
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_READBACK             0x00200000
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_XFER_BUSY            0x01000000
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_SECRET               0x10000000
#define NVC0_PGRAPH_GPC_CTXCTL_UPLOAD_ADDR_CODE_BUSY            0x20000000

#define NVC0_PGRAPH_GPC_CTXCTL_HOST_IO_INDEX(i0)               (0x00502ffc + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_DONE(i0)                        (0x00502400 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_STRAND                      0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_MMCTX                       0x00000020
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_MMIO_RD                     0x00000040
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_MMIO_WRS                    0x00000080
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_BAR                         0x00000100
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_CC_WATCHDOG                 0x00000800
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_UNK12                       0x00001000
#define NVC0_PGRAPH_GPC_CTXCTL_DONE_UNK13                       0x00002000

#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE(i0)                  (0x00502404 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0__MASK            0x0000003f
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0__SHIFT           0
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_GPC_UNK2         0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_HUB_CHANNEL_SWITCH       0x00000003
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_HUB_UNK4         0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_HUB_CTXCTL_DOWN  0x0000000b
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_HUB_UNK12        0x0000000c
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_ZERO             0x00000020
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_STRAND           0x00000022
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_MMCTX            0x00000025
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_MMIO_RD          0x00000026
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_MMIO_WRS         0x00000027
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_BAR              0x00000028
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_CC_WATCHDOG      0x0000002b
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_UNK12            0x0000002c
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC0_UNK13            0x0000002d
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1__MASK            0x00003f00
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1__SHIFT           8
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_GPC_UNK2         0x00000200
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_HUB_CHANNEL_SWITCH       0x00000300
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_HUB_UNK4         0x00000400
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_HUB_CTXCTL_DOWN  0x00000b00
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_HUB_UNK12        0x00000c00
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_ZERO             0x00002000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_STRAND           0x00002200
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_MMCTX            0x00002500
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_MMIO_RD          0x00002600
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_MMIO_WRS         0x00002700
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_BAR              0x00002800
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_CC_WATCHDOG      0x00002b00
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_UNK12            0x00002c00
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_SRC1_UNK13            0x00002d00
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_FUN__MASK             0x00010000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_FUN__SHIFT            16
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_FUN_OR                0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_FUN_AND               0x00010000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_NOT                   0x00020000
#define NVC0_PGRAPH_GPC_CTXCTL_INTR_ROUTE_LEVEL                 0x00040000

#define NVC0_PGRAPH_GPC_CTXCTL_BAR_REQMASK(i0, i1)             (0x0050240c + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_CTXCTL_BAR_REQMASK__ESIZE               0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_BAR_REQMASK__LEN                 0x00000002

#define NVC0_PGRAPH_GPC_CTXCTL_BAR(i0)                         (0x00502414 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_BAR_SET(i0)                     (0x00502418 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_CC_WATCHDOG(i0)                 (0x00502430 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_CC_WATCHDOG_TIME_REMAINING__MASK 0x3fffffff
#define NVC0_PGRAPH_GPC_CTXCTL_CC_WATCHDOG_TIME_REMAINING__SHIFT        0
#define NVC0_PGRAPH_GPC_CTXCTL_CC_WATCHDOG_ENABLE               0x80000000

#define NVC0_PGRAPH_GPC_CTXCTL_WRCMD_DATA(i0)                  (0x00502500 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_WRCMD_CMD(i0)                   (0x00502504 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_NEW_CAPS(i0)                    (0x00502620 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_NEW_CAPS_CODE_SIZE__MASK         0x000000ff
#define NVC0_PGRAPH_GPC_CTXCTL_NEW_CAPS_CODE_SIZE__SHIFT        0
#define NVC0_PGRAPH_GPC_CTXCTL_NEW_CAPS_CODE_SIZE__SHR          8
#define NVC0_PGRAPH_GPC_CTXCTL_NEW_CAPS_DATA_SIZE__MASK         0x0000ff00
#define NVC0_PGRAPH_GPC_CTXCTL_NEW_CAPS_DATA_SIZE__SHIFT        8
#define NVC0_PGRAPH_GPC_CTXCTL_NEW_CAPS_DATA_SIZE__SHR          8

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_SAVE_SWBASE(i0)           (0x00502700 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_SAVE_SWBASE__SHR           8

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_LOAD_SWBASE(i0)           (0x00502704 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_LOAD_SWBASE__SHR           8

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_BASE(i0)                  (0x00502710 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL(i0)                  (0x00502714 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_QFREE__MASK           0x0000001f
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_QFREE__SHIFT          0
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_QLIMIT__MASK          0x00001f00
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_QLIMIT__SHIFT         8
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_DIR__MASK             0x00010000
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_DIR__SHIFT            16
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_DIR_SAVE              0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_DIR_LOAD              0x00010000
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_START_TRIGGER         0x00020000
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_CTRL_STOP_TRIGGER          0x00040000

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_MULTI_STRIDE(i0)          (0x00502718 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_MULTI_MASK(i0)            (0x0050271c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE(i0)                 (0x00502720 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE_BASE_EN              0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE_MULTI_EN             0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE_ADDR__MASK           0x03fffffc
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE_ADDR__SHIFT          2
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE_ADDR__SHR            2
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE_CNTM1__MASK          0xfc000000
#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_QUEUE_CNTM1__SHIFT         26

#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL(i0)                   (0x00502728 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_UNK0                   0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_ADDR__MASK             0x03fffffc
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_ADDR__SHIFT            2
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_ADDR__SHR              2
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_WRS                    0x20000000
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_ACCESS__MASK           0x40000000
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_ACCESS__SHIFT          30
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_ACCESS_READ            0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_ACCESS_WRITE           0x40000000
#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_CTRL_TRIGGER                0x80000000

#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_RDVAL(i0)                  (0x0050272c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_MMIO_WRVAL(i0)                  (0x00502730 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_MMCTX_LOAD_COUNT(i0)            (0x0050274c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH(i0, i1)              (0x00502800 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH__ESIZE                0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH__LEN                  0x00000008

#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH_SET(i0, i1)          (0x00502820 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH_SET__ESIZE            0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH_SET__LEN              0x00000008

#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH_CLEAR(i0, i1)        (0x00502840 + 0x8000*(i0) + 0x4*(i1))
#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH_CLEAR__ESIZE          0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_CC_SCRATCH_CLEAR__LEN            0x00000008

#define NVC0_PGRAPH_GPC_CTXCTL_STRANDS(i0)                     (0x00502880 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_SAVE_SWBASE(i0)          (0x00502908 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_SAVE_SWBASE__SHR          8

#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_LOAD_SWBASE(i0)          (0x0050290c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_LOAD_SWBASE__SHR          8

#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_SIZE(i0)                 (0x00502910 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_GENE_CNT(i0)             (0x00502918 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_FIRST_GENE(i0)           (0x0050291c + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD(i0)                  (0x00502928 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_LATCH_FIRST_GENE      0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_LATCH_GENE_CNT        0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_SAVE                  0x00000003
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_LOAD                  0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_UNK5                  0x00000005
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_UNKA                  0x0000000a
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_UNKB                  0x0000000b
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_UNKC                  0x0000000c
#define NVC0_PGRAPH_GPC_CTXCTL_STRAND_CMD_UNKD                  0x0000000d

#define NVC0_PGRAPH_GPC_CTXCTL_MEM_BASE(i0)                    (0x00502a04 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_BASE__SHR                    8

#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN(i0)                    (0x00502a0c + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_ADDRESS__MASK           0x0fffffff
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_ADDRESS__SHIFT          0
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_ADDRESS__SHR            12
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_TARGET__MASK            0x30000000
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_TARGET__SHIFT           28
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_TARGET_VRAM             0x00000000
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_TARGET_SYSRAM           0x20000000
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CHAN_TARGET_SYSRAM_NO_SNOOP  0x30000000

#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CMD(i0)                     (0x00502a10 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_CMD_LOAD_CHAN                0x00000007

#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET(i0)                  (0x00502a20 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET_TARGET__MASK          0x0000001f
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET_TARGET__SHIFT         0
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET_TARGET_VM             0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET_TARGET_VRAM           0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET_TARGET_SYSRAM_NOSNOOP 0x00000003
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET_TARGET_SYSRAM         0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_MEM_TARGET_UNK31                 0x80000000

#define NVC0_PGRAPH_GPC_CTXCTL_UNITS(i0)                       (0x00502608 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_UNITS_TP_COUNT__MASK             0x0000001f
#define NVC0_PGRAPH_GPC_CTXCTL_UNITS_TP_COUNT__SHIFT            0
#define NVC0_PGRAPH_GPC_CTXCTL_UNITS_UNK_ZCULL_COUNT__MASK      0x001f0000
#define NVC0_PGRAPH_GPC_CTXCTL_UNITS_UNK_ZCULL_COUNT__SHIFT     16

#define NVC0_PGRAPH_GPC_CTXCTL_RED_SWITCH(i0)                  (0x00502614 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_RED_SWITCH_UNK0_GPC              0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_RED_SWITCH_POWER_GPC             0x00000020
#define NVC0_PGRAPH_GPC_CTXCTL_RED_SWITCH_ENABLE_GPC            0x00000200
#define NVC0_PGRAPH_GPC_CTXCTL_RED_SWITCH_UNK11                 0x00000800

#define NVC0_PGRAPH_GPC_CTXCTL_MYINDEX(i0)                     (0x00502618 + 0x8000*(i0))

#define NVC0_PGRAPH_GPC_CTXCTL_TRAP(i0)                        (0x00502c90 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_PROP                        0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_ZCULL                       0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_CCACHE                      0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_ESETUP                      0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_TP__MASK                    0x00ff0000
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_TP__SHIFT                   16

#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_EN(i0)                     (0x00502c94 + 0x8000*(i0))
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_EN_PROP                     0x00000001
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_EN_ZCULL                    0x00000002
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_EN_CCACHE                   0x00000004
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_EN_ESETUP                   0x00000008
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_EN_TP__MASK                 0x00ff0000
#define NVC0_PGRAPH_GPC_CTXCTL_TRAP_EN_TP__SHIFT                16

#define NVC0_PGRAPH_GPC_TP(i0, i1)                             (0x00504000 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP__ESIZE                               0x00000800
#define NVC0_PGRAPH_GPC_TP__LEN                                 0x00000004


#define NVC0_PGRAPH_GPC_TP_POLY(i0, i1)                        (0x00504000 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_POLY__ESIZE                          0x00000200

#define NVC0_PGRAPH_GPC_TP_POLY_POLY2ESETUP(i0, i1)            (0x00504048 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_POLY_POLY2ESETUP_ADDRESS__MASK       0x0fffffff
#define NVC0_PGRAPH_GPC_TP_POLY_POLY2ESETUP_ADDRESS__SHIFT      0
#define NVC0_PGRAPH_GPC_TP_POLY_POLY2ESETUP_ADDRESS__SHR        12
#define NVC0_PGRAPH_GPC_TP_POLY_POLY2ESETUP_UNK28               0x10000000

#define NVC0_PGRAPH_GPC_TP_POLY_TRAP(i0, i1)                   (0x00504084 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_POLY_TRAP_CLEAR                      0x40000000
#define NVC0_PGRAPH_GPC_TP_POLY_TRAP_ENABLE                     0x80000000

#define NVC0_PGRAPH_GPC_TP_POLY_TPID(i0, i1)                   (0x00504088 + 0x8000*(i0) + 0x800*(i1))

#define NVC0_PGRAPH_GPC_TP_TEX(i0, i1)                         (0x00504200 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_TEX__ESIZE                           0x00000100

#define NVC0_PGRAPH_GPC_TP_TEX_TRAP(i0, i1)                    (0x00504224 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_TEX_TRAP_CLEAR                       0x40000000
#define NVC0_PGRAPH_GPC_TP_TEX_TRAP_ENABLE                      0x80000000

#define NVC0_PGRAPH_GPC_TP_TPBUS(i0, i1)                       (0x00504300 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_TPBUS__ESIZE                         0x00000100

#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID(i0, i1, i2)          (0x00504300 + 0x8000*(i0) + 0x800*(i1) + 0x4*(i2))
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID__ESIZE                0x00000004
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID__LEN                  0x0000002c
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_0__MASK               0x0000001f
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_0__SHIFT              0
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_1__MASK               0x000003e0
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_1__SHIFT              5
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_2__MASK               0x00007c00
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_2__SHIFT              10
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_3__MASK               0x000f8000
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_3__SHIFT              15
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_4__MASK               0x01f00000
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_4__SHIFT              20
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_5__MASK               0x3e000000
#define NVC0_PGRAPH_GPC_TP_TPBUS_TP_GPCID_5__SHIFT              25

#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKD0(i0, i1)                 (0x005043d0 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKD0_ROPC_COUNT__MASK         0x000000ff
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKD0_ROPC_COUNT__SHIFT        0
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKD0_GPC_COUNT__MASK          0x0000ff00
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKD0_GPC_COUNT__SHIFT         8
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKD0_UNK16__MASK              0x1fff0000
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKD0_UNK16__SHIFT             16

#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKE4(i0, i1)                 (0x005043e4 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKE4_UNK0__MASK               0x3fffffff
#define NVC0_PGRAPH_GPC_TP_TPBUS_UNKE4_UNK0__SHIFT              0

#define NVC0_PGRAPH_GPC_TP_L1(i0, i1)                          (0x00504480 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_L1__ESIZE                            0x00000080

#define NVC0_PGRAPH_GPC_TP_L1_TRAP(i0, i1)                     (0x0050448c + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_L1_TRAP_GLOBAL_MAP_READ              0x00000002
#define NVC0_PGRAPH_GPC_TP_L1_TRAP_GLOBAL_MAP_WRITE             0x00000004
#define NVC0_PGRAPH_GPC_TP_L1_TRAP_CLEAR                        0x40000000
#define NVC0_PGRAPH_GPC_TP_L1_TRAP_ENABLE                       0x80000000

#define NVC0_PGRAPH_GPC_TP_L1_TPID(i0, i1)                     (0x005044e8 + 0x8000*(i0) + 0x800*(i1))

#define NVC0_PGRAPH_GPC_TP_TRAP(i0, i1)                        (0x00504508 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_TRAP_TEX                             0x00000001
#define NVC0_PGRAPH_GPC_TP_TRAP_MP                              0x00000002
#define NVC0_PGRAPH_GPC_TP_TRAP_POLY                            0x00000004
#define NVC0_PGRAPH_GPC_TP_TRAP_L1C                             0x00000008

#define NVC0_PGRAPH_GPC_TP_TRAP_EN(i0, i1)                     (0x0050450c + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_TRAP_EN_TEX                          0x00000001
#define NVC0_PGRAPH_GPC_TP_TRAP_EN_MP                           0x00000002
#define NVC0_PGRAPH_GPC_TP_TRAP_EN_POLY                         0x00000004
#define NVC0_PGRAPH_GPC_TP_TRAP_EN_L1C                          0x00000008

#define NVC0_PGRAPH_GPC_TP_MP(i0, i1)                          (0x00504600 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_MP__ESIZE                            0x00000200

#define NVC0_PGRAPH_GPC_TP_MP_UNK44_TRAP(i0, i1)               (0x00504644 + 0x8000*(i0) + 0x800*(i1))

#define NVC0_PGRAPH_GPC_TP_MP_UNK4C_TRAP(i0, i1)               (0x0050464c + 0x8000*(i0) + 0x800*(i1))

#define NVC0_PGRAPH_GPC_TP_MP_TRAP_HANDLER_PC(i0, i1)          (0x00504658 + 0x8000*(i0) + 0x800*(i1))

#define NVC0_PGRAPH_GPC_TP_MP_PM_OP(i0, i1, i2)                (0x00504660 + 0x8000*(i0) + 0x800*(i1) + 0x4*(i2))
#define NVC0_PGRAPH_GPC_TP_MP_PM_OP__ESIZE                      0x00000004
#define NVC0_PGRAPH_GPC_TP_MP_PM_OP__LEN                        0x00000004
#define NVC0_PGRAPH_GPC_TP_MP_PM_OP_0__MASK                     0x0000ffff
#define NVC0_PGRAPH_GPC_TP_MP_PM_OP_0__SHIFT                    0
#define NVC0_PGRAPH_GPC_TP_MP_PM_OP_1__MASK                     0xffff0000
#define NVC0_PGRAPH_GPC_TP_MP_PM_OP_1__SHIFT                    16

#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW(i0, i1)      (0x00504670 + 0x8000*(i0) + 0x800*(i1))
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_0             0x00000001
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_1             0x00000002
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_2             0x00000004
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_3             0x00000008
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_4             0x00000010
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_5             0x00000020
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_6             0x00000040
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER_OVERFLOW_7             0x00000080

#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER(i0, i1, i2)           (0x00504674 + 0x8000*(i0) + 0x800*(i1) + 0x4*(i2))
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER__ESIZE                 0x00000004
#define NVC0_PGRAPH_GPC_TP_MP_PM_COUNTER__LEN                   0x00000008

#define NVC0_PGRAPH_GPC_TP_MP_TPID(i0, i1)                     (0x00504698 + 0x8000*(i0) + 0x800*(i1))


#endif /* ___RNNDB____RNNDB_NVC0_PGRAPH_XML */