pscnv/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "nouveau_drv.h"
  27 #include "drm.h"
  28 #include "drm_sarea.h"
  29 #include "drm_crtc_helper.h"
  30 #ifdef __linux__
  31 #include <linux/swab.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #endif
  36
  37 #include "pscnv_drm.h"
  38 #include "nouveau_reg.h"
  39 #include "nouveau_fbcon.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42 #include "pscnv_vm.h"
  43 #include "pscnv_chan.h"
  44 #include "pscnv_fifo.h"
  45 #include "pscnv_ioctl.h"
  46
  47 static void nouveau_stub_takedown(struct drm_device *dev) {}
  48 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  49
  50 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  51 {
  52         struct drm_nouveau_private *dev_priv = dev->dev_private;
  53         struct nouveau_engine *engine = &dev_priv->engine;
  54
  55         if (dev_priv->chipset < 0x10) {
  56                 engine->gpio.init               = nouveau_stub_init;
  57                 engine->gpio.takedown           = nouveau_stub_takedown;
  58                 engine->gpio.get                = NULL;
  59                 engine->gpio.set                = NULL;
  60                 engine->gpio.irq_enable         = NULL;
  61                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  62                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  63                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  64         } else if (dev_priv->chipset < 0x50 || (dev_priv->chipset & 0xf0) == 0x60) {
  65                 engine->gpio.init               = nouveau_stub_init;
  66                 engine->gpio.takedown           = nouveau_stub_takedown;
  67                 engine->gpio.get                = nv10_gpio_get;
  68                 engine->gpio.set                = nv10_gpio_set;
  69                 engine->gpio.irq_enable         = NULL;
  70                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  71                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  72                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  73         } else {
  74                 u32 chip = dev_priv->chipset;
  75                 if (chip >= 0xc0)
  76                         chip &= ~0xf;
  77                 engine->gpio.init               = nv50_gpio_init;
  78                 engine->gpio.takedown           = nouveau_stub_takedown;
  79                 engine->gpio.get                = nv50_gpio_get;
  80                 engine->gpio.set                = nv50_gpio_set;
  81                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
  82                 engine->pm.pwm_get              = nv50_pm_pwm_get;
  83                 engine->pm.pwm_set              = nv50_pm_pwm_set;
  84                 engine->pm.counter.init         = nv40_counter_init;
  85                 engine->pm.counter.takedown     = nv40_counter_fini;
  86                 engine->pm.counter.watch        = nv40_counter_watch_signal;
  87                 engine->pm.counter.unwatch      = nv40_counter_unwatch_signal;
  88                 engine->pm.counter.poll         = nv40_counter_poll;
  89                 engine->pm.counter.start        = nv40_counter_start;
  90                 engine->pm.counter.stop         = nv40_counter_stop;
  91                 engine->pm.counter.signal_value = nv40_counter_value;
  92                 switch (chip) {
  93                 case 0xa3:
  94                 case 0xa5:
  95                 case 0xa8:
  96                 case 0xaf:
  97                         engine->pm.clocks_get   = nva3_pm_clocks_get;
  98                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
  99                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 100                         break;
 101                 case 0xd0:
 102                         engine->gpio.get        = nvd0_gpio_get;
 103                         engine->gpio.set        = nvd0_gpio_set;
 104                         engine->pm.pwm_get      = NULL;
 105                         engine->pm.pwm_set      = NULL;
 106                 case 0xc0:
 107                         engine->pm.clocks_get           = nvc0_pm_clocks_get;
 108                         engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 109                         engine->pm.clocks_set           = nvc0_pm_clocks_set;
 110                         break;
 111                 default:
 112                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 113                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 114                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 115                         break;
 116                 }
 117         }
 118
 119         if (dev_priv->chipset < 0x40) {
 120                 // Missing
 121         } else if (dev_priv->chipset < 0x80) {
 122                 engine->pm.temp_get             = nv40_temp_get;
 123         } else {
 124                 engine->pm.temp_get             = nv84_temp_get;
 125         }
 126
 127         engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 128         engine->pm.voltage_set_range    = nouveau_voltage_gpio_set_range;
 129
 130         if (dev_priv->chipset < 0x50 || (dev_priv->chipset & 0xf0) == 0x60) {
 131 #if 0
 132                 engine->display.early_init      = nv04_display_early_init;
 133                 engine->display.late_takedown   = nv04_display_late_takedown;
 134                 engine->display.create          = nv04_display_create;
 135                 engine->display.init            = nv04_display_init;
 136                 engine->display.destroy         = nv04_display_destroy;
 137 #endif
 138                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 139                 return -ENOSYS;
 140         } else if (dev_priv->chipset < 0xd0) {
 141                 engine->display.early_init      = nv50_display_early_init;
 142                 engine->display.late_takedown   = nv50_display_late_takedown;
 143                 engine->display.create          = nv50_display_create;
 144                 engine->display.init            = nv50_display_init;
 145                 engine->display.destroy         = nv50_display_destroy;
 146         } else {
 147                 engine->display.early_init      = nouveau_stub_init;
 148                 engine->display.late_takedown   = nouveau_stub_takedown;
 149                 engine->display.create          = nvd0_display_create;
 150                 engine->display.init            = nvd0_display_init;
 151                 engine->display.destroy         = nvd0_display_destroy;
 152         }
 153
 154         return 0;
 155 }
 156
 157 #ifdef __linux__
 158 static unsigned int
 159 nouveau_vga_set_decode(void *priv, bool state)
 160 {
 161         struct drm_device *dev = priv;
 162         struct drm_nouveau_private *dev_priv = dev->dev_private;
 163
 164         if (dev_priv->chipset >= 0x40)
 165                 nv_wr32(dev, 0x88054, state);
 166         else
 167                 nv_wr32(dev, 0x1854, state);
 168
 169         if (state)
 170                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 171                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 172         else
 173                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 174 }
 175
 176 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 177                                          enum vga_switcheroo_state state)
 178 {
 179         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 180         if (state == VGA_SWITCHEROO_ON) {
 181                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 182                 nouveau_pci_resume(pdev);
 183         } else {
 184                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 185                 nouveau_pci_suspend(pdev, pmm);
 186         }
 187 }
 188
 189 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 190 {
 191         struct drm_device *dev = pci_get_drvdata(pdev);
 192         nouveau_fbcon_output_poll_changed(dev);
 193 }
 194
 195 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 196 {
 197         struct drm_device *dev = pci_get_drvdata(pdev);
 198         bool can_switch;
 199
 200         spin_lock(&dev->count_lock);
 201         can_switch = (dev->open_count == 0);
 202         spin_unlock(&dev->count_lock);
 203         return can_switch;
 204 }
 205 #ifdef PSCNV_KAPI_SWITCHEROO_OPS
 206 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
 207         .set_gpu_state = nouveau_switcheroo_set_state,
 208         .reprobe = nouveau_switcheroo_reprobe,
 209         .can_switch = nouveau_switcheroo_can_switch,
 210 };
 211 #endif
 212 #endif /* __linux__ */
 213
 214 int
 215 nouveau_card_init(struct drm_device *dev)
 216 {
 217         struct drm_nouveau_private *dev_priv = dev->dev_private;
 218         struct nouveau_engine *engine;
 219         int ret;
 220         int i;
 221
 222         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 223
 224         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
 225                 return 0;
 226
 227         NV_INFO(dev, "Initializing card...\n");
 228
 229 #ifdef __linux__
 230         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 231 #ifdef PSCNV_KAPI_SWITCHEROO_OPS
 232         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
 233 #else
 234 #ifdef PSCNV_KAPI_SWITCHEROO_REPROBE
 235         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 236                                                                    nouveau_switcheroo_reprobe,
 237                                                                    nouveau_switcheroo_can_switch);
 238 #else
 239         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 240                                                                    nouveau_switcheroo_can_switch);
 241 #endif
 242 #endif
 243 #endif /* __linux__ */
 244
 245         dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
 246
 247         /* Initialise internal driver API hooks */
 248         ret = nouveau_init_engine_ptrs(dev);
 249         if (ret)
 250                 goto out;
 251         engine = &dev_priv->engine;
 252         spin_lock_init(&dev_priv->context_switch_lock);
 253
 254         /* Make the CRTCs and I2C buses accessible */
 255         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 256                 ret = engine->display.early_init(dev);
 257                 if (ret)
 258                         goto out;
 259         }
 260
 261         /* Parse BIOS tables / Run init tables if card not POSTed */
 262         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 263                 ret = nouveau_bios_init(dev);
 264                 if (ret)
 265                         goto out_display_early;
 266
 267                 /* workaround an odd issue on nvc1 by disabling the device's
 268                  * nosnoop capability.  hopefully won't cause issues until a
 269                  * better fix is found - assuming there is one...
 270                  */
 271                 if (dev_priv->chipset == 0xc1) {
 272                         nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 273                 }
 274         }
 275
 276         ret = pscnv_mem_init(dev);
 277         if (ret)
 278                 goto out_bios;
 279
 280         nouveau_pm_init(dev);
 281
 282         switch (dev_priv->card_type) {
 283                 case NV_50:
 284                         ret = nv50_chan_init(dev);
 285                         break;
 286                 case NV_D0:
 287                 case NV_C0:
 288                         ret = nvc0_chan_init(dev);
 289                         break;
 290                 default:
 291                         NV_ERROR(dev, "No CHAN implementation for NV%02x!\n", dev_priv->chipset);
 292                         ret = -ENOSYS;
 293         }
 294         if (ret)
 295                 goto out_vram;
 296
 297         switch (dev_priv->card_type) {
 298                 case NV_50:
 299                         ret = nv50_vm_init(dev);
 300                         break;
 301                 case NV_D0:
 302                 case NV_C0:
 303                         ret = nvc0_vm_init(dev);
 304                         break;
 305                 default:
 306                         NV_ERROR(dev, "No VM implementation for NV%02x!\n", dev_priv->chipset);
 307                         ret = -ENOSYS;
 308         }
 309         if (ret)
 310                 goto out_chan;
 311
 312         /* PMC */
 313         nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF);
 314
 315         /* PBUS */
 316         nv_wr32(dev, 0x1100, 0xFFFFFFFF);
 317         nv_wr32(dev, 0x1140, 0xFFFFFFFF);
 318
 319         /* PGPIO */
 320         ret = engine->gpio.init(dev);
 321         if (ret)
 322                 goto out_vm;
 323
 324         /* PTIMER */
 325         ret = nv04_timer_init(dev);
 326         if (ret)
 327                 goto out_gpio;
 328
 329         /* XXX: handle noaccel */
 330         switch (dev_priv->card_type) {
 331                 case NV_50:
 332                         /* PFIFO */
 333                         ret = nv50_fifo_init(dev);
 334                         if (!ret) {
 335                                 /* PGRAPH */
 336                                 nv50_graph_init(dev);
 337                         }
 338                         break;
 339                 case NV_D0:
 340                 case NV_C0:
 341                         /* PFIFO */
 342                         ret = nvc0_fifo_init(dev);
 343                         if (!ret) {
 344                                 /* PGRAPH */
 345                                 ret = nvc0_graph_init(dev);
 346                                 if (!ret && dev_priv->card_type == NV_C0) {
 347                                         /* PCOPY0 */
 348                                         nvc0_copy_init(dev, 0);
 349                                         /* PCOPY1 */
 350                                         nvc0_copy_init(dev, 1);
 351                                 }
 352                         }
 353                         break;
 354                 default:
 355                         break;
 356         }
 357         switch (dev_priv->chipset) {
 358                 case 0x84:
 359                 case 0x86:
 360                 case 0x92:
 361                 case 0x94:
 362                 case 0x96:
 363                 case 0xa0:
 364                         nv84_crypt_init(dev);
 365                         break;
 366                 case 0x98:
 367                 case 0xaa:
 368                 case 0xac:
 369                         nv98_crypt_init(dev);
 370                         break;
 371         }
 372
 373         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 374                 ret = nouveau_display_create(dev);
 375                 if (ret)
 376                         goto out_fifo;
 377         }
 378
 379         /* this call irq_preinstall, register irq handler and
 380          * call irq_postinstall
 381          */
 382 #ifdef __linux__
 383         ret = drm_irq_install(dev);
 384 #else
 385         // SIGH
 386         DRM_UNLOCK();
 387         ret = drm_irq_install(dev);
 388         DRM_LOCK();
 389 #endif
 390         if (ret)
 391                 goto out_display;
 392
 393         ret = drm_vblank_init(dev, 0);
 394         if (ret)
 395                 goto out_irq;
 396
 397         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 398 #if 0
 399         if (!engine->graph.accel_blocked) {
 400                 ret = nouveau_card_init_channel(dev);
 401                 if (ret)
 402                         goto out_irq;
 403         }
 404 #endif
 405
 406         ret = nouveau_backlight_init(dev);
 407         if (ret)
 408                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 409
 410         dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
 411
 412         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 413 #ifdef __linux__
 414                 nouveau_fbcon_init(dev);
 415 #else
 416                 // SIGH
 417                 DRM_UNLOCK();
 418                 nouveau_fbcon_init(dev);
 419                 DRM_LOCK();
 420 #endif
 421                 drm_kms_helper_poll_init(dev);
 422         }
 423
 424         NV_INFO(dev, "Card initialized.\n");
 425         return 0;
 426
 427 #if 0
 428 out_channel:
 429         if (dev_priv->channel) {
 430                 nouveau_channel_free(dev_priv->channel);
 431                 dev_priv->channel = NULL;
 432         }
 433 #endif
 434 out_irq:
 435         drm_irq_uninstall(dev);
 436 out_display:
 437         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 438                 nouveau_display_destroy(dev);
 439         }
 440 out_fifo:
 441         for (i = 0; i < PSCNV_ENGINES_NUM; i++)
 442                 if (dev_priv->engines[i]) {
 443                         dev_priv->engines[i]->takedown(dev_priv->engines[i]);
 444                         dev_priv->engines[i] = 0;
 445                 }
 446         if (dev_priv->fifo)
 447                 dev_priv->fifo->takedown(dev);
 448 out_gpio:
 449         engine->gpio.takedown(dev);
 450 out_vm:
 451         nv_wr32(dev, 0x1140, 0);
 452         dev_priv->vm->takedown(dev);
 453 out_chan:
 454         dev_priv->chan->takedown(dev);
 455         nouveau_pm_fini(dev);
 456 out_vram:
 457         pscnv_mem_takedown(dev);
 458 out_bios:
 459         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 460                 nouveau_bios_takedown(dev);
 461         }
 462 out_display_early:
 463         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 464                 engine->display.late_takedown(dev);
 465         }
 466 out:
 467 #ifdef __linux__
 468         vga_client_register(dev->pdev, NULL, NULL, NULL);
 469 #endif
 470         return ret;
 471 }
 472
 473 static void nouveau_card_takedown(struct drm_device *dev)
 474 {
 475         struct drm_nouveau_private *dev_priv = dev->dev_private;
 476         int i;
 477
 478         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 479
 480         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE) {
 481                 NV_INFO(dev, "Stopping card...\n");
 482                 nouveau_backlight_exit(dev);
 483                 drm_irq_uninstall(dev);
 484                 flush_workqueue(dev_priv->wq);
 485                 for (i = 0; i < PSCNV_ENGINES_NUM; i++)
 486                         if (dev_priv->engines[i]) {
 487                                 dev_priv->engines[i]->takedown(dev_priv->engines[i]);
 488                                 dev_priv->engines[i] = 0;
 489                         }
 490                 if (dev_priv->fifo)
 491                         dev_priv->fifo->takedown(dev);
 492                 dev_priv->vm->takedown(dev);
 493                 dev_priv->chan->takedown(dev);
 494                 pscnv_mem_takedown(dev);
 495                 nv_wr32(dev, 0x1140, 0);
 496                 nouveau_pm_fini(dev);
 497                 nouveau_bios_takedown(dev);
 498
 499 #ifdef __linux__
 500                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 501 #endif
 502                 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 503                 NV_INFO(dev, "Card stopped.\n");
 504         }
 505 }
 506
 507 /* here a client dies, release the stuff that was allocated for its
 508  * file_priv */
 509 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 510 {
 511         pscnv_chan_cleanup(dev, file_priv);
 512         pscnv_vspace_cleanup(dev, file_priv);
 513 }
 514
 515 /* first module load, setup the mmio/fb mapping */
 516 /* KMS: we need mmio at load time, not when the first drm client opens. */
 517 int nouveau_firstopen(struct drm_device *dev)
 518 {
 519         nouveau_card_init(dev);
 520         return 0;
 521 }
 522
 523 /* if we have an OF card, copy vbios to RAMIN */
 524 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 525 {
 526 #if defined(__powerpc__)
 527         int size, i;
 528         const uint32_t *bios;
 529         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 530         if (!dn) {
 531                 NV_INFO(dev, "Unable to get the OF node\n");
 532                 return;
 533         }
 534
 535         bios = of_get_property(dn, "NVDA,BMP", &size);
 536         if (bios) {
 537                 for (i = 0; i < size; i += 4)
 538                         nv_wi32(dev, i, bios[i/4]);
 539                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 540         } else {
 541                 NV_INFO(dev, "Unable to get the OF bios\n");
 542         }
 543 #endif
 544 }
 545
 546 #ifdef __linux__
 547 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 548 {
 549         struct pci_dev *pdev = dev->pdev;
 550         struct apertures_struct *aper = alloc_apertures(3);
 551         if (!aper)
 552                 return NULL;
 553
 554         aper->ranges[0].base = pci_resource_start(pdev, 1);
 555         aper->ranges[0].size = pci_resource_len(pdev, 1);
 556         aper->count = 1;
 557
 558         if (pci_resource_len(pdev, 2)) {
 559                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 560                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 561                 aper->count++;
 562         }
 563
 564         if (pci_resource_len(pdev, 3)) {
 565                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 566                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 567                 aper->count++;
 568         }
 569
 570         return aper;
 571 }
 572 #endif
 573
 574 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 575 {
 576 #ifdef __linux__
 577         struct drm_nouveau_private *dev_priv = dev->dev_private;
 578         bool primary = false;
 579         dev_priv->apertures = nouveau_get_apertures(dev);
 580         if (!dev_priv->apertures)
 581                 return -ENOMEM;
 582
 583 #ifdef CONFIG_X86
 584         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 585 #endif
 586
 587         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 588 #endif
 589         return 0;
 590 }
 591
 592 int nouveau_load(struct drm_device *dev, unsigned long flags)
 593 {
 594         struct drm_nouveau_private *dev_priv;
 595         uint32_t reg0, strap;
 596         resource_size_t mmio_start_offs;
 597         int ret;
 598
 599         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 600         if (!dev_priv)
 601                 return -ENOMEM;
 602         dev->dev_private = dev_priv;
 603         dev_priv->dev = dev;
 604
 605         dev_priv->flags = flags/* & NOUVEAU_FLAGS*/;
 606         dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 607
 608         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X\n",
 609                  dev->pci_vendor, dev->pci_device);
 610
 611         dev_priv->wq = create_workqueue("nouveau");
 612         if (!dev_priv->wq)
 613                 return -EINVAL;
 614
 615         /* resource 0 is mmio regs */
 616         /* resource 1 is linear FB */
 617         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 618         /* resource 6 is bios */
 619
 620         /* map the mmio regs */
 621         mmio_start_offs = drm_get_resource_start(dev, 0);
 622         ret = drm_addmap(dev, mmio_start_offs, 0x00800000, _DRM_REGISTERS,
 623             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio);
 624
 625         if (ret) {
 626                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 627                          "Please report your setup to " DRIVER_EMAIL "\n");
 628                 return ret;
 629         }
 630         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 631                                         (unsigned long long)mmio_start_offs);
 632
 633 #ifdef __BIG_ENDIAN
 634         /* Put the card in BE mode if it's not */
 635         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 636                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 637
 638         DRM_MEMORYBARRIER();
 639 #endif
 640
 641         /* Time to determine the card architecture */
 642         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 643
 644         /* We're dealing with >=NV10 */
 645         if ((reg0 & 0x0f000000) > 0) {
 646                 /* Bit 27-20 contain the architecture in hex */
 647                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 648         /* NV04 or NV05 */
 649         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 650                 if (reg0 & 0x00f00000)
 651                         dev_priv->chipset = 0x05;
 652                 else
 653                         dev_priv->chipset = 0x04;
 654         } else {
 655                 dev_priv->chipset = (reg0 & 0xf0000) >> 16;
 656                 if (dev_priv->chipset < 1 || dev_priv->chipset > 3)
 657                         dev_priv->chipset = 0xff;
 658         }
 659
 660         switch (dev_priv->chipset & 0xf0) {
 661         case 0x00:
 662                 if (dev_priv->chipset >= 4)
 663                         dev_priv->card_type = NV_04;
 664                 else
 665                         dev_priv->card_type = dev_priv->chipset;
 666                 break;
 667         case 0x10:
 668         case 0x20:
 669         case 0x30:
 670                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 671                 break;
 672         case 0x40:
 673         case 0x60:
 674                 dev_priv->card_type = NV_40;
 675                 break;
 676         case 0x50:
 677         case 0x80:
 678         case 0x90:
 679         case 0xa0:
 680                 dev_priv->card_type = NV_50;
 681                 break;
 682         case 0xc0:
 683                 dev_priv->card_type = NV_C0;
 684                 break;
 685         case 0xd0:
 686                 dev_priv->card_type = NV_D0;
 687                 break;
 688         default:
 689                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 690                 return -EINVAL;
 691         }
 692
 693         NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
 694                 dev_priv->card_type, reg0);
 695
 696         /* determine frequency of timing crystal */
 697         strap = nv_rd32(dev, 0x101000);
 698         if ( dev_priv->chipset < 0x17 ||
 699             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
 700                 strap &= 0x00000040;
 701         else
 702                 strap &= 0x00400040;
 703
 704         switch (strap) {
 705         case 0x00000000: dev_priv->crystal = 13500; break;
 706         case 0x00000040: dev_priv->crystal = 14318; break;
 707         case 0x00400000: dev_priv->crystal = 27000; break;
 708         case 0x00400040: dev_priv->crystal = 25000; break;
 709         }
 710
 711         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
 712
 713         dev_priv->fb_size = drm_get_resource_len(dev, 1);
 714         dev_priv->fb_phys = drm_get_resource_start(dev, 1);
 715         dev_priv->mmio_phys = drm_get_resource_start(dev, 0);
 716
 717         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 718                 int ret = nouveau_remove_conflicting_drivers(dev);
 719                 if (ret)
 720                         return ret;
 721         }
 722
 723         /* map larger RAMIN aperture on NV40 cards */
 724         if (dev_priv->card_type >= NV_40) {
 725                 int ramin_bar = 2;
 726                 if (drm_get_resource_len(dev, ramin_bar) < PAGE_SIZE)
 727                         ramin_bar = 3;
 728
 729                 dev_priv->ramin_size = drm_get_resource_len(dev, ramin_bar);
 730                 ret = drm_addmap(dev, drm_get_resource_start(dev, ramin_bar),
 731                                  dev_priv->ramin_size, _DRM_REGISTERS,
 732                                  _DRM_KERNEL | _DRM_DRIVER, &dev_priv->ramin);
 733                 if (ret) {
 734                         NV_ERROR(dev, "Failed to init RAMIN mapping\n");
 735                         return ret;
 736                 }
 737         }
 738
 739         nouveau_OF_copy_vbios_to_ramin(dev);
 740
 741         /* Special flags */
 742         if (dev->pci_device == 0x01a0)
 743                 dev_priv->flags |= NV_NFORCE;
 744         else if (dev->pci_device == 0x01f0)
 745                 dev_priv->flags |= NV_NFORCE2;
 746
 747         /* For kernel modesetting, init card now and bring up fbcon */
 748         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 749                 int ret = nouveau_card_init(dev);
 750                 if (ret)
 751                         return ret;
 752         }
 753
 754         return 0;
 755 }
 756
 757 static void nouveau_close(struct drm_device *dev)
 758 {
 759         struct drm_nouveau_private *dev_priv = dev->dev_private;
 760
 761         /* In the case of an error dev_priv may not be allocated yet */
 762         if (dev_priv)
 763                 nouveau_card_takedown(dev);
 764 }
 765
 766 /* KMS: we need mmio at load time, not when the first drm client opens. */
 767 void nouveau_lastclose(struct drm_device *dev)
 768 {
 769         if (drm_core_check_feature(dev, DRIVER_MODESET))
 770                 return;
 771
 772         nouveau_close(dev);
 773 }
 774
 775 int nouveau_unload(struct drm_device *dev)
 776 {
 777         struct drm_nouveau_private *dev_priv = dev->dev_private;
 778
 779         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 780                 nouveau_fbcon_fini(dev);
 781                 nouveau_display_destroy(dev);
 782                 nouveau_close(dev);
 783         }
 784         destroy_workqueue(dev_priv->wq);
 785
 786         drm_rmmap(dev, dev_priv->mmio);
 787         drm_rmmap(dev, dev_priv->ramin);
 788
 789         kfree(dev_priv);
 790         dev->dev_private = NULL;
 791         return 0;
 792 }
 793
 794 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
 795 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
 796                         uint32_t reg, uint32_t mask, uint32_t val)
 797 {
 798         uint64_t start = nv04_timer_read(dev);
 799
 800         do {
 801                 if ((nv_rd32(dev, reg) & mask) == val)
 802                         return true;
 803         } while (nv04_timer_read(dev) - start < timeout);
 804
 805         return false;
 806 }
 807
 808 /* Wait until (value(reg) & mask) != val, up until timeout has hit. */
 809 bool nouveau_wait_until_neq(struct drm_device *dev, uint64_t timeout,
 810                             uint32_t reg, uint32_t mask, uint32_t val)
 811 {
 812         uint64_t start = nv04_timer_read(dev);
 813
 814         do {
 815                 if ((nv_rd32(dev, reg) & mask) != val)
 816                         return true;
 817         } while (nv04_timer_read(dev) - start < timeout);
 818
 819         return false;
 820 }
 821
 822 bool
 823 nouveau_wait_cb(struct drm_device *dev, uint64_t timeout,
 824                 bool (*cond)(void *), void *data)
 825 {
 826         uint64_t start = nv04_timer_read(dev);
 827
 828         do {
 829                 if (cond(data) == true)
 830                         return true;
 831         } while (nv04_timer_read(dev) - start < timeout);
 832
 833         return false;
 834 }