drivers/net/fec_8xx/fec_8xx.h

   1 #ifndef FEC_8XX_H
   2 #define FEC_8XX_H
   3
   4 #include <linux/mii.h>
   5 #include <linux/netdevice.h>
   6
   7 #include <linux/types.h>
   8
   9 /* HW info */
  10
  11 /* CRC polynomium used by the FEC for the multicast group filtering */
  12 #define FEC_CRC_POLY   0x04C11DB7
  13
  14 #define MII_ADVERTISE_HALF      (ADVERTISE_100HALF | \
  15                                  ADVERTISE_10HALF | ADVERTISE_CSMA)
  16 #define MII_ADVERTISE_ALL       (ADVERTISE_100FULL | \
  17                                  ADVERTISE_10FULL | MII_ADVERTISE_HALF)
  18
  19 /* Interrupt events/masks.
  20 */
  21 #define FEC_ENET_HBERR  0x80000000U     /* Heartbeat error          */
  22 #define FEC_ENET_BABR   0x40000000U     /* Babbling receiver        */
  23 #define FEC_ENET_BABT   0x20000000U     /* Babbling transmitter     */
  24 #define FEC_ENET_GRA    0x10000000U     /* Graceful stop complete   */
  25 #define FEC_ENET_TXF    0x08000000U     /* Full frame transmitted   */
  26 #define FEC_ENET_TXB    0x04000000U     /* A buffer was transmitted */
  27 #define FEC_ENET_RXF    0x02000000U     /* Full frame received      */
  28 #define FEC_ENET_RXB    0x01000000U     /* A buffer was received    */
  29 #define FEC_ENET_MII    0x00800000U     /* MII interrupt            */
  30 #define FEC_ENET_EBERR  0x00400000U     /* SDMA bus error           */
  31
  32 #define FEC_ECNTRL_PINMUX       0x00000004
  33 #define FEC_ECNTRL_ETHER_EN     0x00000002
  34 #define FEC_ECNTRL_RESET        0x00000001
  35
  36 #define FEC_RCNTRL_BC_REJ       0x00000010
  37 #define FEC_RCNTRL_PROM         0x00000008
  38 #define FEC_RCNTRL_MII_MODE     0x00000004
  39 #define FEC_RCNTRL_DRT          0x00000002
  40 #define FEC_RCNTRL_LOOP         0x00000001
  41
  42 #define FEC_TCNTRL_FDEN         0x00000004
  43 #define FEC_TCNTRL_HBC          0x00000002
  44 #define FEC_TCNTRL_GTS          0x00000001
  45
  46 /* values for MII phy_status */
  47
  48 #define PHY_CONF_ANE    0x0001  /* 1 auto-negotiation enabled     */
  49 #define PHY_CONF_LOOP   0x0002  /* 1 loopback mode enabled        */
  50 #define PHY_CONF_SPMASK 0x00f0  /* mask for speed                 */
  51 #define PHY_CONF_10HDX  0x0010  /* 10 Mbit half duplex supported  */
  52 #define PHY_CONF_10FDX  0x0020  /* 10 Mbit full duplex supported  */
  53 #define PHY_CONF_100HDX 0x0040  /* 100 Mbit half duplex supported */
  54 #define PHY_CONF_100FDX 0x0080  /* 100 Mbit full duplex supported */
  55
  56 #define PHY_STAT_LINK   0x0100  /* 1 up - 0 down                  */
  57 #define PHY_STAT_FAULT  0x0200  /* 1 remote fault                 */
  58 #define PHY_STAT_ANC    0x0400  /* 1 auto-negotiation complete    */
  59 #define PHY_STAT_SPMASK 0xf000  /* mask for speed                 */
  60 #define PHY_STAT_10HDX  0x1000  /* 10 Mbit half duplex selected   */
  61 #define PHY_STAT_10FDX  0x2000  /* 10 Mbit full duplex selected   */
  62 #define PHY_STAT_100HDX 0x4000  /* 100 Mbit half duplex selected  */
  63 #define PHY_STAT_100FDX 0x8000  /* 100 Mbit full duplex selected  */
  64
  65 typedef struct phy_info {
  66         unsigned int id;
  67         const char *name;
  68         void (*startup) (struct net_device * dev);
  69         void (*shutdown) (struct net_device * dev);
  70         void (*ack_int) (struct net_device * dev);
  71 } phy_info_t;
  72
  73 /* The FEC stores dest/src/type, data, and checksum for receive packets.
  74  */
  75 #define MAX_MTU 1508            /* Allow fullsized pppoe packets over VLAN */
  76 #define MIN_MTU 46              /* this is data size */
  77 #define CRC_LEN 4
  78
  79 #define PKT_MAXBUF_SIZE         (MAX_MTU+ETH_HLEN+CRC_LEN)
  80 #define PKT_MINBUF_SIZE         (MIN_MTU+ETH_HLEN+CRC_LEN)
  81
  82 /* Must be a multiple of 4 */
  83 #define PKT_MAXBLR_SIZE         ((PKT_MAXBUF_SIZE+3) & ~3)
  84 /* This is needed so that invalidate_xxx wont invalidate too much */
  85 #define ENET_RX_FRSIZE          L1_CACHE_ALIGN(PKT_MAXBUF_SIZE)
  86
  87 /* platform interface */
  88
  89 struct fec_platform_info {
  90         int fec_no;             /* FEC index                  */
  91         int use_mdio;           /* use external MII           */
  92         int phy_addr;           /* the phy address            */
  93         int fec_irq, phy_irq;   /* the irq for the controller */
  94         int rx_ring, tx_ring;   /* number of buffers on rx    */
  95         int sys_clk;            /* system clock               */
  96         __u8 macaddr[6];        /* mac address                */
  97         int rx_copybreak;       /* limit we copy small frames */
  98         int use_napi;           /* use NAPI                   */
  99         int napi_weight;        /* NAPI weight                */
 100 };
 101
 102 /* forward declaration */
 103 struct fec;
 104
 105 struct fec_enet_private {
 106         spinlock_t lock;        /* during all ops except TX pckt processing */
 107         spinlock_t tx_lock;     /* during fec_start_xmit and fec_tx         */
 108         struct net_device *dev;
 109         struct napi_struct napi;
 110         int fecno;
 111         struct fec *fecp;
 112         const struct fec_platform_info *fpi;
 113         int rx_ring, tx_ring;
 114         dma_addr_t ring_mem_addr;
 115         void *ring_base;
 116         struct sk_buff **rx_skbuff;
 117         struct sk_buff **tx_skbuff;
 118         cbd_t *rx_bd_base;      /* Address of Rx and Tx buffers.    */
 119         cbd_t *tx_bd_base;
 120         cbd_t *dirty_tx;        /* ring entries to be free()ed.     */
 121         cbd_t *cur_rx;
 122         cbd_t *cur_tx;
 123         int tx_free;
 124         struct net_device_stats stats;
 125         struct timer_list phy_timer_list;
 126         const struct phy_info *phy;
 127         unsigned int fec_phy_speed;
 128         __u32 msg_enable;
 129         struct mii_if_info mii_if;
 130 };
 131
 132 /***************************************************************************/
 133
 134 void fec_restart(struct net_device *dev, int duplex, int speed);
 135 void fec_stop(struct net_device *dev);
 136
 137 /***************************************************************************/
 138
 139 int fec_mii_read(struct net_device *dev, int phy_id, int location);
 140 void fec_mii_write(struct net_device *dev, int phy_id, int location, int value);
 141
 142 int fec_mii_phy_id_detect(struct net_device *dev);
 143 void fec_mii_startup(struct net_device *dev);
 144 void fec_mii_shutdown(struct net_device *dev);
 145 void fec_mii_ack_int(struct net_device *dev);
 146
 147 void fec_mii_link_status_change_check(struct net_device *dev, int init_media);
 148
 149 /***************************************************************************/
 150
 151 #define FEC1_NO 0x00
 152 #define FEC2_NO 0x01
 153 #define FEC3_NO 0x02
 154
 155 int fec_8xx_init_one(const struct fec_platform_info *fpi,
 156                      struct net_device **devp);
 157 int fec_8xx_cleanup_one(struct net_device *dev);
 158
 159 /***************************************************************************/
 160
 161 #define DRV_MODULE_NAME         "fec_8xx"
 162 #define PFX DRV_MODULE_NAME     ": "
 163 #define DRV_MODULE_VERSION      "0.1"
 164 #define DRV_MODULE_RELDATE      "May 6, 2004"
 165
 166 /***************************************************************************/
 167
 168 int fec_8xx_platform_init(void);
 169 void fec_8xx_platform_cleanup(void);
 170
 171 /***************************************************************************/
 172
 173 /* FEC access macros */
 174 #if defined(CONFIG_8xx)
 175 /* for a 8xx __raw_xxx's are sufficient */
 176 #define __fec_out32(addr, x)    __raw_writel(x, addr)
 177 #define __fec_out16(addr, x)    __raw_writew(x, addr)
 178 #define __fec_in32(addr)        __raw_readl(addr)
 179 #define __fec_in16(addr)        __raw_readw(addr)
 180 #else
 181 /* for others play it safe */
 182 #define __fec_out32(addr, x)    out_be32(addr, x)
 183 #define __fec_out16(addr, x)    out_be16(addr, x)
 184 #define __fec_in32(addr)        in_be32(addr)
 185 #define __fec_in16(addr)        in_be16(addr)
 186 #endif
 187
 188 /* write */
 189 #define FW(_fecp, _reg, _v) __fec_out32(&(_fecp)->fec_ ## _reg, (_v))
 190
 191 /* read */
 192 #define FR(_fecp, _reg) __fec_in32(&(_fecp)->fec_ ## _reg)
 193
 194 /* set bits */
 195 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
 196
 197 /* clear bits */
 198 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
 199
 200 /* buffer descriptor access macros */
 201
 202 /* write */
 203 #define CBDW_SC(_cbd, _sc)              __fec_out16(&(_cbd)->cbd_sc, (_sc))
 204 #define CBDW_DATLEN(_cbd, _datlen)      __fec_out16(&(_cbd)->cbd_datlen, (_datlen))
 205 #define CBDW_BUFADDR(_cbd, _bufaddr)    __fec_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
 206
 207 /* read */
 208 #define CBDR_SC(_cbd)                   __fec_in16(&(_cbd)->cbd_sc)
 209 #define CBDR_DATLEN(_cbd)               __fec_in16(&(_cbd)->cbd_datlen)
 210 #define CBDR_BUFADDR(_cbd)              __fec_in32(&(_cbd)->cbd_bufaddr)
 211
 212 /* set bits */
 213 #define CBDS_SC(_cbd, _sc)              CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
 214
 215 /* clear bits */
 216 #define CBDC_SC(_cbd, _sc)              CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
 217
 218 /***************************************************************************/
 219
 220 #endif