drivers/net/tokenring/olympic.h

   1 /*
   2  *  olympic.h (c) 1999 Peter De Schrijver All Rights Reserved
   3  *                1999,2000 Mike Phillips (mikep@linuxtr.net)
   4  *
   5  *  Linux driver for IBM PCI tokenring cards based on the olympic and the PIT/PHY chipset.
   6  *
   7  *  Base Driver Skeleton:
   8  *      Written 1993-94 by Donald Becker.
   9  *
  10  *      Copyright 1993 United States Government as represented by the
  11  *      Director, National Security Agency.
  12  *
  13  *  This software may be used and distributed according to the terms
  14  *  of the GNU General Public License, incorporated herein by reference.
  15  */
  16
  17 #define CID 0x4e
  18
  19 #define BCTL 0x70
  20 #define BCTL_SOFTRESET (1<<15)
  21 #define BCTL_MIMREB (1<<6)
  22 #define BCTL_MODE_INDICATOR (1<<5)
  23
  24 #define GPR 0x4a
  25 #define GPR_OPTI_BF (1<<6)
  26 #define GPR_NEPTUNE_BF (1<<4)
  27 #define GPR_AUTOSENSE (1<<2)
  28 #define GPR_16MBPS (1<<3)
  29
  30 #define PAG 0x85
  31 #define LBC 0x8e
  32
  33 #define LISR 0x10
  34 #define LISR_SUM 0x14
  35 #define LISR_RWM 0x18
  36
  37 #define LISR_LIE (1<<15)
  38 #define LISR_SLIM (1<<13)
  39 #define LISR_SLI (1<<12)
  40 #define LISR_PCMSRMASK (1<<11)
  41 #define LISR_PCMSRINT (1<<10)
  42 #define LISR_WOLMASK (1<<9)
  43 #define LISR_WOL (1<<8)
  44 #define LISR_SRB_CMD (1<<5)
  45 #define LISR_ASB_REPLY (1<<4)
  46 #define LISR_ASB_FREE_REQ (1<<2)
  47 #define LISR_ARB_FREE (1<<1)
  48 #define LISR_TRB_FRAME (1<<0)
  49
  50 #define SISR 0x20
  51 #define SISR_SUM 0x24
  52 #define SISR_RWM 0x28
  53 #define SISR_RR 0x2C
  54 #define SISR_RESMASK 0x30
  55 #define SISR_MASK 0x54
  56 #define SISR_MASK_SUM 0x58
  57 #define SISR_MASK_RWM 0x5C
  58
  59 #define SISR_TX2_IDLE (1<<31)
  60 #define SISR_TX2_HALT (1<<29)
  61 #define SISR_TX2_EOF (1<<28)
  62 #define SISR_TX1_IDLE (1<<27)
  63 #define SISR_TX1_HALT (1<<25)
  64 #define SISR_TX1_EOF (1<<24)
  65 #define SISR_TIMEOUT (1<<23)
  66 #define SISR_RX_NOBUF (1<<22)
  67 #define SISR_RX_STATUS (1<<21)
  68 #define SISR_RX_HALT (1<<18)
  69 #define SISR_RX_EOF_EARLY (1<<16)
  70 #define SISR_MI (1<<15)
  71 #define SISR_PI (1<<13)
  72 #define SISR_ERR (1<<9)
  73 #define SISR_ADAPTER_CHECK (1<<6)
  74 #define SISR_SRB_REPLY (1<<5)
  75 #define SISR_ASB_FREE (1<<4)
  76 #define SISR_ARB_CMD (1<<3)
  77 #define SISR_TRB_REPLY (1<<2)
  78
  79 #define EISR 0x34
  80 #define EISR_RWM 0x38
  81 #define EISR_MASK 0x3c
  82 #define EISR_MASK_OPTIONS 0x001FFF7F
  83
  84 #define LAPA 0x60
  85 #define LAPWWO 0x64
  86 #define LAPWWC 0x68
  87 #define LAPCTL 0x6C
  88 #define LAIPD 0x78
  89 #define LAIPDDINC 0x7C
  90
  91 #define TIMER 0x50
  92
  93 #define CLKCTL 0x74
  94 #define CLKCTL_PAUSE (1<<15)
  95
  96 #define PM_CON 0x4
  97
  98 #define BMCTL_SUM 0x40
  99 #define BMCTL_RWM 0x44
 100 #define BMCTL_TX2_DIS (1<<30)
 101 #define BMCTL_TX1_DIS (1<<26)
 102 #define BMCTL_RX_DIS (1<<22)
 103
 104 #define BMASR 0xcc
 105
 106 #define RXDESCQ 0x90
 107 #define RXDESCQCNT 0x94
 108 #define RXCDA 0x98
 109 #define RXENQ 0x9C
 110 #define RXSTATQ 0xA0
 111 #define RXSTATQCNT 0xA4
 112 #define RXCSA 0xA8
 113 #define RXCLEN 0xAC
 114 #define RXHLEN 0xAE
 115
 116 #define TXDESCQ_1 0xb0
 117 #define TXDESCQ_2 0xd0
 118 #define TXDESCQCNT_1 0xb4
 119 #define TXDESCQCNT_2 0xd4
 120 #define TXCDA_1 0xb8
 121 #define TXCDA_2 0xd8
 122 #define TXENQ_1 0xbc
 123 #define TXENQ_2 0xdc
 124 #define TXSTATQ_1 0xc0
 125 #define TXSTATQ_2 0xe0
 126 #define TXSTATQCNT_1 0xc4
 127 #define TXSTATQCNT_2 0xe4
 128 #define TXCSA_1 0xc8
 129 #define TXCSA_2 0xe8
 130 /* Cardbus */
 131 #define FERMASK 0xf4
 132 #define FERMASK_INT_BIT (1<<15)
 133
 134 #define OLYMPIC_IO_SPACE 256
 135
 136 #define SRB_COMMAND_SIZE 50
 137
 138 #define OLYMPIC_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
 139
 140 /* Defines for LAN STATUS CHANGE reports */
 141 #define LSC_SIG_LOSS 0x8000
 142 #define LSC_HARD_ERR 0x4000
 143 #define LSC_SOFT_ERR 0x2000
 144 #define LSC_TRAN_BCN 0x1000
 145 #define LSC_LWF      0x0800
 146 #define LSC_ARW      0x0400
 147 #define LSC_FPE      0x0200
 148 #define LSC_RR       0x0100
 149 #define LSC_CO       0x0080
 150 #define LSC_SS       0x0040
 151 #define LSC_RING_REC 0x0020
 152 #define LSC_SR_CO    0x0010
 153 #define LSC_FDX_MODE 0x0004
 154
 155 /* Defines for OPEN ADAPTER command */
 156
 157 #define OPEN_ADAPTER_EXT_WRAP (1<<15)
 158 #define OPEN_ADAPTER_DIS_HARDEE (1<<14)
 159 #define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
 160 #define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
 161 #define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
 162 #define OPEN_ADAPTER_ENABLE_EC (1<<10)
 163 #define OPEN_ADAPTER_CONTENDER (1<<8)
 164 #define OPEN_ADAPTER_PASS_BEACON (1<<7)
 165 #define OPEN_ADAPTER_ENABLE_FDX (1<<6)
 166 #define OPEN_ADAPTER_ENABLE_RPL (1<<5)
 167 #define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
 168 #define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
 169 #define OPEN_ADAPTER_USE_OPTS2 (1<<0)
 170
 171 #define OPEN_ADAPTER_2_ENABLE_ONNOW (1<<15)
 172
 173 /* Defines for SRB Commands */
 174
 175 #define SRB_ACCESS_REGISTER 0x1f
 176 #define SRB_CLOSE_ADAPTER 0x04
 177 #define SRB_CONFIGURE_BRIDGE 0x0c
 178 #define SRB_CONFIGURE_WAKEUP_EVENT 0x1a
 179 #define SRB_MODIFY_BRIDGE_PARMS 0x15
 180 #define SRB_MODIFY_OPEN_OPTIONS 0x01
 181 #define SRB_MODIFY_RECEIVE_OPTIONS 0x17
 182 #define SRB_NO_OPERATION 0x00
 183 #define SRB_OPEN_ADAPTER 0x03
 184 #define SRB_READ_LOG 0x08
 185 #define SRB_READ_SR_COUNTERS 0x16
 186 #define SRB_RESET_GROUP_ADDRESS 0x02
 187 #define SRB_SAVE_CONFIGURATION 0x1b
 188 #define SRB_SET_BRIDGE_PARMS 0x09
 189 #define SRB_SET_BRIDGE_TARGETS 0x10
 190 #define SRB_SET_FUNC_ADDRESS 0x07
 191 #define SRB_SET_GROUP_ADDRESS 0x06
 192 #define SRB_SET_GROUP_ADDR_OPTIONS 0x11
 193 #define SRB_UPDATE_WAKEUP_PATTERN 0x19
 194
 195 /* Clear return code */
 196
 197 #define OLYMPIC_CLEAR_RET_CODE 0xfe
 198
 199 /* ARB Commands */
 200 #define ARB_RECEIVE_DATA 0x81
 201 #define ARB_LAN_CHANGE_STATUS 0x84
 202 /* ASB Response commands */
 203
 204 #define ASB_RECEIVE_DATA 0x81
 205
 206
 207 /* Olympic defaults for buffers */
 208
 209 #define OLYMPIC_RX_RING_SIZE 16 /* should be a power of 2 */
 210 #define OLYMPIC_TX_RING_SIZE 8 /* should be a power of 2 */
 211
 212 #define PKT_BUF_SZ 4096 /* Default packet size */
 213
 214 /* Olympic data structures */
 215
 216 /* xxxx These structures are all little endian in hardware. */
 217
 218 struct olympic_tx_desc {
 219         u32 buffer;
 220         u32 status_length;
 221 };
 222
 223 struct olympic_tx_status {
 224         u32 status;
 225 };
 226
 227 struct olympic_rx_desc {
 228         u32 buffer;
 229         u32 res_length;
 230 };
 231
 232 struct olympic_rx_status {
 233         u32 fragmentcnt_framelen;
 234         u32 status_buffercnt;
 235 };
 236 /* xxxx END These structures are all little endian in hardware. */
 237 /* xxxx There may be more, but I'm pretty sure about these */
 238
 239 struct mac_receive_buffer {
 240         u16 next ;
 241         u8 padding ;
 242         u8 frame_status ;
 243         u16 buffer_length ;
 244         u8 frame_data ;
 245 };
 246
 247 struct olympic_private {
 248
 249         u16 srb;      /* be16 */
 250         u16 trb;      /* be16 */
 251         u16 arb;      /* be16 */
 252         u16 asb;      /* be16 */
 253
 254         u8 __iomem *olympic_mmio;
 255         u8 __iomem *olympic_lap;
 256         struct pci_dev *pdev ;
 257         char *olympic_card_name ;
 258
 259         spinlock_t olympic_lock ;
 260
 261         volatile int srb_queued;    /* True if an SRB is still posted */
 262         wait_queue_head_t srb_wait;
 263
 264         volatile int asb_queued;    /* True if an ASB is posted */
 265
 266         volatile int trb_queued;   /* True if a TRB is posted */
 267         wait_queue_head_t trb_wait ;
 268
 269         /* These must be on a 4 byte boundary. */
 270         struct olympic_rx_desc olympic_rx_ring[OLYMPIC_RX_RING_SIZE];
 271         struct olympic_tx_desc olympic_tx_ring[OLYMPIC_TX_RING_SIZE];
 272         struct olympic_rx_status olympic_rx_status_ring[OLYMPIC_RX_RING_SIZE];
 273         struct olympic_tx_status olympic_tx_status_ring[OLYMPIC_TX_RING_SIZE];
 274
 275         struct sk_buff *tx_ring_skb[OLYMPIC_TX_RING_SIZE], *rx_ring_skb[OLYMPIC_RX_RING_SIZE];
 276         int tx_ring_free, tx_ring_last_status, rx_ring_last_received,rx_status_last_received, free_tx_ring_entries;
 277
 278         struct net_device_stats olympic_stats ;
 279         u16 olympic_lan_status ;
 280         u8 olympic_ring_speed ;
 281         u16 pkt_buf_sz ;
 282         u8 olympic_receive_options, olympic_copy_all_options,olympic_message_level, olympic_network_monitor;
 283         u16 olympic_addr_table_addr, olympic_parms_addr ;
 284         u8 olympic_laa[6] ;
 285         u32 rx_ring_dma_addr;
 286         u32 rx_status_ring_dma_addr;
 287         u32 tx_ring_dma_addr;
 288         u32 tx_status_ring_dma_addr;
 289 };
 290
 291 struct olympic_adapter_addr_table {
 292
 293         u8 node_addr[6] ;
 294         u8 reserved[4] ;
 295         u8 func_addr[4] ;
 296 } ;
 297
 298 struct olympic_parameters_table {
 299
 300         u8  phys_addr[4] ;
 301         u8  up_node_addr[6] ;
 302         u8  up_phys_addr[4] ;
 303         u8  poll_addr[6] ;
 304         u16 reserved ;
 305         u16 acc_priority ;
 306         u16 auth_source_class ;
 307         u16 att_code ;
 308         u8  source_addr[6] ;
 309         u16 beacon_type ;
 310         u16 major_vector ;
 311         u16 lan_status ;
 312         u16 soft_error_time ;
 313         u16 reserved1 ;
 314         u16 local_ring ;
 315         u16 mon_error ;
 316         u16 beacon_transmit ;
 317         u16 beacon_receive ;
 318         u16 frame_correl ;
 319         u8  beacon_naun[6] ;
 320         u32 reserved2 ;
 321         u8  beacon_phys[4] ;
 322 };