drivers/video/savage/savagefb.h

   1 /*
   2  * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
   3  *
   4  * Copyright (c) 2001  Denis Oliver Kropp <dok@convergence.de>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General
   7  * Public License.  See the file COPYING in the main directory of this
   8  * archive for more details.
   9  */
  10
  11
  12 #ifndef __SAVAGEFB_H__
  13 #define __SAVAGEFB_H__
  14
  15 #include <linux/i2c.h>
  16 #include <linux/i2c-id.h>
  17 #include <linux/i2c-algo-bit.h>
  18 #include <linux/mutex.h>
  19 #include <video/vga.h>
  20 #include "../edid.h"
  21
  22 #ifdef SAVAGEFB_DEBUG
  23 # define DBG(x)         printk (KERN_DEBUG "savagefb: %s\n", (x));
  24 #else
  25 # define DBG(x)
  26 # define SavagePrintRegs(...)
  27 #endif
  28
  29
  30 #define PCI_CHIP_SAVAGE4      0x8a22
  31 #define PCI_CHIP_SAVAGE3D     0x8a20
  32 #define PCI_CHIP_SAVAGE3D_MV  0x8a21
  33 #define PCI_CHIP_SAVAGE2000   0x9102
  34 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
  35 #define PCI_CHIP_SAVAGE_MX    0x8c11
  36 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
  37 #define PCI_CHIP_SAVAGE_IX    0x8c13
  38 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
  39 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
  40  /* Twister is a code name; hope I get the real name soon. */
  41 #define PCI_CHIP_S3TWISTER_P  0x8d01
  42 #define PCI_CHIP_S3TWISTER_K  0x8d02
  43 #define PCI_CHIP_PROSAVAGE_DDR          0x8d03
  44 #define PCI_CHIP_PROSAVAGE_DDRK         0x8d04
  45 #define PCI_CHIP_SUPSAV_MX128           0x8c22
  46 #define PCI_CHIP_SUPSAV_MX64            0x8c24
  47 #define PCI_CHIP_SUPSAV_MX64C           0x8c26
  48 #define PCI_CHIP_SUPSAV_IX128SDR        0x8c2a
  49 #define PCI_CHIP_SUPSAV_IX128DDR        0x8c2b
  50 #define PCI_CHIP_SUPSAV_IX64SDR         0x8c2c
  51 #define PCI_CHIP_SUPSAV_IX64DDR         0x8c2d
  52 #define PCI_CHIP_SUPSAV_IXCSDR          0x8c2e
  53 #define PCI_CHIP_SUPSAV_IXCDDR          0x8c2f
  54
  55
  56
  57 #define S3_SAVAGE3D_SERIES(chip)  ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
  58
  59 #define S3_SAVAGE4_SERIES(chip)   ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
  60
  61 #define S3_SAVAGE_MOBILE_SERIES(chip)  ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
  62
  63 #define S3_SAVAGE_SERIES(chip)    ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
  64
  65 /* Chip tags.  These are used to group the adapters into
  66  * related families.
  67  */
  68
  69 typedef enum {
  70   S3_UNKNOWN = 0,
  71   S3_SAVAGE3D,
  72   S3_SAVAGE_MX,
  73   S3_SAVAGE4,
  74   S3_PROSAVAGE,
  75   S3_SUPERSAVAGE,
  76   S3_SAVAGE2000,
  77   S3_LAST
  78 } savage_chipset;
  79
  80 #define BIOS_BSIZE                   1024
  81 #define BIOS_BASE                    0xc0000
  82
  83 #define SAVAGE_NEWMMIO_REGBASE_S3    0x1000000  /* 16MB */
  84 #define SAVAGE_NEWMMIO_REGBASE_S4    0x0000000
  85 #define SAVAGE_NEWMMIO_REGSIZE       0x0080000  /* 512kb */
  86 #define SAVAGE_NEWMMIO_VGABASE       0x8000
  87
  88 #define BASE_FREQ                    14318
  89 #define HALF_BASE_FREQ               7159
  90
  91 #define FIFO_CONTROL_REG             0x8200
  92 #define MIU_CONTROL_REG              0x8204
  93 #define STREAMS_TIMEOUT_REG          0x8208
  94 #define MISC_TIMEOUT_REG             0x820c
  95
  96 #define MONO_PAT_0                   0xa4e8
  97 #define MONO_PAT_1                   0xa4ec
  98
  99 #define MAXFIFO                      0x7f00
 100
 101 #define BCI_CMD_NOP                  0x40000000
 102 #define BCI_CMD_SETREG               0x96000000
 103 #define BCI_CMD_RECT                 0x48000000
 104 #define BCI_CMD_RECT_XP              0x01000000
 105 #define BCI_CMD_RECT_YP              0x02000000
 106 #define BCI_CMD_SEND_COLOR           0x00008000
 107 #define BCI_CMD_DEST_GBD             0x00000000
 108 #define BCI_CMD_SRC_GBD              0x00000020
 109 #define BCI_CMD_SRC_SOLID            0x00000000
 110 #define BCI_CMD_SRC_MONO             0x00000060
 111 #define BCI_CMD_CLIP_NEW             0x00006000
 112 #define BCI_CMD_CLIP_LR              0x00004000
 113
 114 #define BCI_CLIP_LR(l, r)            ((((r) << 16) | (l)) & 0x0FFF0FFF)
 115 #define BCI_CLIP_TL(t, l)            ((((t) << 16) | (l)) & 0x0FFF0FFF)
 116 #define BCI_CLIP_BR(b, r)            ((((b) << 16) | (r)) & 0x0FFF0FFF)
 117 #define BCI_W_H(w, h)                (((h) << 16) | ((w) & 0xFFF))
 118 #define BCI_X_Y(x, y)                (((y) << 16) | ((x) & 0xFFF))
 119
 120 #define BCI_GBD1                     0xE0
 121 #define BCI_GBD2                     0xE1
 122
 123 #define BCI_BUFFER_OFFSET            0x10000
 124 #define BCI_SIZE                     0x4000
 125
 126 #define BCI_SEND(dw)                 writel(dw, par->bci_base + par->bci_ptr++)
 127
 128 #define BCI_CMD_GET_ROP(cmd)         (((cmd) >> 16) & 0xFF)
 129 #define BCI_CMD_SET_ROP(cmd, rop)    ((cmd) |= ((rop & 0xFF) << 16))
 130 #define BCI_CMD_SEND_COLOR           0x00008000
 131
 132 #define DISP_CRT     1
 133 #define DISP_LCD     2
 134 #define DISP_DFP     3
 135
 136 struct xtimings {
 137         unsigned int Clock;
 138         unsigned int HDisplay;
 139         unsigned int HSyncStart;
 140         unsigned int HSyncEnd;
 141         unsigned int HTotal;
 142         unsigned int HAdjusted;
 143         unsigned int VDisplay;
 144         unsigned int VSyncStart;
 145         unsigned int VSyncEnd;
 146         unsigned int VTotal;
 147         unsigned int sync;
 148         int            dblscan;
 149         int            interlaced;
 150 };
 151
 152 struct savage_reg {
 153         unsigned char MiscOutReg;     /* Misc */
 154         unsigned char CRTC[25];       /* Crtc Controller */
 155         unsigned char Sequencer[5];   /* Video Sequencer */
 156         unsigned char Graphics[9];    /* Video Graphics */
 157         unsigned char Attribute[21];  /* Video Atribute */
 158
 159         unsigned int mode, refresh;
 160         unsigned char SR08, SR0E, SR0F;
 161         unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
 162         unsigned char SR54[8];
 163         unsigned char Clock;
 164         unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
 165         unsigned char CR40, CR41, CR42, CR43, CR45;
 166         unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
 167         unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
 168         unsigned char CR86, CR88;
 169         unsigned char CR90, CR91, CRB0;
 170         unsigned int  STREAMS[22];      /* yuck, streams regs */
 171         unsigned int  MMPR0, MMPR1, MMPR2, MMPR3;
 172 };
 173 /* --------------------------------------------------------------------- */
 174
 175 #define NR_PALETTE      256
 176
 177
 178 struct savagefb_par;
 179
 180 struct savagefb_i2c_chan {
 181         struct savagefb_par *par;
 182         struct i2c_adapter adapter;
 183         struct i2c_algo_bit_data algo;
 184         volatile u8 __iomem *ioaddr;
 185         u32   reg;
 186 };
 187
 188 struct savagefb_par {
 189         struct pci_dev *pcidev;
 190         savage_chipset  chip;
 191         struct savagefb_i2c_chan chan;
 192         struct savage_reg state;
 193         struct savage_reg save;
 194         struct savage_reg initial;
 195         struct vgastate vgastate;
 196         struct mutex open_lock;
 197         unsigned char   *edid;
 198         u32 pseudo_palette[16];
 199         u32 open_count;
 200         int paletteEnabled;
 201         int pm_state;
 202         int display_type;
 203         int dvi;
 204         int crtonly;
 205         int dacSpeedBpp;
 206         int maxClock;
 207         int minClock;
 208         int numClocks;
 209         int clock[4];
 210         int MCLK, REFCLK, LCDclk;
 211         struct {
 212                 void   __iomem *vbase;
 213                 u32    pbase;
 214                 u32    len;
 215 #ifdef CONFIG_MTRR
 216                 int    mtrr;
 217 #endif
 218         } video;
 219
 220         struct {
 221                 void  __iomem *vbase;
 222                 u32           pbase;
 223                 u32           len;
 224         } mmio;
 225
 226         volatile u32  __iomem *bci_base;
 227         unsigned int  bci_ptr;
 228         u32           cob_offset;
 229         u32           cob_size;
 230         int           cob_index;
 231
 232         void (*SavageWaitIdle) (struct savagefb_par *par);
 233         void (*SavageWaitFifo) (struct savagefb_par *par, int space);
 234
 235         int HorizScaleFactor;
 236
 237         /* Panels size */
 238         int SavagePanelWidth;
 239         int SavagePanelHeight;
 240
 241         struct {
 242                 u16 red, green, blue, transp;
 243         } palette[NR_PALETTE];
 244
 245         int depth;
 246         int vwidth;
 247 };
 248
 249 #define BCI_BD_BW_DISABLE            0x10000000
 250 #define BCI_BD_SET_BPP(bd, bpp)      ((bd) |= (((bpp) & 0xFF) << 16))
 251 #define BCI_BD_SET_STRIDE(bd, st)    ((bd) |= ((st) & 0xFFFF))
 252
 253
 254 /* IO functions */
 255 static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
 256 {
 257         return readb(par->mmio.vbase + addr);
 258 }
 259
 260 static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
 261 {
 262         return readw(par->mmio.vbase + addr);
 263 }
 264
 265 static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
 266 {
 267         return readl(par->mmio.vbase + addr);
 268 }
 269
 270 static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
 271 {
 272         writeb(val, par->mmio.vbase + addr);
 273 }
 274
 275 static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
 276 {
 277         writew(val, par->mmio.vbase + addr);
 278 }
 279
 280 static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
 281 {
 282         writel(val, par->mmio.vbase + addr);
 283 }
 284
 285 static inline u8 vga_in8(int addr, struct savagefb_par *par)
 286 {
 287         return savage_in8(0x8000 + addr, par);
 288 }
 289
 290 static inline u16 vga_in16(int addr, struct savagefb_par *par)
 291 {
 292         return savage_in16(0x8000 + addr, par);
 293 }
 294
 295 static inline u8 vga_in32(int addr, struct savagefb_par *par)
 296 {
 297         return savage_in32(0x8000 + addr, par);
 298 }
 299
 300 static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
 301 {
 302         savage_out8(0x8000 + addr, val, par);
 303 }
 304
 305 static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
 306 {
 307         savage_out16(0x8000 + addr, val, par);
 308 }
 309
 310 static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
 311 {
 312         savage_out32(0x8000 + addr, val, par);
 313 }
 314
 315 static inline u8 VGArCR (u8 index, struct savagefb_par *par)
 316 {
 317         vga_out8(0x3d4, index,  par);
 318         return vga_in8(0x3d5, par);
 319 }
 320
 321 static inline u8 VGArGR (u8 index, struct savagefb_par *par)
 322 {
 323         vga_out8(0x3ce, index, par);
 324         return vga_in8(0x3cf, par);
 325 }
 326
 327 static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
 328 {
 329         vga_out8(0x3c4, index, par);
 330         return vga_in8(0x3c5, par);
 331 }
 332
 333 static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
 334 {
 335         vga_out8(0x3d4, index, par);
 336         vga_out8(0x3d5, val, par);
 337 }
 338
 339 static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
 340 {
 341         vga_out8(0x3ce, index, par);
 342         vga_out8(0x3cf, val, par);
 343 }
 344
 345 static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
 346 {
 347         vga_out8(0x3c4, index, par);
 348         vga_out8 (0x3c5, val, par);
 349 }
 350
 351 static inline void VGAenablePalette(struct savagefb_par *par)
 352 {
 353         u8 tmp;
 354
 355         tmp = vga_in8(0x3da, par);
 356         vga_out8(0x3c0, 0x00, par);
 357         par->paletteEnabled = 1;
 358 }
 359
 360 static inline void VGAdisablePalette(struct savagefb_par *par)
 361 {
 362         u8 tmp;
 363
 364         tmp = vga_in8(0x3da, par);
 365         vga_out8(0x3c0, 0x20, par);
 366         par->paletteEnabled = 0;
 367 }
 368
 369 static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
 370 {
 371         u8 tmp;
 372
 373         if (par->paletteEnabled)
 374                 index &= ~0x20;
 375         else
 376                 index |= 0x20;
 377
 378         tmp = vga_in8(0x3da, par);
 379         vga_out8(0x3c0, index, par);
 380         vga_out8 (0x3c0, value, par);
 381 }
 382
 383 static inline void VGAwMISC(u8 value, struct savagefb_par *par)
 384 {
 385         vga_out8(0x3c2, value, par);
 386 }
 387
 388 #ifndef CONFIG_FB_SAVAGE_ACCEL
 389 #define savagefb_set_clip(x)
 390 #endif
 391
 392 static inline void VerticalRetraceWait(struct savagefb_par *par)
 393 {
 394         vga_out8(0x3d4, 0x17, par);
 395         if (vga_in8(0x3d5, par) & 0x80) {
 396                 while ((vga_in8(0x3da, par) & 0x08) == 0x08);
 397                 while ((vga_in8(0x3da, par) & 0x08) == 0x00);
 398         }
 399 }
 400
 401 extern int savagefb_probe_i2c_connector(struct fb_info *info,
 402                                         u8 **out_edid);
 403 extern void savagefb_create_i2c_busses(struct fb_info *info);
 404 extern void savagefb_delete_i2c_busses(struct fb_info *info);
 405 extern int  savagefb_sync(struct fb_info *info);
 406 extern void savagefb_copyarea(struct fb_info *info,
 407                               const struct fb_copyarea *region);
 408 extern void savagefb_fillrect(struct fb_info *info,
 409                               const struct fb_fillrect *rect);
 410 extern void savagefb_imageblit(struct fb_info *info,
 411                                const struct fb_image *image);
 412
 413
 414 #endif /* __SAVAGEFB_H__ */