?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[NET] drivers/net: statistics cleanup #1 -- save memory and shrink code
[pv_ops_mirror.git] / drivers / net / pci-skeleton.c
blob7dace63fb6e66f2479256bd30d28513073771e63
1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #include <linux/module.h>
89 #include <linux/kernel.h>
90 #include <linux/pci.h>
91 #include <linux/init.h>
92 #include <linux/ioport.h>
93 #include <linux/netdevice.h>
94 #include <linux/etherdevice.h>
95 #include <linux/delay.h>
96 #include <linux/ethtool.h>
97 #include <linux/mii.h>
98 #include <linux/crc32.h>
99 #include <asm/io.h>
100
101 #define NETDRV_VERSION "1.0.1"
102 #define MODNAME "netdrv"
103 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
104 #define PFX MODNAME ": "
105
106 static char version[] __devinitdata =
107 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
108 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
109
110 /* define to 1 to enable PIO instead of MMIO */
111 #undef USE_IO_OPS
112
113 /* define to 1 to enable copious debugging info */
114 #undef NETDRV_DEBUG
115
116 /* define to 1 to disable lightweight runtime debugging checks */
117 #undef NETDRV_NDEBUG
118
119
120 #ifdef NETDRV_DEBUG
121 /* note: prints function name for you */
122 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
123 #else
124 # define DPRINTK(fmt, args...)
125 #endif
126
127 #ifdef NETDRV_NDEBUG
128 # define assert(expr) do {} while (0)
129 #else
130 # define assert(expr) \
131 if(!(expr)) { \
132 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
133 #expr,__FILE__,__FUNCTION__,__LINE__); \
134 }
135 #endif
136
137
138 /* A few user-configurable values. */
139 /* media options */
140 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
141
142 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
143 static int max_interrupt_work = 20;
144
145 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
146 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
147 static int multicast_filter_limit = 32;
148
149 /* Size of the in-memory receive ring. */
150 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
151 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
152 #define RX_BUF_PAD 16
153 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
154 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
155
156 /* Number of Tx descriptor registers. */
157 #define NUM_TX_DESC 4
158
159 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
160 #define MAX_ETH_FRAME_SIZE 1536
161
162 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
163 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
164 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
165
166 /* PCI Tuning Parameters
167 Threshold is bytes transferred to chip before transmission starts. */
168 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
169
170 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
171 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
172 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
173 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174
175
176 /* Operational parameters that usually are not changed. */
177 /* Time in jiffies before concluding the transmitter is hung. */
178 #define TX_TIMEOUT (6*HZ)
179
180
181 enum {
182 HAS_CHIP_XCVR = 0x020000,
183 HAS_LNK_CHNG = 0x040000,
184 };
185
186 #define NETDRV_MIN_IO_SIZE 0x80
187 #define RTL8139B_IO_SIZE 256
188
189 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
190
191 typedef enum {
192 RTL8139 = 0,
193 NETDRV_CB,
194 SMC1211TX,
195 /*MPX5030,*/
196 DELTA8139,
197 ADDTRON8139,
198 } board_t;
199
200
201 /* indexed by board_t, above */
202 static struct {
203 const char *name;
204 } board_info[] __devinitdata = {
205 { "RealTek RTL8139 Fast Ethernet" },
206 { "RealTek RTL8139B PCI/CardBus" },
207 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
208 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
209 { "Delta Electronics 8139 10/100BaseTX" },
210 { "Addtron Technolgy 8139 10/100BaseTX" },
211 };
212
213
214 static struct pci_device_id netdrv_pci_tbl[] = {
215 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
216 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
217 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
218 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
219 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
220 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
221 {0,}
222 };
223 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
224
225
226 /* The rest of these values should never change. */
227
228 /* Symbolic offsets to registers. */
229 enum NETDRV_registers {
230 MAC0 = 0, /* Ethernet hardware address. */
231 MAR0 = 8, /* Multicast filter. */
232 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
233 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
234 RxBuf = 0x30,
235 RxEarlyCnt = 0x34,
236 RxEarlyStatus = 0x36,
237 ChipCmd = 0x37,
238 RxBufPtr = 0x38,
239 RxBufAddr = 0x3A,
240 IntrMask = 0x3C,
241 IntrStatus = 0x3E,
242 TxConfig = 0x40,
243 ChipVersion = 0x43,
244 RxConfig = 0x44,
245 Timer = 0x48, /* A general-purpose counter. */
246 RxMissed = 0x4C, /* 24 bits valid, write clears. */
247 Cfg9346 = 0x50,
248 Config0 = 0x51,
249 Config1 = 0x52,
250 FlashReg = 0x54,
251 MediaStatus = 0x58,
252 Config3 = 0x59,
253 Config4 = 0x5A, /* absent on RTL-8139A */
254 HltClk = 0x5B,
255 MultiIntr = 0x5C,
256 TxSummary = 0x60,
257 BasicModeCtrl = 0x62,
258 BasicModeStatus = 0x64,
259 NWayAdvert = 0x66,
260 NWayLPAR = 0x68,
261 NWayExpansion = 0x6A,
262 /* Undocumented registers, but required for proper operation. */
263 FIFOTMS = 0x70, /* FIFO Control and test. */
264 CSCR = 0x74, /* Chip Status and Configuration Register. */
265 PARA78 = 0x78,
266 PARA7c = 0x7c, /* Magic transceiver parameter register. */
267 Config5 = 0xD8, /* absent on RTL-8139A */
268 };
269
270 enum ClearBitMasks {
271 MultiIntrClear = 0xF000,
272 ChipCmdClear = 0xE2,
273 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
274 };
275
276 enum ChipCmdBits {
277 CmdReset = 0x10,
278 CmdRxEnb = 0x08,
279 CmdTxEnb = 0x04,
280 RxBufEmpty = 0x01,
281 };
282
283 /* Interrupt register bits, using my own meaningful names. */
284 enum IntrStatusBits {
285 PCIErr = 0x8000,
286 PCSTimeout = 0x4000,
287 RxFIFOOver = 0x40,
288 RxUnderrun = 0x20,
289 RxOverflow = 0x10,
290 TxErr = 0x08,
291 TxOK = 0x04,
292 RxErr = 0x02,
293 RxOK = 0x01,
294 };
295 enum TxStatusBits {
296 TxHostOwns = 0x2000,
297 TxUnderrun = 0x4000,
298 TxStatOK = 0x8000,
299 TxOutOfWindow = 0x20000000,
300 TxAborted = 0x40000000,
301 TxCarrierLost = 0x80000000,
302 };
303 enum RxStatusBits {
304 RxMulticast = 0x8000,
305 RxPhysical = 0x4000,
306 RxBroadcast = 0x2000,
307 RxBadSymbol = 0x0020,
308 RxRunt = 0x0010,
309 RxTooLong = 0x0008,
310 RxCRCErr = 0x0004,
311 RxBadAlign = 0x0002,
312 RxStatusOK = 0x0001,
313 };
314
315 /* Bits in RxConfig. */
316 enum rx_mode_bits {
317 AcceptErr = 0x20,
318 AcceptRunt = 0x10,
319 AcceptBroadcast = 0x08,
320 AcceptMulticast = 0x04,
321 AcceptMyPhys = 0x02,
322 AcceptAllPhys = 0x01,
323 };
324
325 /* Bits in TxConfig. */
326 enum tx_config_bits {
327 TxIFG1 = (1 << 25), /* Interframe Gap Time */
328 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
329 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
330 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
331 TxClearAbt = (1 << 0), /* Clear abort (WO) */
332 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
333
334 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
335 };
336
337 /* Bits in Config1 */
338 enum Config1Bits {
339 Cfg1_PM_Enable = 0x01,
340 Cfg1_VPD_Enable = 0x02,
341 Cfg1_PIO = 0x04,
342 Cfg1_MMIO = 0x08,
343 Cfg1_LWAKE = 0x10,
344 Cfg1_Driver_Load = 0x20,
345 Cfg1_LED0 = 0x40,
346 Cfg1_LED1 = 0x80,
347 };
348
349 enum RxConfigBits {
350 /* Early Rx threshold, none or X/16 */
351 RxCfgEarlyRxNone = 0,
352 RxCfgEarlyRxShift = 24,
353
354 /* rx fifo threshold */
355 RxCfgFIFOShift = 13,
356 RxCfgFIFONone = (7 << RxCfgFIFOShift),
357
358 /* Max DMA burst */
359 RxCfgDMAShift = 8,
360 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
361
362 /* rx ring buffer length */
363 RxCfgRcv8K = 0,
364 RxCfgRcv16K = (1 << 11),
365 RxCfgRcv32K = (1 << 12),
366 RxCfgRcv64K = (1 << 11) | (1 << 12),
367
368 /* Disable packet wrap at end of Rx buffer */
369 RxNoWrap = (1 << 7),
370 };
371
372
373 /* Twister tuning parameters from RealTek.
374 Completely undocumented, but required to tune bad links. */
375 enum CSCRBits {
376 CSCR_LinkOKBit = 0x0400,
377 CSCR_LinkChangeBit = 0x0800,
378 CSCR_LinkStatusBits = 0x0f000,
379 CSCR_LinkDownOffCmd = 0x003c0,
380 CSCR_LinkDownCmd = 0x0f3c0,
381 };
382
383
384 enum Cfg9346Bits {
385 Cfg9346_Lock = 0x00,
386 Cfg9346_Unlock = 0xC0,
387 };
388
389
390 #define PARA78_default 0x78fa8388
391 #define PARA7c_default 0xcb38de43 /* param[0][3] */
392 #define PARA7c_xxx 0xcb38de43
393 static const unsigned long param[4][4] = {
394 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
395 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
398 };
399
400 struct ring_info {
401 struct sk_buff *skb;
402 dma_addr_t mapping;
403 };
404
405
406 typedef enum {
407 CH_8139 = 0,
408 CH_8139_K,
409 CH_8139A,
410 CH_8139B,
411 CH_8130,
412 CH_8139C,
413 } chip_t;
414
415
416 /* directly indexed by chip_t, above */
417 static const struct {
418 const char *name;
419 u8 version; /* from RTL8139C docs */
420 u32 RxConfigMask; /* should clear the bits supported by this chip */
421 } rtl_chip_info[] = {
422 { "RTL-8139",
423 0x40,
424 0xf0fe0040, /* XXX copied from RTL8139A, verify */
425 },
426
427 { "RTL-8139 rev K",
428 0x60,
429 0xf0fe0040,
430 },
431
432 { "RTL-8139A",
433 0x70,
434 0xf0fe0040,
435 },
436
437 { "RTL-8139B",
438 0x78,
439 0xf0fc0040
440 },
441
442 { "RTL-8130",
443 0x7C,
444 0xf0fe0040, /* XXX copied from RTL8139A, verify */
445 },
446
447 { "RTL-8139C",
448 0x74,
449 0xf0fc0040, /* XXX copied from RTL8139B, verify */
450 },
451
452 };
453
454
455 struct netdrv_private {
456 board_t board;
457 void *mmio_addr;
458 int drv_flags;
459 struct pci_dev *pci_dev;
460 struct timer_list timer; /* Media selection timer. */
461 unsigned char *rx_ring;
462 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
463 unsigned int tx_flag;
464 atomic_t cur_tx;
465 atomic_t dirty_tx;
466 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
467 struct ring_info tx_info[NUM_TX_DESC];
468 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
469 unsigned char *tx_bufs; /* Tx bounce buffer region. */
470 dma_addr_t rx_ring_dma;
471 dma_addr_t tx_bufs_dma;
472 char phys[4]; /* MII device addresses. */
473 char twistie, twist_row, twist_col; /* Twister tune state. */
474 unsigned int full_duplex:1; /* Full-duplex operation requested. */
475 unsigned int duplex_lock:1;
476 unsigned int default_port:4; /* Last dev->if_port value. */
477 unsigned int media2:4; /* Secondary monitored media port. */
478 unsigned int medialock:1; /* Don't sense media type. */
479 unsigned int mediasense:1; /* Media sensing in progress. */
480 spinlock_t lock;
481 chip_t chipset;
482 };
483
484 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
485 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
486 MODULE_LICENSE("GPL");
487 module_param(multicast_filter_limit, int, 0);
488 module_param(max_interrupt_work, int, 0);
489 module_param_array(media, int, NULL, 0);
490 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
491 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
492 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
493
494 static int read_eeprom (void *ioaddr, int location, int addr_len);
495 static int netdrv_open (struct net_device *dev);
496 static int mdio_read (struct net_device *dev, int phy_id, int location);
497 static void mdio_write (struct net_device *dev, int phy_id, int location,
498 int val);
499 static void netdrv_timer (unsigned long data);
500 static void netdrv_tx_timeout (struct net_device *dev);
501 static void netdrv_init_ring (struct net_device *dev);
502 static int netdrv_start_xmit (struct sk_buff *skb,
503 struct net_device *dev);
504 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance);
505 static int netdrv_close (struct net_device *dev);
506 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
507 static void netdrv_set_rx_mode (struct net_device *dev);
508 static void netdrv_hw_start (struct net_device *dev);
509
510
511 #ifdef USE_IO_OPS
512
513 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
514 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
515 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
516 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
517 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
518 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
519 #define NETDRV_W8_F NETDRV_W8
520 #define NETDRV_W16_F NETDRV_W16
521 #define NETDRV_W32_F NETDRV_W32
522 #undef readb
523 #undef readw
524 #undef readl
525 #undef writeb
526 #undef writew
527 #undef writel
528 #define readb(addr) inb((unsigned long)(addr))
529 #define readw(addr) inw((unsigned long)(addr))
530 #define readl(addr) inl((unsigned long)(addr))
531 #define writeb(val,addr) outb((val),(unsigned long)(addr))
532 #define writew(val,addr) outw((val),(unsigned long)(addr))
533 #define writel(val,addr) outl((val),(unsigned long)(addr))
534
535 #else
536
537 /* write MMIO register, with flush */
538 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
539 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
540 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
541 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
542
543
544 #if MMIO_FLUSH_AUDIT_COMPLETE
545
546 /* write MMIO register */
547 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
548 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
549 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
550
551 #else
552
553 /* write MMIO register, then flush */
554 #define NETDRV_W8 NETDRV_W8_F
555 #define NETDRV_W16 NETDRV_W16_F
556 #define NETDRV_W32 NETDRV_W32_F
557
558 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
559
560 /* read MMIO register */
561 #define NETDRV_R8(reg) readb (ioaddr + (reg))
562 #define NETDRV_R16(reg) readw (ioaddr + (reg))
563 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
564
565 #endif /* USE_IO_OPS */
566
567
568 static const u16 netdrv_intr_mask =
569 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
570 TxErr | TxOK | RxErr | RxOK;
571
572 static const unsigned int netdrv_rx_config =
573 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
574 (RX_FIFO_THRESH << RxCfgFIFOShift) |
575 (RX_DMA_BURST << RxCfgDMAShift);
576
577
578 static int __devinit netdrv_init_board (struct pci_dev *pdev,
579 struct net_device **dev_out,
580 void **ioaddr_out)
581 {
582 void *ioaddr = NULL;
583 struct net_device *dev;
584 struct netdrv_private *tp;
585 int rc, i;
586 u32 pio_start, pio_end, pio_flags, pio_len;
587 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
588 u32 tmp;
589
590 DPRINTK ("ENTER\n");
591
592 assert (pdev != NULL);
593 assert (ioaddr_out != NULL);
594
595 *ioaddr_out = NULL;
596 *dev_out = NULL;
597
598 /* dev zeroed in alloc_etherdev */
599 dev = alloc_etherdev (sizeof (*tp));
600 if (dev == NULL) {
601 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
602 DPRINTK ("EXIT, returning -ENOMEM\n");
603 return -ENOMEM;
604 }
605 SET_NETDEV_DEV(dev, &pdev->dev);
606 tp = dev->priv;
607
608 /* enable device (incl. PCI PM wakeup), and bus-mastering */
609 rc = pci_enable_device (pdev);
610 if (rc)
611 goto err_out;
612
613 pio_start = pci_resource_start (pdev, 0);
614 pio_end = pci_resource_end (pdev, 0);
615 pio_flags = pci_resource_flags (pdev, 0);
616 pio_len = pci_resource_len (pdev, 0);
617
618 mmio_start = pci_resource_start (pdev, 1);
619 mmio_end = pci_resource_end (pdev, 1);
620 mmio_flags = pci_resource_flags (pdev, 1);
621 mmio_len = pci_resource_len (pdev, 1);
622
623 /* set this immediately, we need to know before
624 * we talk to the chip directly */
625 DPRINTK("PIO region size == 0x%02X\n", pio_len);
626 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
627
628 /* make sure PCI base addr 0 is PIO */
629 if (!(pio_flags & IORESOURCE_IO)) {
630 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
631 rc = -ENODEV;
632 goto err_out;
633 }
634
635 /* make sure PCI base addr 1 is MMIO */
636 if (!(mmio_flags & IORESOURCE_MEM)) {
637 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
638 rc = -ENODEV;
639 goto err_out;
640 }
641
642 /* check for weird/broken PCI region reporting */
643 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
644 (mmio_len < NETDRV_MIN_IO_SIZE)) {
645 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
646 rc = -ENODEV;
647 goto err_out;
648 }
649
650 rc = pci_request_regions (pdev, MODNAME);
651 if (rc)
652 goto err_out;
653
654 pci_set_master (pdev);
655
656 #ifdef USE_IO_OPS
657 ioaddr = (void *) pio_start;
658 #else
659 /* ioremap MMIO region */
660 ioaddr = ioremap (mmio_start, mmio_len);
661 if (ioaddr == NULL) {
662 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
663 rc = -EIO;
664 goto err_out_free_res;
665 }
666 #endif /* USE_IO_OPS */
667
668 /* Soft reset the chip. */
669 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
670
671 /* Check that the chip has finished the reset. */
672 for (i = 1000; i > 0; i--)
673 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
674 break;
675 else
676 udelay (10);
677
678 /* Bring the chip out of low-power mode. */
679 /* <insert device-specific code here> */
680
681 #ifndef USE_IO_OPS
682 /* sanity checks -- ensure PIO and MMIO registers agree */
683 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
684 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
685 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
686 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
687 #endif /* !USE_IO_OPS */
688
689 /* identify chip attached to board */
690 tmp = NETDRV_R8 (ChipVersion);
691 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
692 if (tmp == rtl_chip_info[i].version) {
693 tp->chipset = i;
694 goto match;
695 }
696
697 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
698 dev_printk (KERN_DEBUG, &pdev->dev,
699 "unknown chip version, assuming RTL-8139\n");
700 dev_printk (KERN_DEBUG, &pdev->dev, "TxConfig = 0x%lx\n",
701 NETDRV_R32 (TxConfig));
702 tp->chipset = 0;
703
704 match:
705 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
706 tmp,
707 tp->chipset,
708 rtl_chip_info[tp->chipset].name);
709
710 rc = register_netdev (dev);
711 if (rc)
712 goto err_out_unmap;
713
714 DPRINTK ("EXIT, returning 0\n");
715 *ioaddr_out = ioaddr;
716 *dev_out = dev;
717 return 0;
718
719 err_out_unmap:
720 #ifndef USE_IO_OPS
721 iounmap(ioaddr);
722 err_out_free_res:
723 #endif
724 pci_release_regions (pdev);
725 err_out:
726 free_netdev (dev);
727 DPRINTK ("EXIT, returning %d\n", rc);
728 return rc;
729 }
730
731
732 static int __devinit netdrv_init_one (struct pci_dev *pdev,
733 const struct pci_device_id *ent)
734 {
735 struct net_device *dev = NULL;
736 struct netdrv_private *tp;
737 int i, addr_len, option;
738 void *ioaddr = NULL;
739 static int board_idx = -1;
740
741 /* when built into the kernel, we only print version if device is found */
742 #ifndef MODULE
743 static int printed_version;
744 if (!printed_version++)
745 printk(version);
746 #endif
747
748 DPRINTK ("ENTER\n");
749
750 assert (pdev != NULL);
751 assert (ent != NULL);
752
753 board_idx++;
754
755 i = netdrv_init_board (pdev, &dev, &ioaddr);
756 if (i < 0) {
757 DPRINTK ("EXIT, returning %d\n", i);
758 return i;
759 }
760
761 tp = dev->priv;
762
763 assert (ioaddr != NULL);
764 assert (dev != NULL);
765 assert (tp != NULL);
766
767 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
768 for (i = 0; i < 3; i++)
769 ((u16 *) (dev->dev_addr))[i] =
770 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
771
772 /* The Rtl8139-specific entries in the device structure. */
773 dev->open = netdrv_open;
774 dev->hard_start_xmit = netdrv_start_xmit;
775 dev->stop = netdrv_close;
776 dev->set_multicast_list = netdrv_set_rx_mode;
777 dev->do_ioctl = netdrv_ioctl;
778 dev->tx_timeout = netdrv_tx_timeout;
779 dev->watchdog_timeo = TX_TIMEOUT;
780
781 dev->irq = pdev->irq;
782 dev->base_addr = (unsigned long) ioaddr;
783
784 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
785 tp = dev->priv;
786
787 /* note: tp->chipset set in netdrv_init_board */
788 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
789 PCI_COMMAND_MASTER | NETDRV_CAPS;
790 tp->pci_dev = pdev;
791 tp->board = ent->driver_data;
792 tp->mmio_addr = ioaddr;
793 spin_lock_init(&tp->lock);
794
795 pci_set_drvdata(pdev, dev);
796
797 tp->phys[0] = 32;
798
799 printk (KERN_INFO "%s: %s at 0x%lx, "
800 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
801 "IRQ %d\n",
802 dev->name,
803 board_info[ent->driver_data].name,
804 dev->base_addr,
805 dev->dev_addr[0], dev->dev_addr[1],
806 dev->dev_addr[2], dev->dev_addr[3],
807 dev->dev_addr[4], dev->dev_addr[5],
808 dev->irq);
809
810 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
811 dev->name, rtl_chip_info[tp->chipset].name);
812
813 /* Put the chip into low-power mode. */
814 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
815
816 /* The lower four bits are the media type. */
817 option = (board_idx > 7) ? 0 : media[board_idx];
818 if (option > 0) {
819 tp->full_duplex = (option & 0x200) ? 1 : 0;
820 tp->default_port = option & 15;
821 if (tp->default_port)
822 tp->medialock = 1;
823 }
824
825 if (tp->full_duplex) {
826 printk (KERN_INFO
827 "%s: Media type forced to Full Duplex.\n",
828 dev->name);
829 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
830 tp->duplex_lock = 1;
831 }
832
833 DPRINTK ("EXIT - returning 0\n");
834 return 0;
835 }
836
837
838 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
839 {
840 struct net_device *dev = pci_get_drvdata (pdev);
841 struct netdrv_private *np;
842
843 DPRINTK ("ENTER\n");
844
845 assert (dev != NULL);
846
847 np = dev->priv;
848 assert (np != NULL);
849
850 unregister_netdev (dev);
851
852 #ifndef USE_IO_OPS
853 iounmap (np->mmio_addr);
854 #endif /* !USE_IO_OPS */
855
856 pci_release_regions (pdev);
857
858 free_netdev (dev);
859
860 pci_set_drvdata (pdev, NULL);
861
862 pci_disable_device (pdev);
863
864 DPRINTK ("EXIT\n");
865 }
866
867
868 /* Serial EEPROM section. */
869
870 /* EEPROM_Ctrl bits. */
871 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
872 #define EE_CS 0x08 /* EEPROM chip select. */
873 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
874 #define EE_WRITE_0 0x00
875 #define EE_WRITE_1 0x02
876 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
877 #define EE_ENB (0x80 | EE_CS)
878
879 /* Delay between EEPROM clock transitions.
880 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
881 */
882
883 #define eeprom_delay() readl(ee_addr)
884
885 /* The EEPROM commands include the alway-set leading bit. */
886 #define EE_WRITE_CMD (5)
887 #define EE_READ_CMD (6)
888 #define EE_ERASE_CMD (7)
889
890 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
891 {
892 int i;
893 unsigned retval = 0;
894 void *ee_addr = ioaddr + Cfg9346;
895 int read_cmd = location | (EE_READ_CMD << addr_len);
896
897 DPRINTK ("ENTER\n");
898
899 writeb (EE_ENB & ~EE_CS, ee_addr);
900 writeb (EE_ENB, ee_addr);
901 eeprom_delay ();
902
903 /* Shift the read command bits out. */
904 for (i = 4 + addr_len; i >= 0; i--) {
905 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
906 writeb (EE_ENB | dataval, ee_addr);
907 eeprom_delay ();
908 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
909 eeprom_delay ();
910 }
911 writeb (EE_ENB, ee_addr);
912 eeprom_delay ();
913
914 for (i = 16; i > 0; i--) {
915 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
916 eeprom_delay ();
917 retval =
918 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
919 0);
920 writeb (EE_ENB, ee_addr);
921 eeprom_delay ();
922 }
923
924 /* Terminate the EEPROM access. */
925 writeb (~EE_CS, ee_addr);
926 eeprom_delay ();
927
928 DPRINTK ("EXIT - returning %d\n", retval);
929 return retval;
930 }
931
932 /* MII serial management: mostly bogus for now. */
933 /* Read and write the MII management registers using software-generated
934 serial MDIO protocol.
935 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
936 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
937 "overclocking" issues. */
938 #define MDIO_DIR 0x80
939 #define MDIO_DATA_OUT 0x04
940 #define MDIO_DATA_IN 0x02
941 #define MDIO_CLK 0x01
942 #define MDIO_WRITE0 (MDIO_DIR)
943 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
944
945 #define mdio_delay() readb(mdio_addr)
946
947
948 static char mii_2_8139_map[8] = {
949 BasicModeCtrl,
950 BasicModeStatus,
951 0,
952 0,
953 NWayAdvert,
954 NWayLPAR,
955 NWayExpansion,
956 0
957 };
958
959
960 /* Syncronize the MII management interface by shifting 32 one bits out. */
961 static void mdio_sync (void *mdio_addr)
962 {
963 int i;
964
965 DPRINTK ("ENTER\n");
966
967 for (i = 32; i >= 0; i--) {
968 writeb (MDIO_WRITE1, mdio_addr);
969 mdio_delay ();
970 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
971 mdio_delay ();
972 }
973
974 DPRINTK ("EXIT\n");
975 }
976
977
978 static int mdio_read (struct net_device *dev, int phy_id, int location)
979 {
980 struct netdrv_private *tp = dev->priv;
981 void *mdio_addr = tp->mmio_addr + Config4;
982 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
983 int retval = 0;
984 int i;
985
986 DPRINTK ("ENTER\n");
987
988 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
989 DPRINTK ("EXIT after directly using 8139 internal regs\n");
990 return location < 8 && mii_2_8139_map[location] ?
991 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
992 }
993 mdio_sync (mdio_addr);
994 /* Shift the read command bits out. */
995 for (i = 15; i >= 0; i--) {
996 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
997
998 writeb (MDIO_DIR | dataval, mdio_addr);
999 mdio_delay ();
1000 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1001 mdio_delay ();
1002 }
1003
1004 /* Read the two transition, 16 data, and wire-idle bits. */
1005 for (i = 19; i > 0; i--) {
1006 writeb (0, mdio_addr);
1007 mdio_delay ();
1008 retval =
1009 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1010 : 0);
1011 writeb (MDIO_CLK, mdio_addr);
1012 mdio_delay ();
1013 }
1014
1015 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1016 return (retval >> 1) & 0xffff;
1017 }
1018
1019
1020 static void mdio_write (struct net_device *dev, int phy_id, int location,
1021 int value)
1022 {
1023 struct netdrv_private *tp = dev->priv;
1024 void *mdio_addr = tp->mmio_addr + Config4;
1025 int mii_cmd =
1026 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1027 int i;
1028
1029 DPRINTK ("ENTER\n");
1030
1031 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1032 if (location < 8 && mii_2_8139_map[location]) {
1033 writew (value,
1034 tp->mmio_addr + mii_2_8139_map[location]);
1035 readw (tp->mmio_addr + mii_2_8139_map[location]);
1036 }
1037 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1038 return;
1039 }
1040 mdio_sync (mdio_addr);
1041
1042 /* Shift the command bits out. */
1043 for (i = 31; i >= 0; i--) {
1044 int dataval =
1045 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1046 writeb (dataval, mdio_addr);
1047 mdio_delay ();
1048 writeb (dataval | MDIO_CLK, mdio_addr);
1049 mdio_delay ();
1050 }
1051
1052 /* Clear out extra bits. */
1053 for (i = 2; i > 0; i--) {
1054 writeb (0, mdio_addr);
1055 mdio_delay ();
1056 writeb (MDIO_CLK, mdio_addr);
1057 mdio_delay ();
1058 }
1059
1060 DPRINTK ("EXIT\n");
1061 }
1062
1063
1064 static int netdrv_open (struct net_device *dev)
1065 {
1066 struct netdrv_private *tp = dev->priv;
1067 int retval;
1068 #ifdef NETDRV_DEBUG
1069 void *ioaddr = tp->mmio_addr;
1070 #endif
1071
1072 DPRINTK ("ENTER\n");
1073
1074 retval = request_irq (dev->irq, netdrv_interrupt, IRQF_SHARED, dev->name, dev);
1075 if (retval) {
1076 DPRINTK ("EXIT, returning %d\n", retval);
1077 return retval;
1078 }
1079
1080 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1081 &tp->tx_bufs_dma);
1082 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1083 &tp->rx_ring_dma);
1084 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1085 free_irq(dev->irq, dev);
1086
1087 if (tp->tx_bufs)
1088 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1089 tp->tx_bufs, tp->tx_bufs_dma);
1090 if (tp->rx_ring)
1091 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1092 tp->rx_ring, tp->rx_ring_dma);
1093
1094 DPRINTK ("EXIT, returning -ENOMEM\n");
1095 return -ENOMEM;
1096
1097 }
1098
1099 tp->full_duplex = tp->duplex_lock;
1100 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1101
1102 netdrv_init_ring (dev);
1103 netdrv_hw_start (dev);
1104
1105 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1106 " GP Pins %2.2x %s-duplex.\n",
1107 dev->name, pci_resource_start (tp->pci_dev, 1),
1108 dev->irq, NETDRV_R8 (MediaStatus),
1109 tp->full_duplex ? "full" : "half");
1110
1111 /* Set the timer to switch to check for link beat and perhaps switch
1112 to an alternate media type. */
1113 init_timer (&tp->timer);
1114 tp->timer.expires = jiffies + 3 * HZ;
1115 tp->timer.data = (unsigned long) dev;
1116 tp->timer.function = &netdrv_timer;
1117 add_timer (&tp->timer);
1118
1119 DPRINTK ("EXIT, returning 0\n");
1120 return 0;
1121 }
1122
1123
1124 /* Start the hardware at open or resume. */
1125 static void netdrv_hw_start (struct net_device *dev)
1126 {
1127 struct netdrv_private *tp = dev->priv;
1128 void *ioaddr = tp->mmio_addr;
1129 u32 i;
1130
1131 DPRINTK ("ENTER\n");
1132
1133 /* Soft reset the chip. */
1134 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1135 udelay (100);
1136
1137 /* Check that the chip has finished the reset. */
1138 for (i = 1000; i > 0; i--)
1139 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1140 break;
1141
1142 /* Restore our idea of the MAC address. */
1143 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1144 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1145
1146 /* Must enable Tx/Rx before setting transfer thresholds! */
1147 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1148 CmdRxEnb | CmdTxEnb);
1149
1150 i = netdrv_rx_config |
1151 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1152 NETDRV_W32_F (RxConfig, i);
1153
1154 /* Check this value: the documentation for IFG contradicts ifself. */
1155 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1156
1157 /* unlock Config[01234] and BMCR register writes */
1158 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1159 udelay (10);
1160
1161 tp->cur_rx = 0;
1162
1163 /* Lock Config[01234] and BMCR register writes */
1164 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1165 udelay (10);
1166
1167 /* init Rx ring buffer DMA address */
1168 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1169
1170 /* init Tx buffer DMA addresses */
1171 for (i = 0; i < NUM_TX_DESC; i++)
1172 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1173
1174 NETDRV_W32_F (RxMissed, 0);
1175
1176 netdrv_set_rx_mode (dev);
1177
1178 /* no early-rx interrupts */
1179 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1180
1181 /* make sure RxTx has started */
1182 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1183 CmdRxEnb | CmdTxEnb);
1184
1185 /* Enable all known interrupts by setting the interrupt mask. */
1186 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1187
1188 netif_start_queue (dev);
1189
1190 DPRINTK ("EXIT\n");
1191 }
1192
1193
1194 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1195 static void netdrv_init_ring (struct net_device *dev)
1196 {
1197 struct netdrv_private *tp = dev->priv;
1198 int i;
1199
1200 DPRINTK ("ENTER\n");
1201
1202 tp->cur_rx = 0;
1203 atomic_set (&tp->cur_tx, 0);
1204 atomic_set (&tp->dirty_tx, 0);
1205
1206 for (i = 0; i < NUM_TX_DESC; i++) {
1207 tp->tx_info[i].skb = NULL;
1208 tp->tx_info[i].mapping = 0;
1209 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1210 }
1211
1212 DPRINTK ("EXIT\n");
1213 }
1214
1215
1216 static void netdrv_timer (unsigned long data)
1217 {
1218 struct net_device *dev = (struct net_device *) data;
1219 struct netdrv_private *tp = dev->priv;
1220 void *ioaddr = tp->mmio_addr;
1221 int next_tick = 60 * HZ;
1222 int mii_lpa;
1223
1224 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1225
1226 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1227 int duplex = (mii_lpa & LPA_100FULL)
1228 || (mii_lpa & 0x01C0) == 0x0040;
1229 if (tp->full_duplex != duplex) {
1230 tp->full_duplex = duplex;
1231 printk (KERN_INFO
1232 "%s: Setting %s-duplex based on MII #%d link"
1233 " partner ability of %4.4x.\n", dev->name,
1234 tp->full_duplex ? "full" : "half",
1235 tp->phys[0], mii_lpa);
1236 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1237 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1238 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1239 }
1240 }
1241
1242 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1243 dev->name, NETDRV_R16 (NWayLPAR));
1244 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1245 " RxStatus %4.4x.\n", dev->name,
1246 NETDRV_R16 (IntrMask),
1247 NETDRV_R16 (IntrStatus),
1248 NETDRV_R32 (RxEarlyStatus));
1249 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1250 dev->name, NETDRV_R8 (Config0),
1251 NETDRV_R8 (Config1));
1252
1253 tp->timer.expires = jiffies + next_tick;
1254 add_timer (&tp->timer);
1255 }
1256
1257
1258 static void netdrv_tx_clear (struct netdrv_private *tp)
1259 {
1260 int i;
1261
1262 atomic_set (&tp->cur_tx, 0);
1263 atomic_set (&tp->dirty_tx, 0);
1264
1265 /* Dump the unsent Tx packets. */
1266 for (i = 0; i < NUM_TX_DESC; i++) {
1267 struct ring_info *rp = &tp->tx_info[i];
1268 if (rp->mapping != 0) {
1269 pci_unmap_single (tp->pci_dev, rp->mapping,
1270 rp->skb->len, PCI_DMA_TODEVICE);
1271 rp->mapping = 0;
1272 }
1273 if (rp->skb) {
1274 dev_kfree_skb (rp->skb);
1275 rp->skb = NULL;
1276 dev->stats.tx_dropped++;
1277 }
1278 }
1279 }
1280
1281
1282 static void netdrv_tx_timeout (struct net_device *dev)
1283 {
1284 struct netdrv_private *tp = dev->priv;
1285 void *ioaddr = tp->mmio_addr;
1286 int i;
1287 u8 tmp8;
1288 unsigned long flags;
1289
1290 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1291 "media %2.2x.\n", dev->name,
1292 NETDRV_R8 (ChipCmd),
1293 NETDRV_R16 (IntrStatus),
1294 NETDRV_R8 (MediaStatus));
1295
1296 /* disable Tx ASAP, if not already */
1297 tmp8 = NETDRV_R8 (ChipCmd);
1298 if (tmp8 & CmdTxEnb)
1299 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1300
1301 /* Disable interrupts by clearing the interrupt mask. */
1302 NETDRV_W16 (IntrMask, 0x0000);
1303
1304 /* Emit info to figure out what went wrong. */
1305 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1306 dev->name, atomic_read (&tp->cur_tx),
1307 atomic_read (&tp->dirty_tx));
1308 for (i = 0; i < NUM_TX_DESC; i++)
1309 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1310 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1311 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1312 " (queue head)" : "");
1313
1314 /* Stop a shared interrupt from scavenging while we are. */
1315 spin_lock_irqsave (&tp->lock, flags);
1316
1317 netdrv_tx_clear (tp);
1318
1319 spin_unlock_irqrestore (&tp->lock, flags);
1320
1321 /* ...and finally, reset everything */
1322 netdrv_hw_start (dev);
1323
1324 netif_wake_queue (dev);
1325 }
1326
1327
1328
1329 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1330 {
1331 struct netdrv_private *tp = dev->priv;
1332 void *ioaddr = tp->mmio_addr;
1333 int entry;
1334
1335 /* Calculate the next Tx descriptor entry. */
1336 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1337
1338 assert (tp->tx_info[entry].skb == NULL);
1339 assert (tp->tx_info[entry].mapping == 0);
1340
1341 tp->tx_info[entry].skb = skb;
1342 /* tp->tx_info[entry].mapping = 0; */
1343 skb_copy_from_linear_data(skb, tp->tx_buf[entry], skb->len);
1344
1345 /* Note: the chip doesn't have auto-pad! */
1346 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1347 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1348
1349 dev->trans_start = jiffies;
1350 atomic_inc (&tp->cur_tx);
1351 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1352 netif_stop_queue (dev);
1353
1354 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1355 dev->name, skb->data, skb->len, entry);
1356
1357 return 0;
1358 }
1359
1360
1361 static void netdrv_tx_interrupt (struct net_device *dev,
1362 struct netdrv_private *tp,
1363 void *ioaddr)
1364 {
1365 int cur_tx, dirty_tx, tx_left;
1366
1367 assert (dev != NULL);
1368 assert (tp != NULL);
1369 assert (ioaddr != NULL);
1370
1371 dirty_tx = atomic_read (&tp->dirty_tx);
1372
1373 cur_tx = atomic_read (&tp->cur_tx);
1374 tx_left = cur_tx - dirty_tx;
1375 while (tx_left > 0) {
1376 int entry = dirty_tx % NUM_TX_DESC;
1377 int txstatus;
1378
1379 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1380
1381 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1382 break; /* It still hasn't been Txed */
1383
1384 /* Note: TxCarrierLost is always asserted at 100mbps. */
1385 if (txstatus & (TxOutOfWindow | TxAborted)) {
1386 /* There was an major error, log it. */
1387 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1388 dev->name, txstatus);
1389 dev->stats.tx_errors++;
1390 if (txstatus & TxAborted) {
1391 dev->stats.tx_aborted_errors++;
1392 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1393 }
1394 if (txstatus & TxCarrierLost)
1395 dev->stats.tx_carrier_errors++;
1396 if (txstatus & TxOutOfWindow)
1397 dev->stats.tx_window_errors++;
1398 } else {
1399 if (txstatus & TxUnderrun) {
1400 /* Add 64 to the Tx FIFO threshold. */
1401 if (tp->tx_flag < 0x00300000)
1402 tp->tx_flag += 0x00020000;
1403 dev->stats.tx_fifo_errors++;
1404 }
1405 dev->stats.collisions += (txstatus >> 24) & 15;
1406 dev->stats.tx_bytes += txstatus & 0x7ff;
1407 dev->stats.tx_packets++;
1408 }
1409
1410 /* Free the original skb. */
1411 if (tp->tx_info[entry].mapping != 0) {
1412 pci_unmap_single(tp->pci_dev,
1413 tp->tx_info[entry].mapping,
1414 tp->tx_info[entry].skb->len,
1415 PCI_DMA_TODEVICE);
1416 tp->tx_info[entry].mapping = 0;
1417 }
1418 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1419 tp->tx_info[entry].skb = NULL;
1420 dirty_tx++;
1421 if (dirty_tx < 0) { /* handle signed int overflow */
1422 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1423 dirty_tx = cur_tx - tx_left + 1;
1424 }
1425 if (netif_queue_stopped (dev))
1426 netif_wake_queue (dev);
1427
1428 cur_tx = atomic_read (&tp->cur_tx);
1429 tx_left = cur_tx - dirty_tx;
1430
1431 }
1432
1433 #ifndef NETDRV_NDEBUG
1434 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1435 printk (KERN_ERR
1436 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1437 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1438 dirty_tx += NUM_TX_DESC;
1439 }
1440 #endif /* NETDRV_NDEBUG */
1441
1442 atomic_set (&tp->dirty_tx, dirty_tx);
1443 }
1444
1445
1446 /* TODO: clean this up! Rx reset need not be this intensive */
1447 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1448 struct netdrv_private *tp, void *ioaddr)
1449 {
1450 u8 tmp8;
1451 int tmp_work = 1000;
1452
1453 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1454 dev->name, rx_status);
1455 if (rx_status & RxTooLong) {
1456 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1457 dev->name, rx_status);
1458 /* A.C.: The chip hangs here. */
1459 }
1460 dev->stats.rx_errors++;
1461 if (rx_status & (RxBadSymbol | RxBadAlign))
1462 dev->stats.rx_frame_errors++;
1463 if (rx_status & (RxRunt | RxTooLong))
1464 dev->stats.rx_length_errors++;
1465 if (rx_status & RxCRCErr)
1466 dev->stats.rx_crc_errors++;
1467 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1468 tp->cur_rx = 0;
1469
1470 /* disable receive */
1471 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1472 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1473
1474 /* A.C.: Reset the multicast list. */
1475 netdrv_set_rx_mode (dev);
1476
1477 /* XXX potentially temporary hack to
1478 * restart hung receiver */
1479 while (--tmp_work > 0) {
1480 tmp8 = NETDRV_R8 (ChipCmd);
1481 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1482 break;
1483 NETDRV_W8_F (ChipCmd,
1484 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1485 }
1486
1487 /* G.S.: Re-enable receiver */
1488 /* XXX temporary hack to work around receiver hang */
1489 netdrv_set_rx_mode (dev);
1490
1491 if (tmp_work <= 0)
1492 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1493 }
1494
1495
1496 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1497 field alignments and semantics. */
1498 static void netdrv_rx_interrupt (struct net_device *dev,
1499 struct netdrv_private *tp, void *ioaddr)
1500 {
1501 unsigned char *rx_ring;
1502 u16 cur_rx;
1503
1504 assert (dev != NULL);
1505 assert (tp != NULL);
1506 assert (ioaddr != NULL);
1507
1508 rx_ring = tp->rx_ring;
1509 cur_rx = tp->cur_rx;
1510
1511 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1512 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1513 NETDRV_R16 (RxBufAddr),
1514 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1515
1516 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1517 int ring_offset = cur_rx % RX_BUF_LEN;
1518 u32 rx_status;
1519 unsigned int rx_size;
1520 unsigned int pkt_size;
1521 struct sk_buff *skb;
1522
1523 /* read size+status of next frame from DMA ring buffer */
1524 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1525 rx_size = rx_status >> 16;
1526 pkt_size = rx_size - 4;
1527
1528 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1529 " cur %4.4x.\n", dev->name, rx_status,
1530 rx_size, cur_rx);
1531 #if NETDRV_DEBUG > 2
1532 {
1533 int i;
1534 DPRINTK ("%s: Frame contents ", dev->name);
1535 for (i = 0; i < 70; i++)
1536 printk (" %2.2x",
1537 rx_ring[ring_offset + i]);
1538 printk (".\n");
1539 }
1540 #endif
1541
1542 /* If Rx err or invalid rx_size/rx_status received
1543 * (which happens if we get lost in the ring),
1544 * Rx process gets reset, so we abort any further
1545 * Rx processing.
1546 */
1547 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1548 (!(rx_status & RxStatusOK))) {
1549 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1550 return;
1551 }
1552
1553 /* Malloc up new buffer, compatible with net-2e. */
1554 /* Omit the four octet CRC from the length. */
1555
1556 /* TODO: consider allocating skb's outside of
1557 * interrupt context, both to speed interrupt processing,
1558 * and also to reduce the chances of having to
1559 * drop packets here under memory pressure.
1560 */
1561
1562 skb = dev_alloc_skb (pkt_size + 2);
1563 if (skb) {
1564 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1565
1566 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1567 skb_put (skb, pkt_size);
1568
1569 skb->protocol = eth_type_trans (skb, dev);
1570 netif_rx (skb);
1571 dev->last_rx = jiffies;
1572 dev->stats.rx_bytes += pkt_size;
1573 dev->stats.rx_packets++;
1574 } else {
1575 printk (KERN_WARNING
1576 "%s: Memory squeeze, dropping packet.\n",
1577 dev->name);
1578 dev->stats.rx_dropped++;
1579 }
1580
1581 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1582 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1583 }
1584
1585 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1586 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1587 NETDRV_R16 (RxBufAddr),
1588 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1589
1590 tp->cur_rx = cur_rx;
1591 }
1592
1593
1594 static void netdrv_weird_interrupt (struct net_device *dev,
1595 struct netdrv_private *tp,
1596 void *ioaddr,
1597 int status, int link_changed)
1598 {
1599 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1600 dev->name, status);
1601
1602 assert (dev != NULL);
1603 assert (tp != NULL);
1604 assert (ioaddr != NULL);
1605
1606 /* Update the error count. */
1607 dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1608 NETDRV_W32 (RxMissed, 0);
1609
1610 if ((status & RxUnderrun) && link_changed &&
1611 (tp->drv_flags & HAS_LNK_CHNG)) {
1612 /* Really link-change on new chips. */
1613 int lpar = NETDRV_R16 (NWayLPAR);
1614 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1615 || tp->duplex_lock;
1616 if (tp->full_duplex != duplex) {
1617 tp->full_duplex = duplex;
1618 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1619 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1620 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1621 }
1622 status &= ~RxUnderrun;
1623 }
1624
1625 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1626 if (status &
1627 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1628 dev->stats.rx_errors++;
1629
1630 if (status & (PCSTimeout))
1631 dev->stats.rx_length_errors++;
1632 if (status & (RxUnderrun | RxFIFOOver))
1633 dev->stats.rx_fifo_errors++;
1634 if (status & RxOverflow) {
1635 dev->stats.rx_over_errors++;
1636 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1637 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1638 }
1639 if (status & PCIErr) {
1640 u16 pci_cmd_status;
1641 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1642
1643 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1644 dev->name, pci_cmd_status);
1645 }
1646 }
1647
1648
1649 /* The interrupt handler does all of the Rx thread work and cleans up
1650 after the Tx thread. */
1651 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance)
1652 {
1653 struct net_device *dev = (struct net_device *) dev_instance;
1654 struct netdrv_private *tp = dev->priv;
1655 int boguscnt = max_interrupt_work;
1656 void *ioaddr = tp->mmio_addr;
1657 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1658 int handled = 0;
1659
1660 spin_lock (&tp->lock);
1661
1662 do {
1663 status = NETDRV_R16 (IntrStatus);
1664
1665 /* h/w no longer present (hotplug?) or major error, bail */
1666 if (status == 0xFFFF)
1667 break;
1668
1669 handled = 1;
1670 /* Acknowledge all of the current interrupt sources ASAP */
1671 NETDRV_W16_F (IntrStatus, status);
1672
1673 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1674 dev->name, status,
1675 NETDRV_R16 (IntrStatus));
1676
1677 if ((status &
1678 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1679 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1680 break;
1681
1682 /* Check uncommon events with one test. */
1683 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1684 RxFIFOOver | TxErr | RxErr))
1685 netdrv_weird_interrupt (dev, tp, ioaddr,
1686 status, link_changed);
1687
1688 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1689 netdrv_rx_interrupt (dev, tp, ioaddr);
1690
1691 if (status & (TxOK | TxErr))
1692 netdrv_tx_interrupt (dev, tp, ioaddr);
1693
1694 boguscnt--;
1695 } while (boguscnt > 0);
1696
1697 if (boguscnt <= 0) {
1698 printk (KERN_WARNING
1699 "%s: Too much work at interrupt, "
1700 "IntrStatus=0x%4.4x.\n", dev->name,
1701 status);
1702
1703 /* Clear all interrupt sources. */
1704 NETDRV_W16 (IntrStatus, 0xffff);
1705 }
1706
1707 spin_unlock (&tp->lock);
1708
1709 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1710 dev->name, NETDRV_R16 (IntrStatus));
1711 return IRQ_RETVAL(handled);
1712 }
1713
1714
1715 static int netdrv_close (struct net_device *dev)
1716 {
1717 struct netdrv_private *tp = dev->priv;
1718 void *ioaddr = tp->mmio_addr;
1719 unsigned long flags;
1720
1721 DPRINTK ("ENTER\n");
1722
1723 netif_stop_queue (dev);
1724
1725 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1726 dev->name, NETDRV_R16 (IntrStatus));
1727
1728 del_timer_sync (&tp->timer);
1729
1730 spin_lock_irqsave (&tp->lock, flags);
1731
1732 /* Stop the chip's Tx and Rx DMA processes. */
1733 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1734
1735 /* Disable interrupts by clearing the interrupt mask. */
1736 NETDRV_W16 (IntrMask, 0x0000);
1737
1738 /* Update the error counts. */
1739 dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1740 NETDRV_W32 (RxMissed, 0);
1741
1742 spin_unlock_irqrestore (&tp->lock, flags);
1743
1744 synchronize_irq ();
1745 free_irq (dev->irq, dev);
1746
1747 netdrv_tx_clear (tp);
1748
1749 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1750 tp->rx_ring, tp->rx_ring_dma);
1751 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1752 tp->tx_bufs, tp->tx_bufs_dma);
1753 tp->rx_ring = NULL;
1754 tp->tx_bufs = NULL;
1755
1756 /* Green! Put the chip in low-power mode. */
1757 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1758 NETDRV_W8 (Config1, 0x03);
1759 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1760
1761 DPRINTK ("EXIT\n");
1762 return 0;
1763 }
1764
1765
1766 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1767 {
1768 struct netdrv_private *tp = dev->priv;
1769 struct mii_ioctl_data *data = if_mii(rq);
1770 unsigned long flags;
1771 int rc = 0;
1772
1773 DPRINTK ("ENTER\n");
1774
1775 switch (cmd) {
1776 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1777 data->phy_id = tp->phys[0] & 0x3f;
1778 /* Fall Through */
1779
1780 case SIOCGMIIREG: /* Read MII PHY register. */
1781 spin_lock_irqsave (&tp->lock, flags);
1782 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1783 spin_unlock_irqrestore (&tp->lock, flags);
1784 break;
1785
1786 case SIOCSMIIREG: /* Write MII PHY register. */
1787 if (!capable (CAP_NET_ADMIN)) {
1788 rc = -EPERM;
1789 break;
1790 }
1791
1792 spin_lock_irqsave (&tp->lock, flags);
1793 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1794 spin_unlock_irqrestore (&tp->lock, flags);
1795 break;
1796
1797 default:
1798 rc = -EOPNOTSUPP;
1799 break;
1800 }
1801
1802 DPRINTK ("EXIT, returning %d\n", rc);
1803 return rc;
1804 }
1805
1806 /* Set or clear the multicast filter for this adaptor.
1807 This routine is not state sensitive and need not be SMP locked. */
1808
1809 static void netdrv_set_rx_mode (struct net_device *dev)
1810 {
1811 struct netdrv_private *tp = dev->priv;
1812 void *ioaddr = tp->mmio_addr;
1813 u32 mc_filter[2]; /* Multicast hash filter */
1814 int i, rx_mode;
1815 u32 tmp;
1816
1817 DPRINTK ("ENTER\n");
1818
1819 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1820 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1821
1822 /* Note: do not reorder, GCC is clever about common statements. */
1823 if (dev->flags & IFF_PROMISC) {
1824 rx_mode =
1825 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1826 AcceptAllPhys;
1827 mc_filter[1] = mc_filter[0] = 0xffffffff;
1828 } else if ((dev->mc_count > multicast_filter_limit)
1829 || (dev->flags & IFF_ALLMULTI)) {
1830 /* Too many to filter perfectly -- accept all multicasts. */
1831 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1832 mc_filter[1] = mc_filter[0] = 0xffffffff;
1833 } else {
1834 struct dev_mc_list *mclist;
1835 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1836 mc_filter[1] = mc_filter[0] = 0;
1837 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1838 i++, mclist = mclist->next) {
1839 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1840
1841 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1842 }
1843 }
1844
1845 /* if called from irq handler, lock already acquired */
1846 if (!in_irq ())
1847 spin_lock_irq (&tp->lock);
1848
1849 /* We can safely update without stopping the chip. */
1850 tmp = netdrv_rx_config | rx_mode |
1851 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1852 NETDRV_W32_F (RxConfig, tmp);
1853 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1854 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1855
1856 if (!in_irq ())
1857 spin_unlock_irq (&tp->lock);
1858
1859 DPRINTK ("EXIT\n");
1860 }
1861
1862
1863 #ifdef CONFIG_PM
1864
1865 static int netdrv_suspend (struct pci_dev *pdev, pm_message_t state)
1866 {
1867 struct net_device *dev = pci_get_drvdata (pdev);
1868 struct netdrv_private *tp = dev->priv;
1869 void *ioaddr = tp->mmio_addr;
1870 unsigned long flags;
1871
1872 if (!netif_running(dev))
1873 return 0;
1874 netif_device_detach (dev);
1875
1876 spin_lock_irqsave (&tp->lock, flags);
1877
1878 /* Disable interrupts, stop Tx and Rx. */
1879 NETDRV_W16 (IntrMask, 0x0000);
1880 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1881
1882 /* Update the error counts. */
1883 dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1884 NETDRV_W32 (RxMissed, 0);
1885
1886 spin_unlock_irqrestore (&tp->lock, flags);
1887
1888 pci_save_state (pdev);
1889 pci_set_power_state (pdev, PCI_D3hot);
1890
1891 return 0;
1892 }
1893
1894
1895 static int netdrv_resume (struct pci_dev *pdev)
1896 {
1897 struct net_device *dev = pci_get_drvdata (pdev);
1898 struct netdrv_private *tp = dev->priv;
1899
1900 if (!netif_running(dev))
1901 return 0;
1902 pci_set_power_state (pdev, PCI_D0);
1903 pci_restore_state (pdev);
1904 netif_device_attach (dev);
1905 netdrv_hw_start (dev);
1906
1907 return 0;
1908 }
1909
1910 #endif /* CONFIG_PM */
1911
1912
1913 static struct pci_driver netdrv_pci_driver = {
1914 .name = MODNAME,
1915 .id_table = netdrv_pci_tbl,
1916 .probe = netdrv_init_one,
1917 .remove = __devexit_p(netdrv_remove_one),
1918 #ifdef CONFIG_PM
1919 .suspend = netdrv_suspend,
1920 .resume = netdrv_resume,
1921 #endif /* CONFIG_PM */
1922 };
1923
1924
1925 static int __init netdrv_init_module (void)
1926 {
1927 /* when a module, this is printed whether or not devices are found in probe */
1928 #ifdef MODULE
1929 printk(version);
1930 #endif
1931 return pci_register_driver(&netdrv_pci_driver);
1932 }
1933
1934
1935 static void __exit netdrv_cleanup_module (void)
1936 {
1937 pci_unregister_driver (&netdrv_pci_driver);
1938 }
1939
1940
1941 module_init(netdrv_init_module);
1942 module_exit(netdrv_cleanup_module);
Mirror for ia64_pv_ops.git