arch/sh/boards/se/7343/irq.c

   1 /*
   2  * arch/sh/boards/se/7343/irq.c
   3  *
   4  */
   5 #include <linux/init.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/irq.h>
   8 #include <asm/irq.h>
   9 #include <asm/io.h>
  10 #include <asm/mach/se7343.h>
  11
  12 static void
  13 disable_intreq_irq(unsigned int irq)
  14 {
  15         int bit = irq - OFFCHIP_IRQ_BASE;
  16         u16 val;
  17
  18         val = ctrl_inw(PA_CPLD_IMSK);
  19         val |= 1 << bit;
  20         ctrl_outw(val, PA_CPLD_IMSK);
  21 }
  22
  23 static void
  24 enable_intreq_irq(unsigned int irq)
  25 {
  26         int bit = irq - OFFCHIP_IRQ_BASE;
  27         u16 val;
  28
  29         val = ctrl_inw(PA_CPLD_IMSK);
  30         val &= ~(1 << bit);
  31         ctrl_outw(val, PA_CPLD_IMSK);
  32 }
  33
  34 static void
  35 mask_and_ack_intreq_irq(unsigned int irq)
  36 {
  37         disable_intreq_irq(irq);
  38 }
  39
  40 static unsigned int
  41 startup_intreq_irq(unsigned int irq)
  42 {
  43         enable_intreq_irq(irq);
  44         return 0;
  45 }
  46
  47 static void
  48 shutdown_intreq_irq(unsigned int irq)
  49 {
  50         disable_intreq_irq(irq);
  51 }
  52
  53 static void
  54 end_intreq_irq(unsigned int irq)
  55 {
  56         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  57                 enable_intreq_irq(irq);
  58 }
  59
  60 static struct hw_interrupt_type intreq_irq_type = {
  61         .typename = "FPGA-IRQ",
  62         .startup = startup_intreq_irq,
  63         .shutdown = shutdown_intreq_irq,
  64         .enable = enable_intreq_irq,
  65         .disable = disable_intreq_irq,
  66         .ack = mask_and_ack_intreq_irq,
  67         .end = end_intreq_irq
  68 };
  69
  70 static void
  71 make_intreq_irq(unsigned int irq)
  72 {
  73         disable_irq_nosync(irq);
  74         irq_desc[irq].chip = &intreq_irq_type;
  75         disable_intreq_irq(irq);
  76 }
  77
  78 int
  79 shmse_irq_demux(int irq)
  80 {
  81         int bit;
  82         volatile u16 val;
  83
  84         if (irq == IRQ5_IRQ) {
  85                 /* Read status Register */
  86                 val = ctrl_inw(PA_CPLD_ST);
  87                 bit = ffs(val);
  88                 if (bit != 0)
  89                         return OFFCHIP_IRQ_BASE + bit - 1;
  90         }
  91         return irq;
  92 }
  93
  94 /* IRQ5 is multiplexed between the following sources:
  95  * 1. PC Card socket
  96  * 2. Extension slot
  97  * 3. USB Controller
  98  * 4. Serial Controller
  99  *
 100  * We configure IRQ5 as a cascade IRQ.
 101  */
 102 static struct irqaction irq5 = {
 103         .handler = no_action,
 104         .mask = CPU_MASK_NONE,
 105         .name = "IRQ5-cascade",
 106 };
 107
 108 static struct ipr_data se7343_irq5_ipr_map[] = {
 109         { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
 110 };
 111 static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
 112         { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
 113         { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
 114 };
 115 static struct ipr_data se7343_other_ipr_map[] = {
 116         { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
 117         { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
 118         { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
 119         { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
 120         { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
 121         { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
 122
 123         /* I2C block */
 124         { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
 125         { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
 126         { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
 127         { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
 128
 129         { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
 130         { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
 131         { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
 132         { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
 133
 134         /* SIOF */
 135         { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
 136
 137         /* SIU */
 138         { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
 139
 140         /* VIO interrupt */
 141         { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
 142         { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
 143         { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
 144
 145         /*MFI interrupt*/
 146
 147         { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
 148
 149         /* LCD controller */
 150         { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
 151 };
 152
 153 /*
 154  * Initialize IRQ setting
 155  */
 156 void __init
 157 init_7343se_IRQ(void)
 158 {
 159         /* Setup Multiplexed interrupts */
 160         ctrl_outw(8, PA_CPLD_MODESET);  /* Set all CPLD interrupts to active
 161                                          * low.
 162                                          */
 163         /* Mask all CPLD controller interrupts */
 164         ctrl_outw(0x0fff, PA_CPLD_IMSK);
 165
 166         /* PC Card interrupts */
 167         make_intreq_irq(PC_IRQ0);
 168         make_intreq_irq(PC_IRQ1);
 169         make_intreq_irq(PC_IRQ2);
 170         make_intreq_irq(PC_IRQ3);
 171
 172         /* Extension Slot Interrupts */
 173         make_intreq_irq(EXT_IRQ0);
 174         make_intreq_irq(EXT_IRQ1);
 175         make_intreq_irq(EXT_IRQ2);
 176         make_intreq_irq(EXT_IRQ3);
 177
 178         /* USB Controller interrupts */
 179         make_intreq_irq(USB_IRQ0);
 180         make_intreq_irq(USB_IRQ1);
 181
 182         /* Serial Controller interrupts */
 183         make_intreq_irq(UART_IRQ0);
 184         make_intreq_irq(UART_IRQ1);
 185
 186         /* Setup all external interrupts to be active low */
 187         ctrl_outw(0xaaaa, INTC_ICR1);
 188
 189         make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
 190
 191         setup_irq(IRQ5_IRQ, &irq5);
 192         /* Set port control to use IRQ5 */
 193         *(u16 *)0xA4050108 &= ~0xc;
 194
 195         make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
 196
 197         ctrl_outb(0x0f, INTC_IMCR5);    /* enable SCIF IRQ */
 198
 199         make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
 200
 201         ctrl_outw(0x2000, PA_MRSHPC + 0x0c);    /* mrshpc irq enable */
 202 }