bluetooth: hci_core: defer hci_unregister_sysfs()
[pv_ops_mirror.git] / arch / x86 / kernel / tsc_64.c
blob947554ddabb6c7779f9e9adedfc07d7891dba283
1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/interrupt.h>
4 #include <linux/init.h>
5 #include <linux/clocksource.h>
6 #include <linux/time.h>
7 #include <linux/acpi.h>
8 #include <linux/cpufreq.h>
9 #include <linux/acpi_pmtmr.h>
11 #include <asm/hpet.h>
12 #include <asm/timex.h>
13 #include <asm/timer.h>
15 static int notsc __initdata = 0;
17 unsigned int cpu_khz; /* TSC clocks / usec, not used here */
18 EXPORT_SYMBOL(cpu_khz);
19 unsigned int tsc_khz;
20 EXPORT_SYMBOL(tsc_khz);
22 /* Accelerators for sched_clock()
23 * convert from cycles(64bits) => nanoseconds (64bits)
24 * basic equation:
25 * ns = cycles / (freq / ns_per_sec)
26 * ns = cycles * (ns_per_sec / freq)
27 * ns = cycles * (10^9 / (cpu_khz * 10^3))
28 * ns = cycles * (10^6 / cpu_khz)
30 * Then we use scaling math (suggested by george@mvista.com) to get:
31 * ns = cycles * (10^6 * SC / cpu_khz) / SC
32 * ns = cycles * cyc2ns_scale / SC
34 * And since SC is a constant power of two, we can convert the div
35 * into a shift.
37 * We can use khz divisor instead of mhz to keep a better precision, since
38 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
39 * (mathieu.desnoyers@polymtl.ca)
41 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
43 DEFINE_PER_CPU(unsigned long, cyc2ns);
45 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
47 unsigned long flags, prev_scale, *scale;
48 unsigned long long tsc_now, ns_now;
50 local_irq_save(flags);
51 sched_clock_idle_sleep_event();
53 scale = &per_cpu(cyc2ns, cpu);
55 rdtscll(tsc_now);
56 ns_now = __cycles_2_ns(tsc_now);
58 prev_scale = *scale;
59 if (cpu_khz)
60 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
62 sched_clock_idle_wakeup_event(0);
63 local_irq_restore(flags);
66 unsigned long long native_sched_clock(void)
68 unsigned long a = 0;
70 /* Could do CPU core sync here. Opteron can execute rdtsc speculatively,
71 * which means it is not completely exact and may not be monotonous
72 * between CPUs. But the errors should be too small to matter for
73 * scheduling purposes.
76 rdtscll(a);
77 return cycles_2_ns(a);
80 /* We need to define a real function for sched_clock, to override the
81 weak default version */
82 #ifdef CONFIG_PARAVIRT
83 unsigned long long sched_clock(void)
85 return paravirt_sched_clock();
87 #else
88 unsigned long long
89 sched_clock(void) __attribute__((alias("native_sched_clock")));
90 #endif
93 static int tsc_unstable;
95 int check_tsc_unstable(void)
97 return tsc_unstable;
99 EXPORT_SYMBOL_GPL(check_tsc_unstable);
101 #ifdef CONFIG_CPU_FREQ
103 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
104 * changes.
106 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
107 * not that important because current Opteron setups do not support
108 * scaling on SMP anyroads.
110 * Should fix up last_tsc too. Currently gettimeofday in the
111 * first tick after the change will be slightly wrong.
114 static unsigned int ref_freq;
115 static unsigned long loops_per_jiffy_ref;
116 static unsigned long tsc_khz_ref;
118 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
119 void *data)
121 struct cpufreq_freqs *freq = data;
122 unsigned long *lpj, dummy;
124 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
125 return 0;
127 lpj = &dummy;
128 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
129 #ifdef CONFIG_SMP
130 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
131 #else
132 lpj = &boot_cpu_data.loops_per_jiffy;
133 #endif
135 if (!ref_freq) {
136 ref_freq = freq->old;
137 loops_per_jiffy_ref = *lpj;
138 tsc_khz_ref = tsc_khz;
140 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
141 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
142 (val == CPUFREQ_RESUMECHANGE)) {
143 *lpj =
144 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
146 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
147 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
148 mark_tsc_unstable("cpufreq changes");
151 preempt_disable();
152 set_cyc2ns_scale(tsc_khz_ref, smp_processor_id());
153 preempt_enable();
155 return 0;
158 static struct notifier_block time_cpufreq_notifier_block = {
159 .notifier_call = time_cpufreq_notifier
162 static int __init cpufreq_tsc(void)
164 cpufreq_register_notifier(&time_cpufreq_notifier_block,
165 CPUFREQ_TRANSITION_NOTIFIER);
166 return 0;
169 core_initcall(cpufreq_tsc);
171 #endif
173 #define MAX_RETRIES 5
174 #define SMI_TRESHOLD 50000
177 * Read TSC and the reference counters. Take care of SMI disturbance
179 static unsigned long __init tsc_read_refs(unsigned long *pm,
180 unsigned long *hpet)
182 unsigned long t1, t2;
183 int i;
185 for (i = 0; i < MAX_RETRIES; i++) {
186 t1 = get_cycles();
187 if (hpet)
188 *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
189 else
190 *pm = acpi_pm_read_early();
191 t2 = get_cycles();
192 if ((t2 - t1) < SMI_TRESHOLD)
193 return t2;
195 return ULONG_MAX;
199 * tsc_calibrate - calibrate the tsc on boot
201 void __init tsc_calibrate(void)
203 unsigned long flags, tsc1, tsc2, tr1, tr2, pm1, pm2, hpet1, hpet2;
204 int hpet = is_hpet_enabled(), cpu;
206 local_irq_save(flags);
208 tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
210 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
212 outb(0xb0, 0x43);
213 outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
214 outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
215 tr1 = get_cycles();
216 while ((inb(0x61) & 0x20) == 0);
217 tr2 = get_cycles();
219 tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
221 local_irq_restore(flags);
224 * Preset the result with the raw and inaccurate PIT
225 * calibration value
227 tsc_khz = (tr2 - tr1) / 50;
229 /* hpet or pmtimer available ? */
230 if (!hpet && !pm1 && !pm2) {
231 printk(KERN_INFO "TSC calibrated against PIT\n");
232 return;
235 /* Check, whether the sampling was disturbed by an SMI */
236 if (tsc1 == ULONG_MAX || tsc2 == ULONG_MAX) {
237 printk(KERN_WARNING "TSC calibration disturbed by SMI, "
238 "using PIT calibration result\n");
239 return;
242 tsc2 = (tsc2 - tsc1) * 1000000L;
244 if (hpet) {
245 printk(KERN_INFO "TSC calibrated against HPET\n");
246 if (hpet2 < hpet1)
247 hpet2 += 0x100000000;
248 hpet2 -= hpet1;
249 tsc1 = (hpet2 * hpet_readl(HPET_PERIOD)) / 1000000;
250 } else {
251 printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
252 if (pm2 < pm1)
253 pm2 += ACPI_PM_OVRRUN;
254 pm2 -= pm1;
255 tsc1 = (pm2 * 1000000000) / PMTMR_TICKS_PER_SEC;
258 tsc_khz = tsc2 / tsc1;
260 for_each_possible_cpu(cpu)
261 set_cyc2ns_scale(tsc_khz, cpu);
265 * Make an educated guess if the TSC is trustworthy and synchronized
266 * over all CPUs.
268 __cpuinit int unsynchronized_tsc(void)
270 if (tsc_unstable)
271 return 1;
273 #ifdef CONFIG_SMP
274 if (apic_is_clustered_box())
275 return 1;
276 #endif
278 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
279 return 0;
281 /* Assume multi socket systems are not synchronized */
282 return num_present_cpus() > 1;
285 int __init notsc_setup(char *s)
287 notsc = 1;
288 return 1;
291 __setup("notsc", notsc_setup);
294 /* clock source code: */
295 static cycle_t read_tsc(void)
297 cycle_t ret = (cycle_t)get_cycles();
298 return ret;
301 static cycle_t __vsyscall_fn vread_tsc(void)
303 cycle_t ret = (cycle_t)vget_cycles();
304 return ret;
307 static struct clocksource clocksource_tsc = {
308 .name = "tsc",
309 .rating = 300,
310 .read = read_tsc,
311 .mask = CLOCKSOURCE_MASK(64),
312 .shift = 22,
313 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
314 CLOCK_SOURCE_MUST_VERIFY,
315 .vread = vread_tsc,
318 void mark_tsc_unstable(char *reason)
320 if (!tsc_unstable) {
321 tsc_unstable = 1;
322 printk("Marking TSC unstable due to %s\n", reason);
323 /* Change only the rating, when not registered */
324 if (clocksource_tsc.mult)
325 clocksource_change_rating(&clocksource_tsc, 0);
326 else
327 clocksource_tsc.rating = 0;
330 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
332 void __init init_tsc_clocksource(void)
334 if (!notsc) {
335 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
336 clocksource_tsc.shift);
337 if (check_tsc_unstable())
338 clocksource_tsc.rating = 0;
340 clocksource_register(&clocksource_tsc);