arch/x86/pci/numa.c

   1 /*
   2  * numa.c - Low-level PCI access for NUMA-Q machines
   3  */
   4
   5 #include <linux/pci.h>
   6 #include <linux/init.h>
   7 #include <linux/nodemask.h>
   8 #include <mach_apic.h>
   9 #include "pci.h"
  10
  11 #define XQUAD_PORTIO_BASE 0xfe400000
  12 #define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */
  13
  14 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
  15 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
  16 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
  17
  18 extern void *xquad_portio;    /* Where the IO area was mapped */
  19 #define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
  20
  21 #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
  22         (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
  23
  24 static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
  25 {
  26         unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
  27         if (xquad_portio)
  28                 writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
  29         else
  30                 outl(val, 0xCF8);
  31 }
  32
  33 static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
  34                              unsigned int devfn, int reg, int len, u32 *value)
  35 {
  36         unsigned long flags;
  37         void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
  38
  39         if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
  40                 return -EINVAL;
  41
  42         spin_lock_irqsave(&pci_config_lock, flags);
  43
  44         write_cf8(bus, devfn, reg);
  45
  46         switch (len) {
  47         case 1:
  48                 if (xquad_portio)
  49                         *value = readb(adr + (reg & 3));
  50                 else
  51                         *value = inb(0xCFC + (reg & 3));
  52                 break;
  53         case 2:
  54                 if (xquad_portio)
  55                         *value = readw(adr + (reg & 2));
  56                 else
  57                         *value = inw(0xCFC + (reg & 2));
  58                 break;
  59         case 4:
  60                 if (xquad_portio)
  61                         *value = readl(adr);
  62                 else
  63                         *value = inl(0xCFC);
  64                 break;
  65         }
  66
  67         spin_unlock_irqrestore(&pci_config_lock, flags);
  68
  69         return 0;
  70 }
  71
  72 static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
  73                               unsigned int devfn, int reg, int len, u32 value)
  74 {
  75         unsigned long flags;
  76         void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
  77
  78         if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
  79                 return -EINVAL;
  80
  81         spin_lock_irqsave(&pci_config_lock, flags);
  82
  83         write_cf8(bus, devfn, reg);
  84
  85         switch (len) {
  86         case 1:
  87                 if (xquad_portio)
  88                         writeb(value, adr + (reg & 3));
  89                 else
  90                         outb((u8)value, 0xCFC + (reg & 3));
  91                 break;
  92         case 2:
  93                 if (xquad_portio)
  94                         writew(value, adr + (reg & 2));
  95                 else
  96                         outw((u16)value, 0xCFC + (reg & 2));
  97                 break;
  98         case 4:
  99                 if (xquad_portio)
 100                         writel(value, adr + reg);
 101                 else
 102                         outl((u32)value, 0xCFC);
 103                 break;
 104         }
 105
 106         spin_unlock_irqrestore(&pci_config_lock, flags);
 107
 108         return 0;
 109 }
 110
 111 #undef PCI_CONF1_MQ_ADDRESS
 112
 113 static struct pci_raw_ops pci_direct_conf1_mq = {
 114         .read   = pci_conf1_mq_read,
 115         .write  = pci_conf1_mq_write
 116 };
 117
 118
 119 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
 120 {
 121         /*
 122          * i450NX -- Find and scan all secondary buses on all PXB's.
 123          */
 124         int pxb, reg;
 125         u8 busno, suba, subb;
 126         int quad = BUS2QUAD(d->bus->number);
 127
 128         printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
 129         reg = 0xd0;
 130         for(pxb=0; pxb<2; pxb++) {
 131                 pci_read_config_byte(d, reg++, &busno);
 132                 pci_read_config_byte(d, reg++, &suba);
 133                 pci_read_config_byte(d, reg++, &subb);
 134                 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
 135                 if (busno) {
 136                         /* Bus A */
 137                         pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
 138                 }
 139                 if (suba < subb) {
 140                         /* Bus B */
 141                         pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
 142                 }
 143         }
 144         pcibios_last_bus = -1;
 145 }
 146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
 147
 148 static int __init pci_numa_init(void)
 149 {
 150         int quad;
 151
 152         raw_pci_ops = &pci_direct_conf1_mq;
 153
 154         if (pcibios_scanned++)
 155                 return 0;
 156
 157         pci_root_bus = pcibios_scan_root(0);
 158         if (pci_root_bus)
 159                 pci_bus_add_devices(pci_root_bus);
 160         if (num_online_nodes() > 1)
 161                 for_each_online_node(quad) {
 162                         if (quad == 0)
 163                                 continue;
 164                         printk("Scanning PCI bus %d for quad %d\n",
 165                                 QUADLOCAL2BUS(quad,0), quad);
 166                         pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
 167                 }
 168         return 0;
 169 }
 170
 171 subsys_initcall(pci_numa_init);