1 #ifndef _IOP13XX_TIME_H_
2 #define _IOP13XX_TIME_H_
3 #define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
5 #define IOP_TMR_EN 0x02
6 #define IOP_TMR_RELOAD 0x04
7 #define IOP_TMR_PRIVILEGED 0x08
8 #define IOP_TMR_RATIO_1_1 0x00
10 #define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
11 #define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
12 #define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
13 #define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
14 #define IOP13XX_CORE_FREQ_MASK (7 << 16)
15 #define IOP13XX_CORE_FREQ_600 (0 << 16)
16 #define IOP13XX_CORE_FREQ_667 (1 << 16)
17 #define IOP13XX_CORE_FREQ_800 (2 << 16)
18 #define IOP13XX_CORE_FREQ_933 (3 << 16)
19 #define IOP13XX_CORE_FREQ_1000 (4 << 16)
20 #define IOP13XX_CORE_FREQ_1200 (5 << 16)
22 void iop_init_time(unsigned long tickrate
);
23 unsigned long iop_gettimeoffset(void);
25 static inline unsigned long iop13xx_core_freq(void)
27 unsigned long freq
= __raw_readl(IOP13XX_PROCESSOR_FREQ
);
28 freq
&= IOP13XX_CORE_FREQ_MASK
;
30 case IOP13XX_CORE_FREQ_600
:
32 case IOP13XX_CORE_FREQ_667
:
34 case IOP13XX_CORE_FREQ_800
:
36 case IOP13XX_CORE_FREQ_933
:
38 case IOP13XX_CORE_FREQ_1000
:
40 case IOP13XX_CORE_FREQ_1200
:
43 printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
50 static inline unsigned long iop13xx_xsi_bus_ratio(void)
52 unsigned long ratio
= __raw_readl(IOP13XX_PROCESSOR_FREQ
);
53 ratio
&= IOP13XX_XSI_FREQ_RATIO_MASK
;
55 case IOP13XX_XSI_FREQ_RATIO_2
:
57 case IOP13XX_XSI_FREQ_RATIO_3
:
59 case IOP13XX_XSI_FREQ_RATIO_4
:
62 printk("%s: warning unknown ratio, defaulting to 2\n",
69 static inline void write_tmr0(u32 val
)
71 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val
));
74 static inline void write_tmr1(u32 val
)
76 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val
));
79 static inline u32
read_tcr0(void)
82 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val
));
86 static inline u32
read_tcr1(void)
89 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val
));
93 static inline void write_trr0(u32 val
)
95 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val
));
98 static inline void write_trr1(u32 val
)
100 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val
));
103 static inline void write_tisr(u32 val
)
105 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val
));