block/genhd.c: cleanups
[pv_ops_mirror.git] / include / asm-sh / cpu-sh4 / dma.h
blobaaf71b018c281399ade954200171fc60400c8f33
1 #ifndef __ASM_CPU_SH4_DMA_H
2 #define __ASM_CPU_SH4_DMA_H
4 #define DMAOR_INIT ( 0x8000 | DMAOR_DME )
6 /* SH7751/7760/7780 DMA IRQ sources */
7 #define DMTE0_IRQ 34
8 #define DMTE1_IRQ 35
9 #define DMTE2_IRQ 36
10 #define DMTE3_IRQ 37
11 #define DMTE4_IRQ 44
12 #define DMTE5_IRQ 45
13 #define DMTE6_IRQ 46
14 #define DMTE7_IRQ 47
15 #define DMAE_IRQ 38
17 #ifdef CONFIG_CPU_SH4A
18 #define SH_DMAC_BASE 0xfc808020
20 #define CHCR_TS_MASK 0x18
21 #define CHCR_TS_SHIFT 3
23 #include <asm/cpu/dma-sh7780.h>
24 #else
25 #define SH_DMAC_BASE 0xffa00000
27 /* Definitions for the SuperH DMAC */
28 #define TM_BURST 0x0000080
29 #define TS_8 0x00000010
30 #define TS_16 0x00000020
31 #define TS_32 0x00000030
32 #define TS_64 0x00000000
34 #define CHCR_TS_MASK 0x70
35 #define CHCR_TS_SHIFT 4
37 #define DMAOR_COD 0x00000008
40 * The SuperH DMAC supports a number of transmit sizes, we list them here,
41 * with their respective values as they appear in the CHCR registers.
43 * Defaults to a 64-bit transfer size.
45 enum {
46 XMIT_SZ_64BIT,
47 XMIT_SZ_8BIT,
48 XMIT_SZ_16BIT,
49 XMIT_SZ_32BIT,
50 XMIT_SZ_256BIT,
54 * The DMA count is defined as the number of bytes to transfer.
56 static unsigned int ts_shift[] __maybe_unused = {
57 [XMIT_SZ_64BIT] = 3,
58 [XMIT_SZ_8BIT] = 0,
59 [XMIT_SZ_16BIT] = 1,
60 [XMIT_SZ_32BIT] = 2,
61 [XMIT_SZ_256BIT] = 5,
63 #endif
65 #endif /* __ASM_CPU_SH4_DMA_H */