include/asm-sparc/dma.h

   1 /* include/asm-sparc/dma.h
   2  *
   3  * Copyright 1995 (C) David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #ifndef _ASM_SPARC_DMA_H
   7 #define _ASM_SPARC_DMA_H
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11
  12 #include <asm/vac-ops.h>  /* for invalidate's, etc. */
  13 #include <asm/sbus.h>
  14 #include <asm/delay.h>
  15 #include <asm/oplib.h>
  16 #include <asm/system.h>
  17 #include <asm/io.h>
  18 #include <linux/spinlock.h>
  19
  20 struct page;
  21 extern spinlock_t  dma_spin_lock;
  22
  23 static inline unsigned long claim_dma_lock(void)
  24 {
  25         unsigned long flags;
  26         spin_lock_irqsave(&dma_spin_lock, flags);
  27         return flags;
  28 }
  29
  30 static inline void release_dma_lock(unsigned long flags)
  31 {
  32         spin_unlock_irqrestore(&dma_spin_lock, flags);
  33 }
  34
  35 /* These are irrelevant for Sparc DMA, but we leave it in so that
  36  * things can compile.
  37  */
  38 #define MAX_DMA_CHANNELS 8
  39 #define MAX_DMA_ADDRESS  (~0UL)
  40 #define DMA_MODE_READ    1
  41 #define DMA_MODE_WRITE   2
  42
  43 /* Useful constants */
  44 #define SIZE_16MB      (16*1024*1024)
  45 #define SIZE_64K       (64*1024)
  46
  47 /* SBUS DMA controller reg offsets */
  48 #define DMA_CSR         0x00UL          /* rw  DMA control/status register    0x00   */
  49 #define DMA_ADDR        0x04UL          /* rw  DMA transfer address register  0x04   */
  50 #define DMA_COUNT       0x08UL          /* rw  DMA transfer count register    0x08   */
  51 #define DMA_TEST        0x0cUL          /* rw  DMA test/debug register        0x0c   */
  52
  53 /* DVMA chip revisions */
  54 enum dvma_rev {
  55         dvmarev0,
  56         dvmaesc1,
  57         dvmarev1,
  58         dvmarev2,
  59         dvmarev3,
  60         dvmarevplus,
  61         dvmahme
  62 };
  63
  64 #define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
  65
  66 /* Linux DMA information structure, filled during probe. */
  67 struct sbus_dma {
  68         struct sbus_dma *next;
  69         struct sbus_dev *sdev;
  70         void __iomem *regs;
  71
  72         /* Status, misc info */
  73         int node;                /* Prom node for this DMA device */
  74         int running;             /* Are we doing DMA now? */
  75         int allocated;           /* Are we "owned" by anyone yet? */
  76
  77         /* Transfer information. */
  78         unsigned long addr;      /* Start address of current transfer */
  79         int nbytes;              /* Size of current transfer */
  80         int realbytes;           /* For splitting up large transfers, etc. */
  81
  82         /* DMA revision */
  83         enum dvma_rev revision;
  84 };
  85
  86 extern struct sbus_dma *dma_chain;
  87
  88 /* Broken hardware... */
  89 #ifdef CONFIG_SUN4
  90 /* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
  91  * Or is rev0 present only on sun4 boxes? -jj */
  92 #define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
  93 #else
  94 #define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev1)
  95 #endif
  96 #define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
  97
  98 /* Main routines in dma.c */
  99 extern void dvma_init(struct sbus_bus *);
 100
 101 /* Fields in the cond_reg register */
 102 /* First, the version identification bits */
 103 #define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
 104 #define DMA_VERS0        0x00000000        /* Sunray DMA version */
 105 #define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
 106 #define DMA_VERS1        0x80000000        /* DMA rev 1 */
 107 #define DMA_VERS2        0xa0000000        /* DMA rev 2 */
 108 #define DMA_VERHME       0xb0000000        /* DMA hme gate array */
 109 #define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
 110
 111 #define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
 112 #define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
 113 #define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
 114 #define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
 115 #define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
 116 #define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
 117 #define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
 118 #define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
 119 #define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
 120 #define DMA_RST_BPP      DMA_RST_SCSI      /* Reset the BPP controller */
 121 #define DMA_ST_WRITE     0x00000100        /* write from device to memory */
 122 #define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
 123 #define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
 124 #define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
 125 #define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
 126 #define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
 127 #define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
 128 #define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
 129 #define DMA_SCSI_SBUS64  0x00008000        /* HME: Enable 64-bit SBUS mode. */
 130 #define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
 131 #define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
 132 #define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
 133 #define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
 134 #define DMA_E_BURSTS     0x000c0000        /* ENET: SBUS r/w burst mask */
 135 #define DMA_E_BURST32    0x00040000        /* ENET: SBUS 32 byte r/w burst */
 136 #define DMA_E_BURST16    0x00000000        /* ENET: SBUS 16 byte r/w burst */
 137 #define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
 138 #define DMA_BRST64       0x00080000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
 139 #define DMA_BRST32       0x00040000        /* SCSI/BPP: 32byte bursts */
 140 #define DMA_BRST16       0x00000000        /* SCSI/BPP: 16byte bursts */
 141 #define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
 142 #define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
 143 #define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
 144 #define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
 145 #define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
 146 #define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
 147 #define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
 148 #define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
 149 #define DMA_BPP_ON       DMA_SCSI_ON       /* Enable BPP dma */
 150 #define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
 151 #define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
 152 #define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
 153 #define DMA_RESET_FAS366 0x08000000        /* HME: Assert RESET to FAS366 */
 154
 155 /* Values describing the burst-size property from the PROM */
 156 #define DMA_BURST1       0x01
 157 #define DMA_BURST2       0x02
 158 #define DMA_BURST4       0x04
 159 #define DMA_BURST8       0x08
 160 #define DMA_BURST16      0x10
 161 #define DMA_BURST32      0x20
 162 #define DMA_BURST64      0x40
 163 #define DMA_BURSTBITS    0x7f
 164
 165 /* Determine highest possible final transfer address given a base */
 166 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
 167
 168 /* Yes, I hack a lot of elisp in my spare time... */
 169 #define DMA_ERROR_P(regs)  ((((regs)->cond_reg) & DMA_HNDL_ERROR))
 170 #define DMA_IRQ_P(regs)    ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
 171 #define DMA_WRITE_P(regs)  ((((regs)->cond_reg) & DMA_ST_WRITE))
 172 #define DMA_OFF(regs)      ((((regs)->cond_reg) &= (~DMA_ENABLE)))
 173 #define DMA_INTSOFF(regs)  ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
 174 #define DMA_INTSON(regs)   ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
 175 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
 176 #define DMA_SETSTART(regs, addr)  ((((regs)->st_addr) = (char *) addr))
 177 #define DMA_BEGINDMA_W(regs) \
 178         ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
 179 #define DMA_BEGINDMA_R(regs) \
 180         ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
 181
 182 /* For certain DMA chips, we need to disable ints upon irq entry
 183  * and turn them back on when we are done.  So in any ESP interrupt
 184  * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
 185  * when leaving the handler.  You have been warned...
 186  */
 187 #define DMA_IRQ_ENTRY(dma, dregs) do { \
 188         if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
 189    } while (0)
 190
 191 #define DMA_IRQ_EXIT(dma, dregs) do { \
 192         if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
 193    } while(0)
 194
 195 #if 0   /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
 196 /* Pause until counter runs out or BIT isn't set in the DMA condition
 197  * register.
 198  */
 199 static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
 200                                        unsigned long bit)
 201 {
 202         int ctr = 50000;   /* Let's find some bugs ;) */
 203
 204         /* Busy wait until the bit is not set any more */
 205         while((regs->cond_reg&bit) && (ctr>0)) {
 206                 ctr--;
 207                 __delay(5);
 208         }
 209
 210         /* Check for bogus outcome. */
 211         if(!ctr)
 212                 panic("DMA timeout");
 213 }
 214
 215 /* Reset the friggin' thing... */
 216 #define DMA_RESET(dma) do { \
 217         struct sparc_dma_registers *regs = dma->regs;                      \
 218         /* Let the current FIFO drain itself */                            \
 219         sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN));                         \
 220         /* Reset the logic */                                              \
 221         regs->cond_reg |= (DMA_RST_SCSI);     /* assert */                 \
 222         __delay(400);                         /* let the bits set ;) */    \
 223         regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */              \
 224         sparc_dma_enable_interrupts(regs);    /* Re-enable interrupts */   \
 225         /* Enable FAST transfers if available */                           \
 226         if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS;            \
 227         dma->running = 0;                                                  \
 228 } while(0)
 229 #endif
 230
 231 #define for_each_dvma(dma) \
 232         for((dma) = dma_chain; (dma); (dma) = (dma)->next)
 233
 234 extern int get_dma_list(char *);
 235 extern int request_dma(unsigned int, __const__ char *);
 236 extern void free_dma(unsigned int);
 237
 238 /* From PCI */
 239
 240 #ifdef CONFIG_PCI
 241 extern int isa_dma_bridge_buggy;
 242 #else
 243 #define isa_dma_bridge_buggy    (0)
 244 #endif
 245
 246 /* Routines for data transfer buffers. */
 247 BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
 248 BTFIXUPDEF_CALL(void,   mmu_unlockarea, char *, unsigned long)
 249
 250 #define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
 251 #define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
 252
 253 /* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
 254 BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
 255 BTFIXUPDEF_CALL(void,  mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
 256 BTFIXUPDEF_CALL(void,  mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
 257 BTFIXUPDEF_CALL(void,  mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
 258
 259 #define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
 260 #define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
 261 #define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
 262 #define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
 263
 264 /*
 265  * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
 266  *
 267  * The mmu_map_dma_area establishes two mappings in one go.
 268  * These mappings point to pages normally mapped at 'va' (linear address).
 269  * First mapping is for CPU visible address at 'a', uncached.
 270  * This is an alias, but it works because it is an uncached mapping.
 271  * Second mapping is for device visible address, or "bus" address.
 272  * The bus address is returned at '*pba'.
 273  *
 274  * These functions seem distinct, but are hard to split. On sun4c,
 275  * at least for now, 'a' is equal to bus address, and retured in *pba.
 276  * On sun4m, page attributes depend on the CPU type, so we have to
 277  * know if we are mapping RAM or I/O, so it has to be an additional argument
 278  * to a separate mapping function for CPU visible mappings.
 279  */
 280 BTFIXUPDEF_CALL(int,  mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
 281 BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
 282 BTFIXUPDEF_CALL(void,  mmu_unmap_dma_area, unsigned long busa, int len)
 283
 284 #define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
 285 #define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
 286 #define mmu_translate_dvma(ba)     BTFIXUP_CALL(mmu_translate_dvma)(ba)
 287
 288 #endif /* !(_ASM_SPARC_DMA_H) */