6 * read{b,w,l}/write{b,w,l} are for PCI,
7 * while in{b,w,l}/out{b,w,l} are for ISA
8 * These may (will) be platform specific function.
9 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
10 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
12 * do not have a memory barrier after them.
14 * In addition, we have
15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
16 * which are processor specific.
20 * We follow the Alpha convention here:
21 * __inb expands to an inline function call (which calls via the mv)
22 * _inb is a real function call (note ___raw fns are _ version of __raw)
23 * inb by default expands to _inb, but the machine specific code may
24 * define it to __inb if it chooses.
26 #include <asm/cache.h>
27 #include <asm/system.h>
28 #include <asm/addrspace.h>
29 #include <asm/machvec.h>
30 #include <asm/pgtable.h>
31 #include <asm-generic/iomap.h>
36 * Depending on which platform we are running on, we need different
39 #define __IO_PREFIX generic
40 #include <asm/io_generic.h>
42 #define maybebadio(port) \
43 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
44 __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
47 * Since boards are able to define their own set of I/O routines through
48 * their respective machine vector, we always wrap through the mv.
50 * Also, in the event that a board hasn't provided its own definition for
51 * a given routine, it will be wrapped to generic code at run-time.
54 #define __inb(p) sh_mv.mv_inb((p))
55 #define __inw(p) sh_mv.mv_inw((p))
56 #define __inl(p) sh_mv.mv_inl((p))
57 #define __outb(x,p) sh_mv.mv_outb((x),(p))
58 #define __outw(x,p) sh_mv.mv_outw((x),(p))
59 #define __outl(x,p) sh_mv.mv_outl((x),(p))
61 #define __inb_p(p) sh_mv.mv_inb_p((p))
62 #define __inw_p(p) sh_mv.mv_inw_p((p))
63 #define __inl_p(p) sh_mv.mv_inl_p((p))
64 #define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
65 #define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
66 #define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
68 #define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
69 #define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
70 #define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
71 #define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
72 #define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
73 #define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
75 #define __readb(a) sh_mv.mv_readb((a))
76 #define __readw(a) sh_mv.mv_readw((a))
77 #define __readl(a) sh_mv.mv_readl((a))
78 #define __writeb(v,a) sh_mv.mv_writeb((v),(a))
79 #define __writew(v,a) sh_mv.mv_writew((v),(a))
80 #define __writel(v,a) sh_mv.mv_writel((v),(a))
92 #define outb_p __outb_p
93 #define outw_p __outw_p
94 #define outl_p __outl_p
100 #define outsw __outsw
101 #define outsl __outsl
103 #define __raw_readb(a) __readb((void __iomem *)(a))
104 #define __raw_readw(a) __readw((void __iomem *)(a))
105 #define __raw_readl(a) __readl((void __iomem *)(a))
106 #define __raw_writeb(v, a) __writeb(v, (void __iomem *)(a))
107 #define __raw_writew(v, a) __writew(v, (void __iomem *)(a))
108 #define __raw_writel(v, a) __writel(v, (void __iomem *)(a))
110 void __raw_writesl(unsigned long addr
, const void *data
, int longlen
);
111 void __raw_readsl(unsigned long addr
, void *data
, int longlen
);
114 * The platform header files may define some of these macros to use
115 * the inlined versions where appropriate. These macros may also be
116 * redefined by userlevel programs.
119 # define readb(a) ({ unsigned int r_ = __raw_readb(a); mb(); r_; })
122 # define readw(a) ({ unsigned int r_ = __raw_readw(a); mb(); r_; })
125 # define readl(a) ({ unsigned int r_ = __raw_readl(a); mb(); r_; })
129 # define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
132 # define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
135 # define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
138 #define __BUILD_MEMORY_STRING(bwlq, type) \
140 static inline void writes##bwlq(volatile void __iomem *mem, \
141 const void *addr, unsigned int count) \
143 const volatile type *__addr = addr; \
146 __raw_write##bwlq(*__addr, mem); \
151 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
152 unsigned int count) \
154 volatile type *__addr = addr; \
157 *__addr = __raw_read##bwlq(mem); \
162 __BUILD_MEMORY_STRING(b
, u8
)
163 __BUILD_MEMORY_STRING(w
, u16
)
164 #define writesl __raw_writesl
165 #define readsl __raw_readsl
167 #define readb_relaxed(a) readb(a)
168 #define readw_relaxed(a) readw(a)
169 #define readl_relaxed(a) readl(a)
172 #define ioread8(a) readb(a)
173 #define ioread16(a) readw(a)
174 #define ioread16be(a) be16_to_cpu(__raw_readw((a)))
175 #define ioread32(a) readl(a)
176 #define ioread32be(a) be32_to_cpu(__raw_readl((a)))
178 #define iowrite8(v,a) writeb((v),(a))
179 #define iowrite16(v,a) writew((v),(a))
180 #define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
181 #define iowrite32(v,a) writel((v),(a))
182 #define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
184 #define ioread8_rep(a,d,c) insb((a),(d),(c))
185 #define ioread16_rep(a,d,c) insw((a),(d),(c))
186 #define ioread32_rep(a,d,c) insl((a),(d),(c))
188 #define iowrite8_rep(a,s,c) outsb((a),(s),(c))
189 #define iowrite16_rep(a,s,c) outsw((a),(s),(c))
190 #define iowrite32_rep(a,s,c) outsl((a),(s),(c))
192 #define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
195 * This function provides a method for the generic case where a board-specific
196 * ioport_map simply needs to return the port + some arbitrary port base.
198 * We use this at board setup time to implicitly set the port base, and
199 * as a result, we can use the generic ioport_map.
201 static inline void __set_io_port_base(unsigned long pbase
)
203 extern unsigned long generic_io_base
;
205 generic_io_base
= pbase
;
208 /* We really want to try and get these to memcpy etc */
209 extern void memcpy_fromio(void *, volatile void __iomem
*, unsigned long);
210 extern void memcpy_toio(volatile void __iomem
*, const void *, unsigned long);
211 extern void memset_io(volatile void __iomem
*, int, unsigned long);
213 /* SuperH on-chip I/O functions */
214 static inline unsigned char ctrl_inb(unsigned long addr
)
216 return *(volatile unsigned char*)addr
;
219 static inline unsigned short ctrl_inw(unsigned long addr
)
221 return *(volatile unsigned short*)addr
;
224 static inline unsigned int ctrl_inl(unsigned long addr
)
226 return *(volatile unsigned long*)addr
;
229 static inline void ctrl_outb(unsigned char b
, unsigned long addr
)
231 *(volatile unsigned char*)addr
= b
;
234 static inline void ctrl_outw(unsigned short b
, unsigned long addr
)
236 *(volatile unsigned short*)addr
= b
;
239 static inline void ctrl_outl(unsigned int b
, unsigned long addr
)
241 *(volatile unsigned long*)addr
= b
;
244 static inline void ctrl_delay(void)
249 #define IO_SPACE_LIMIT 0xffffffff
253 * Change virtual addresses to physical addresses and vv.
254 * These are trivial on the 1:1 Linux/SuperH mapping
256 static inline unsigned long virt_to_phys(volatile void *address
)
258 return PHYSADDR(address
);
261 static inline void *phys_to_virt(unsigned long address
)
263 return (void *)P1SEGADDR(address
);
266 #define phys_to_virt(address) ((void *)(address))
267 #define virt_to_phys(address) ((unsigned long)(address))
271 * readX/writeX() are used to access memory mapped devices. On some
272 * architectures the memory mapped IO stuff needs to be accessed
273 * differently. On the x86 architecture, we just read/write the
274 * memory location directly.
276 * On SH, we traditionally have the whole physical address space mapped
277 * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not
278 * need to do anything but place the address in the proper segment. This
279 * is true for P1 and P2 addresses, as well as some P3 ones. However,
280 * most of the P3 addresses and newer cores using extended addressing
281 * need to map through page tables, so the ioremap() implementation
282 * becomes a bit more complicated. See arch/sh/mm/ioremap.c for
283 * additional notes on this.
285 * We cheat a bit and always return uncachable areas until we've fixed
286 * the drivers to handle caching properly.
289 void __iomem
*__ioremap(unsigned long offset
, unsigned long size
,
290 unsigned long flags
);
291 void __iounmap(void __iomem
*addr
);
293 #define __ioremap(offset, size, flags) ((void __iomem *)(offset))
294 #define __iounmap(addr) do { } while (0)
295 #endif /* CONFIG_MMU */
297 static inline void __iomem
*
298 __ioremap_mode(unsigned long offset
, unsigned long size
, unsigned long flags
)
300 unsigned long last_addr
= offset
+ size
- 1;
303 * For P1 and P2 space this is trivial, as everything is already
304 * mapped. Uncached access for P1 addresses are done through P2.
305 * In the P3 case or for addresses outside of the 29-bit space,
306 * mapping must be done by the PMB or by using page tables.
308 if (likely(PXSEG(offset
) < P3SEG
&& PXSEG(last_addr
) < P3SEG
)) {
309 if (unlikely(flags
& _PAGE_CACHABLE
))
310 return (void __iomem
*)P1SEGADDR(offset
);
312 return (void __iomem
*)P2SEGADDR(offset
);
315 return __ioremap(offset
, size
, flags
);
318 #define ioremap(offset, size) \
319 __ioremap_mode((offset), (size), 0)
320 #define ioremap_nocache(offset, size) \
321 __ioremap_mode((offset), (size), 0)
322 #define ioremap_cache(offset, size) \
323 __ioremap_mode((offset), (size), _PAGE_CACHABLE)
324 #define p3_ioremap(offset, size, flags) \
325 __ioremap((offset), (size), (flags))
326 #define iounmap(addr) \
330 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
333 #define xlate_dev_mem_ptr(p) __va(p)
336 * Convert a virtual cached pointer to an uncached pointer
338 #define xlate_dev_kmem_ptr(p) p
340 #endif /* __KERNEL__ */
342 #endif /* __ASM_SH_IO_H */