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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / ata / sata_qstor.c
blobc4c4cd29eebba87bfc84e8eeb9c2e20c41bc5e74
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/device.h>
38 #include <scsi/scsi_host.h>
39 #include <linux/libata.h>
40
41 #define DRV_NAME "sata_qstor"
42 #define DRV_VERSION "0.09"
43
44 enum {
45 QS_MMIO_BAR = 4,
46
47 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100 };
101
102 enum {
103 QS_DMA_BOUNDARY = ~0UL
104 };
105
106 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
107
108 struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112 };
113
114 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
115 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
117 static int qs_port_start(struct ata_port *ap);
118 static void qs_host_stop(struct ata_host *host);
119 static void qs_phy_reset(struct ata_port *ap);
120 static void qs_qc_prep(struct ata_queued_cmd *qc);
121 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
122 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
123 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
124 static u8 qs_bmdma_status(struct ata_port *ap);
125 static void qs_irq_clear(struct ata_port *ap);
126 static void qs_eng_timeout(struct ata_port *ap);
127
128 static struct scsi_host_template qs_ata_sht = {
129 .module = THIS_MODULE,
130 .name = DRV_NAME,
131 .ioctl = ata_scsi_ioctl,
132 .queuecommand = ata_scsi_queuecmd,
133 .can_queue = ATA_DEF_QUEUE,
134 .this_id = ATA_SHT_THIS_ID,
135 .sg_tablesize = QS_MAX_PRD,
136 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
137 .emulated = ATA_SHT_EMULATED,
138 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
139 .use_clustering = ENABLE_CLUSTERING,
140 .proc_name = DRV_NAME,
141 .dma_boundary = QS_DMA_BOUNDARY,
142 .slave_configure = ata_scsi_slave_config,
143 .slave_destroy = ata_scsi_slave_destroy,
144 .bios_param = ata_std_bios_param,
145 };
146
147 static const struct ata_port_operations qs_ata_ops = {
148 .tf_load = ata_tf_load,
149 .tf_read = ata_tf_read,
150 .check_status = ata_check_status,
151 .check_atapi_dma = qs_check_atapi_dma,
152 .exec_command = ata_exec_command,
153 .dev_select = ata_std_dev_select,
154 .phy_reset = qs_phy_reset,
155 .qc_prep = qs_qc_prep,
156 .qc_issue = qs_qc_issue,
157 .data_xfer = ata_data_xfer,
158 .eng_timeout = qs_eng_timeout,
159 .irq_clear = qs_irq_clear,
160 .irq_on = ata_irq_on,
161 .scr_read = qs_scr_read,
162 .scr_write = qs_scr_write,
163 .port_start = qs_port_start,
164 .host_stop = qs_host_stop,
165 .bmdma_stop = qs_bmdma_stop,
166 .bmdma_status = qs_bmdma_status,
167 };
168
169 static const struct ata_port_info qs_port_info[] = {
170 /* board_2068_idx */
171 {
172 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
173 ATA_FLAG_SATA_RESET |
174 //FIXME ATA_FLAG_SRST |
175 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
176 .pio_mask = 0x10, /* pio4 */
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &qs_ata_ops,
179 },
180 };
181
182 static const struct pci_device_id qs_ata_pci_tbl[] = {
183 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
184
185 { } /* terminate list */
186 };
187
188 static struct pci_driver qs_ata_pci_driver = {
189 .name = DRV_NAME,
190 .id_table = qs_ata_pci_tbl,
191 .probe = qs_ata_init_one,
192 .remove = ata_pci_remove_one,
193 };
194
195 static void __iomem *qs_mmio_base(struct ata_host *host)
196 {
197 return host->iomap[QS_MMIO_BAR];
198 }
199
200 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
201 {
202 return 1; /* ATAPI DMA not supported */
203 }
204
205 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
206 {
207 /* nothing */
208 }
209
210 static u8 qs_bmdma_status(struct ata_port *ap)
211 {
212 return 0;
213 }
214
215 static void qs_irq_clear(struct ata_port *ap)
216 {
217 /* nothing */
218 }
219
220 static inline void qs_enter_reg_mode(struct ata_port *ap)
221 {
222 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
223
224 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
225 readb(chan + QS_CCT_CTR0); /* flush */
226 }
227
228 static inline void qs_reset_channel_logic(struct ata_port *ap)
229 {
230 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
231
232 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
233 readb(chan + QS_CCT_CTR0); /* flush */
234 qs_enter_reg_mode(ap);
235 }
236
237 static void qs_phy_reset(struct ata_port *ap)
238 {
239 struct qs_port_priv *pp = ap->private_data;
240
241 pp->state = qs_state_idle;
242 qs_reset_channel_logic(ap);
243 sata_phy_reset(ap);
244 }
245
246 static void qs_eng_timeout(struct ata_port *ap)
247 {
248 struct qs_port_priv *pp = ap->private_data;
249
250 if (pp->state != qs_state_idle) /* healthy paranoia */
251 pp->state = qs_state_mmio;
252 qs_reset_channel_logic(ap);
253 ata_eng_timeout(ap);
254 }
255
256 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
257 {
258 if (sc_reg > SCR_CONTROL)
259 return -EINVAL;
260 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 8));
261 return 0;
262 }
263
264 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
265 {
266 if (sc_reg > SCR_CONTROL)
267 return -EINVAL;
268 writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
269 return 0;
270 }
271
272 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
273 {
274 struct scatterlist *sg;
275 struct ata_port *ap = qc->ap;
276 struct qs_port_priv *pp = ap->private_data;
277 unsigned int nelem;
278 u8 *prd = pp->pkt + QS_CPB_BYTES;
279
280 WARN_ON(qc->__sg == NULL);
281 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
282
283 nelem = 0;
284 ata_for_each_sg(sg, qc) {
285 u64 addr;
286 u32 len;
287
288 addr = sg_dma_address(sg);
289 *(__le64 *)prd = cpu_to_le64(addr);
290 prd += sizeof(u64);
291
292 len = sg_dma_len(sg);
293 *(__le32 *)prd = cpu_to_le32(len);
294 prd += sizeof(u64);
295
296 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
297 (unsigned long long)addr, len);
298 nelem++;
299 }
300
301 return nelem;
302 }
303
304 static void qs_qc_prep(struct ata_queued_cmd *qc)
305 {
306 struct qs_port_priv *pp = qc->ap->private_data;
307 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
308 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
309 u64 addr;
310 unsigned int nelem;
311
312 VPRINTK("ENTER\n");
313
314 qs_enter_reg_mode(qc->ap);
315 if (qc->tf.protocol != ATA_PROT_DMA) {
316 ata_qc_prep(qc);
317 return;
318 }
319
320 nelem = qs_fill_sg(qc);
321
322 if ((qc->tf.flags & ATA_TFLAG_WRITE))
323 hflags |= QS_HF_DIRO;
324 if ((qc->tf.flags & ATA_TFLAG_LBA48))
325 dflags |= QS_DF_ELBA;
326
327 /* host control block (HCB) */
328 buf[ 0] = QS_HCB_HDR;
329 buf[ 1] = hflags;
330 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
331 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
332 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
333 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
334
335 /* device control block (DCB) */
336 buf[24] = QS_DCB_HDR;
337 buf[28] = dflags;
338
339 /* frame information structure (FIS) */
340 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
341 }
342
343 static inline void qs_packet_start(struct ata_queued_cmd *qc)
344 {
345 struct ata_port *ap = qc->ap;
346 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
347
348 VPRINTK("ENTER, ap %p\n", ap);
349
350 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
351 wmb(); /* flush PRDs and pkt to memory */
352 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
353 readl(chan + QS_CCT_CFF); /* flush */
354 }
355
356 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
357 {
358 struct qs_port_priv *pp = qc->ap->private_data;
359
360 switch (qc->tf.protocol) {
361 case ATA_PROT_DMA:
362
363 pp->state = qs_state_pkt;
364 qs_packet_start(qc);
365 return 0;
366
367 case ATA_PROT_ATAPI_DMA:
368 BUG();
369 break;
370
371 default:
372 break;
373 }
374
375 pp->state = qs_state_mmio;
376 return ata_qc_issue_prot(qc);
377 }
378
379 static inline unsigned int qs_intr_pkt(struct ata_host *host)
380 {
381 unsigned int handled = 0;
382 u8 sFFE;
383 u8 __iomem *mmio_base = qs_mmio_base(host);
384
385 do {
386 u32 sff0 = readl(mmio_base + QS_HST_SFF);
387 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
388 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
389 sFFE = sff1 >> 31; /* empty flag */
390
391 if (sEVLD) {
392 u8 sDST = sff0 >> 16; /* dev status */
393 u8 sHST = sff1 & 0x3f; /* host status */
394 unsigned int port_no = (sff1 >> 8) & 0x03;
395 struct ata_port *ap = host->ports[port_no];
396
397 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
398 sff1, sff0, port_no, sHST, sDST);
399 handled = 1;
400 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
401 struct ata_queued_cmd *qc;
402 struct qs_port_priv *pp = ap->private_data;
403 if (!pp || pp->state != qs_state_pkt)
404 continue;
405 qc = ata_qc_from_tag(ap, ap->link.active_tag);
406 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
407 switch (sHST) {
408 case 0: /* successful CPB */
409 case 3: /* device error */
410 pp->state = qs_state_idle;
411 qs_enter_reg_mode(qc->ap);
412 qc->err_mask |= ac_err_mask(sDST);
413 ata_qc_complete(qc);
414 break;
415 default:
416 break;
417 }
418 }
419 }
420 }
421 } while (!sFFE);
422 return handled;
423 }
424
425 static inline unsigned int qs_intr_mmio(struct ata_host *host)
426 {
427 unsigned int handled = 0, port_no;
428
429 for (port_no = 0; port_no < host->n_ports; ++port_no) {
430 struct ata_port *ap;
431 ap = host->ports[port_no];
432 if (ap &&
433 !(ap->flags & ATA_FLAG_DISABLED)) {
434 struct ata_queued_cmd *qc;
435 struct qs_port_priv *pp = ap->private_data;
436 if (!pp || pp->state != qs_state_mmio)
437 continue;
438 qc = ata_qc_from_tag(ap, ap->link.active_tag);
439 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
440
441 /* check main status, clearing INTRQ */
442 u8 status = ata_check_status(ap);
443 if ((status & ATA_BUSY))
444 continue;
445 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
446 ap->print_id, qc->tf.protocol, status);
447
448 /* complete taskfile transaction */
449 pp->state = qs_state_idle;
450 qc->err_mask |= ac_err_mask(status);
451 ata_qc_complete(qc);
452 handled = 1;
453 }
454 }
455 }
456 return handled;
457 }
458
459 static irqreturn_t qs_intr(int irq, void *dev_instance)
460 {
461 struct ata_host *host = dev_instance;
462 unsigned int handled = 0;
463
464 VPRINTK("ENTER\n");
465
466 spin_lock(&host->lock);
467 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
468 spin_unlock(&host->lock);
469
470 VPRINTK("EXIT\n");
471
472 return IRQ_RETVAL(handled);
473 }
474
475 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
476 {
477 port->cmd_addr =
478 port->data_addr = base + 0x400;
479 port->error_addr =
480 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
481 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
482 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
483 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
484 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
485 port->device_addr = base + 0x430;
486 port->status_addr =
487 port->command_addr = base + 0x438;
488 port->altstatus_addr =
489 port->ctl_addr = base + 0x440;
490 port->scr_addr = base + 0xc00;
491 }
492
493 static int qs_port_start(struct ata_port *ap)
494 {
495 struct device *dev = ap->host->dev;
496 struct qs_port_priv *pp;
497 void __iomem *mmio_base = qs_mmio_base(ap->host);
498 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
499 u64 addr;
500 int rc;
501
502 rc = ata_port_start(ap);
503 if (rc)
504 return rc;
505 qs_enter_reg_mode(ap);
506 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
507 if (!pp)
508 return -ENOMEM;
509 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
510 GFP_KERNEL);
511 if (!pp->pkt)
512 return -ENOMEM;
513 memset(pp->pkt, 0, QS_PKT_BYTES);
514 ap->private_data = pp;
515
516 addr = (u64)pp->pkt_dma;
517 writel((u32) addr, chan + QS_CCF_CPBA);
518 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
519 return 0;
520 }
521
522 static void qs_host_stop(struct ata_host *host)
523 {
524 void __iomem *mmio_base = qs_mmio_base(host);
525
526 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
527 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
528 }
529
530 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
531 {
532 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
533 unsigned int port_no;
534
535 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
536 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
537
538 /* reset each channel in turn */
539 for (port_no = 0; port_no < host->n_ports; ++port_no) {
540 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
541 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
542 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
543 readb(chan + QS_CCT_CTR0); /* flush */
544 }
545 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
546
547 for (port_no = 0; port_no < host->n_ports; ++port_no) {
548 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
549 /* set FIFO depths to same settings as Windows driver */
550 writew(32, chan + QS_CFC_HUFT);
551 writew(32, chan + QS_CFC_HDFT);
552 writew(10, chan + QS_CFC_DUFT);
553 writew( 8, chan + QS_CFC_DDFT);
554 /* set CPB size in bytes, as a power of two */
555 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
556 }
557 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
558 }
559
560 /*
561 * The QStor understands 64-bit buses, and uses 64-bit fields
562 * for DMA pointers regardless of bus width. We just have to
563 * make sure our DMA masks are set appropriately for whatever
564 * bridge lies between us and the QStor, and then the DMA mapping
565 * code will ensure we only ever "see" appropriate buffer addresses.
566 * If we're 32-bit limited somewhere, then our 64-bit fields will
567 * just end up with zeros in the upper 32-bits, without any special
568 * logic required outside of this routine (below).
569 */
570 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
571 {
572 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
573 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
574
575 if (have_64bit_bus &&
576 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
577 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
578 if (rc) {
579 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
580 if (rc) {
581 dev_printk(KERN_ERR, &pdev->dev,
582 "64-bit DMA enable failed\n");
583 return rc;
584 }
585 }
586 } else {
587 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
588 if (rc) {
589 dev_printk(KERN_ERR, &pdev->dev,
590 "32-bit DMA enable failed\n");
591 return rc;
592 }
593 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
594 if (rc) {
595 dev_printk(KERN_ERR, &pdev->dev,
596 "32-bit consistent DMA enable failed\n");
597 return rc;
598 }
599 }
600 return 0;
601 }
602
603 static int qs_ata_init_one(struct pci_dev *pdev,
604 const struct pci_device_id *ent)
605 {
606 static int printed_version;
607 unsigned int board_idx = (unsigned int) ent->driver_data;
608 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
609 struct ata_host *host;
610 int rc, port_no;
611
612 if (!printed_version++)
613 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
614
615 /* alloc host */
616 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
617 if (!host)
618 return -ENOMEM;
619
620 /* acquire resources and fill host */
621 rc = pcim_enable_device(pdev);
622 if (rc)
623 return rc;
624
625 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
626 return -ENODEV;
627
628 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
629 if (rc)
630 return rc;
631 host->iomap = pcim_iomap_table(pdev);
632
633 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
634 if (rc)
635 return rc;
636
637 for (port_no = 0; port_no < host->n_ports; ++port_no) {
638 struct ata_port *ap = host->ports[port_no];
639 unsigned int offset = port_no * 0x4000;
640 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
641
642 qs_ata_setup_port(&ap->ioaddr, chan);
643
644 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
645 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
646 }
647
648 /* initialize adapter */
649 qs_host_init(host, board_idx);
650
651 pci_set_master(pdev);
652 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
653 &qs_ata_sht);
654 }
655
656 static int __init qs_ata_init(void)
657 {
658 return pci_register_driver(&qs_ata_pci_driver);
659 }
660
661 static void __exit qs_ata_exit(void)
662 {
663 pci_unregister_driver(&qs_ata_pci_driver);
664 }
665
666 MODULE_AUTHOR("Mark Lord");
667 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
668 MODULE_LICENSE("GPL");
669 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
670 MODULE_VERSION(DRV_VERSION);
671
672 module_init(qs_ata_init);
673 module_exit(qs_ata_exit);
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