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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / char / agp / hp-agp.c
blob313a133a1172fac20135a71af05f2e865eddf420
1 /*
2 * HP zx1 AGPGART routines.
3 *
4 * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
5 * Bjorn Helgaas <bjorn.helgaas@hp.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/acpi.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/agp_backend.h>
17
18 #include <asm/acpi-ext.h>
19
20 #include "agp.h"
21
22 #ifndef log2
23 #define log2(x) ffz(~(x))
24 #endif
25
26 #define HP_ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
27
28 /* HP ZX1 IOC registers */
29 #define HP_ZX1_IBASE 0x300
30 #define HP_ZX1_IMASK 0x308
31 #define HP_ZX1_PCOM 0x310
32 #define HP_ZX1_TCNFG 0x318
33 #define HP_ZX1_PDIR_BASE 0x320
34
35 #define HP_ZX1_IOVA_BASE GB(1UL)
36 #define HP_ZX1_IOVA_SIZE GB(1UL)
37 #define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2)
38 #define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
39
40 #define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL
41 #define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift)
42
43 #define AGP8X_MODE_BIT 3
44 #define AGP8X_MODE (1 << AGP8X_MODE_BIT)
45
46 /* AGP bridge need not be PCI device, but DRM thinks it is. */
47 static struct pci_dev fake_bridge_dev;
48
49 static int hp_zx1_gart_found;
50
51 static struct aper_size_info_fixed hp_zx1_sizes[] =
52 {
53 {0, 0, 0}, /* filled in by hp_zx1_fetch_size() */
54 };
55
56 static struct gatt_mask hp_zx1_masks[] =
57 {
58 {.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0}
59 };
60
61 static struct _hp_private {
62 volatile u8 __iomem *ioc_regs;
63 volatile u8 __iomem *lba_regs;
64 int lba_cap_offset;
65 u64 *io_pdir; // PDIR for entire IOVA
66 u64 *gatt; // PDIR just for GART (subset of above)
67 u64 gatt_entries;
68 u64 iova_base;
69 u64 gart_base;
70 u64 gart_size;
71 u64 io_pdir_size;
72 int io_pdir_owner; // do we own it, or share it with sba_iommu?
73 int io_page_size;
74 int io_tlb_shift;
75 int io_tlb_ps; // IOC ps config
76 int io_pages_per_kpage;
77 } hp_private;
78
79 static int __init hp_zx1_ioc_shared(void)
80 {
81 struct _hp_private *hp = &hp_private;
82
83 printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n");
84
85 /*
86 * IOC already configured by sba_iommu module; just use
87 * its setup. We assume:
88 * - IOVA space is 1Gb in size
89 * - first 512Mb is IOMMU, second 512Mb is GART
90 */
91 hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
92 switch (hp->io_tlb_ps) {
93 case 0: hp->io_tlb_shift = 12; break;
94 case 1: hp->io_tlb_shift = 13; break;
95 case 2: hp->io_tlb_shift = 14; break;
96 case 3: hp->io_tlb_shift = 16; break;
97 default:
98 printk(KERN_ERR PFX "Invalid IOTLB page size "
99 "configuration 0x%x\n", hp->io_tlb_ps);
100 hp->gatt = NULL;
101 hp->gatt_entries = 0;
102 return -ENODEV;
103 }
104 hp->io_page_size = 1 << hp->io_tlb_shift;
105 hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
106
107 hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1;
108 hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE;
109
110 hp->gart_size = HP_ZX1_GART_SIZE;
111 hp->gatt_entries = hp->gart_size / hp->io_page_size;
112
113 hp->io_pdir = gart_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE));
114 hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
115
116 if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
117 /* Normal case when no AGP device in system */
118 hp->gatt = NULL;
119 hp->gatt_entries = 0;
120 printk(KERN_ERR PFX "No reserved IO PDIR entry found; "
121 "GART disabled\n");
122 return -ENODEV;
123 }
124
125 return 0;
126 }
127
128 static int __init
129 hp_zx1_ioc_owner (void)
130 {
131 struct _hp_private *hp = &hp_private;
132
133 printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n");
134
135 /*
136 * Select an IOV page size no larger than system page size.
137 */
138 if (PAGE_SIZE >= KB(64)) {
139 hp->io_tlb_shift = 16;
140 hp->io_tlb_ps = 3;
141 } else if (PAGE_SIZE >= KB(16)) {
142 hp->io_tlb_shift = 14;
143 hp->io_tlb_ps = 2;
144 } else if (PAGE_SIZE >= KB(8)) {
145 hp->io_tlb_shift = 13;
146 hp->io_tlb_ps = 1;
147 } else {
148 hp->io_tlb_shift = 12;
149 hp->io_tlb_ps = 0;
150 }
151 hp->io_page_size = 1 << hp->io_tlb_shift;
152 hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
153
154 hp->iova_base = HP_ZX1_IOVA_BASE;
155 hp->gart_size = HP_ZX1_GART_SIZE;
156 hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size;
157
158 hp->gatt_entries = hp->gart_size / hp->io_page_size;
159 hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64);
160
161 return 0;
162 }
163
164 static int __init
165 hp_zx1_ioc_init (u64 hpa)
166 {
167 struct _hp_private *hp = &hp_private;
168
169 hp->ioc_regs = ioremap(hpa, 1024);
170 if (!hp->ioc_regs)
171 return -ENOMEM;
172
173 /*
174 * If the IOTLB is currently disabled, we can take it over.
175 * Otherwise, we have to share with sba_iommu.
176 */
177 hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0;
178
179 if (hp->io_pdir_owner)
180 return hp_zx1_ioc_owner();
181
182 return hp_zx1_ioc_shared();
183 }
184
185 static int
186 hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap)
187 {
188 u16 status;
189 u8 pos, id;
190 int ttl = 48;
191
192 status = readw(hpa+PCI_STATUS);
193 if (!(status & PCI_STATUS_CAP_LIST))
194 return 0;
195 pos = readb(hpa+PCI_CAPABILITY_LIST);
196 while (ttl-- && pos >= 0x40) {
197 pos &= ~3;
198 id = readb(hpa+pos+PCI_CAP_LIST_ID);
199 if (id == 0xff)
200 break;
201 if (id == cap)
202 return pos;
203 pos = readb(hpa+pos+PCI_CAP_LIST_NEXT);
204 }
205 return 0;
206 }
207
208 static int __init
209 hp_zx1_lba_init (u64 hpa)
210 {
211 struct _hp_private *hp = &hp_private;
212 int cap;
213
214 hp->lba_regs = ioremap(hpa, 256);
215 if (!hp->lba_regs)
216 return -ENOMEM;
217
218 hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP);
219
220 cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff;
221 if (cap != PCI_CAP_ID_AGP) {
222 printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n",
223 cap, hp->lba_cap_offset);
224 iounmap(hp->lba_regs);
225 return -ENODEV;
226 }
227
228 return 0;
229 }
230
231 static int
232 hp_zx1_fetch_size(void)
233 {
234 int size;
235
236 size = hp_private.gart_size / MB(1);
237 hp_zx1_sizes[0].size = size;
238 agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
239 return size;
240 }
241
242 static int
243 hp_zx1_configure (void)
244 {
245 struct _hp_private *hp = &hp_private;
246
247 agp_bridge->gart_bus_addr = hp->gart_base;
248 agp_bridge->capndx = hp->lba_cap_offset;
249 agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
250
251 if (hp->io_pdir_owner) {
252 writel(virt_to_gart(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE);
253 readl(hp->ioc_regs+HP_ZX1_PDIR_BASE);
254 writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG);
255 readl(hp->ioc_regs+HP_ZX1_TCNFG);
256 writel((unsigned int)(~(HP_ZX1_IOVA_SIZE-1)), hp->ioc_regs+HP_ZX1_IMASK);
257 readl(hp->ioc_regs+HP_ZX1_IMASK);
258 writel(hp->iova_base|1, hp->ioc_regs+HP_ZX1_IBASE);
259 readl(hp->ioc_regs+HP_ZX1_IBASE);
260 writel(hp->iova_base|log2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM);
261 readl(hp->ioc_regs+HP_ZX1_PCOM);
262 }
263
264 return 0;
265 }
266
267 static void
268 hp_zx1_cleanup (void)
269 {
270 struct _hp_private *hp = &hp_private;
271
272 if (hp->ioc_regs) {
273 if (hp->io_pdir_owner) {
274 writeq(0, hp->ioc_regs+HP_ZX1_IBASE);
275 readq(hp->ioc_regs+HP_ZX1_IBASE);
276 }
277 iounmap(hp->ioc_regs);
278 }
279 if (hp->lba_regs)
280 iounmap(hp->lba_regs);
281 }
282
283 static void
284 hp_zx1_tlbflush (struct agp_memory *mem)
285 {
286 struct _hp_private *hp = &hp_private;
287
288 writeq(hp->gart_base | log2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM);
289 readq(hp->ioc_regs+HP_ZX1_PCOM);
290 }
291
292 static int
293 hp_zx1_create_gatt_table (struct agp_bridge_data *bridge)
294 {
295 struct _hp_private *hp = &hp_private;
296 int i;
297
298 if (hp->io_pdir_owner) {
299 hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL,
300 get_order(hp->io_pdir_size));
301 if (!hp->io_pdir) {
302 printk(KERN_ERR PFX "Couldn't allocate contiguous "
303 "memory for I/O PDIR\n");
304 hp->gatt = NULL;
305 hp->gatt_entries = 0;
306 return -ENOMEM;
307 }
308 memset(hp->io_pdir, 0, hp->io_pdir_size);
309
310 hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
311 }
312
313 for (i = 0; i < hp->gatt_entries; i++) {
314 hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
315 }
316
317 return 0;
318 }
319
320 static int
321 hp_zx1_free_gatt_table (struct agp_bridge_data *bridge)
322 {
323 struct _hp_private *hp = &hp_private;
324
325 if (hp->io_pdir_owner)
326 free_pages((unsigned long) hp->io_pdir,
327 get_order(hp->io_pdir_size));
328 else
329 hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE;
330 return 0;
331 }
332
333 static int
334 hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
335 {
336 struct _hp_private *hp = &hp_private;
337 int i, k;
338 off_t j, io_pg_start;
339 int io_pg_count;
340
341 if (type != 0 || mem->type != 0) {
342 return -EINVAL;
343 }
344
345 io_pg_start = hp->io_pages_per_kpage * pg_start;
346 io_pg_count = hp->io_pages_per_kpage * mem->page_count;
347 if ((io_pg_start + io_pg_count) > hp->gatt_entries) {
348 return -EINVAL;
349 }
350
351 j = io_pg_start;
352 while (j < (io_pg_start + io_pg_count)) {
353 if (hp->gatt[j]) {
354 return -EBUSY;
355 }
356 j++;
357 }
358
359 if (mem->is_flushed == FALSE) {
360 global_cache_flush();
361 mem->is_flushed = TRUE;
362 }
363
364 for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
365 unsigned long paddr;
366
367 paddr = mem->memory[i];
368 for (k = 0;
369 k < hp->io_pages_per_kpage;
370 k++, j++, paddr += hp->io_page_size) {
371 hp->gatt[j] =
372 agp_bridge->driver->mask_memory(agp_bridge,
373 paddr, type);
374 }
375 }
376
377 agp_bridge->driver->tlb_flush(mem);
378 return 0;
379 }
380
381 static int
382 hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
383 {
384 struct _hp_private *hp = &hp_private;
385 int i, io_pg_start, io_pg_count;
386
387 if (type != 0 || mem->type != 0) {
388 return -EINVAL;
389 }
390
391 io_pg_start = hp->io_pages_per_kpage * pg_start;
392 io_pg_count = hp->io_pages_per_kpage * mem->page_count;
393 for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
394 hp->gatt[i] = agp_bridge->scratch_page;
395 }
396
397 agp_bridge->driver->tlb_flush(mem);
398 return 0;
399 }
400
401 static unsigned long
402 hp_zx1_mask_memory (struct agp_bridge_data *bridge,
403 unsigned long addr, int type)
404 {
405 return HP_ZX1_PDIR_VALID_BIT | addr;
406 }
407
408 static void
409 hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode)
410 {
411 struct _hp_private *hp = &hp_private;
412 u32 command;
413
414 command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
415 command = agp_collect_device_status(bridge, mode, command);
416 command |= 0x00000100;
417
418 writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);
419
420 agp_device_command(command, (mode & AGP8X_MODE) != 0);
421 }
422
423 const struct agp_bridge_driver hp_zx1_driver = {
424 .owner = THIS_MODULE,
425 .size_type = FIXED_APER_SIZE,
426 .configure = hp_zx1_configure,
427 .fetch_size = hp_zx1_fetch_size,
428 .cleanup = hp_zx1_cleanup,
429 .tlb_flush = hp_zx1_tlbflush,
430 .mask_memory = hp_zx1_mask_memory,
431 .masks = hp_zx1_masks,
432 .agp_enable = hp_zx1_enable,
433 .cache_flush = global_cache_flush,
434 .create_gatt_table = hp_zx1_create_gatt_table,
435 .free_gatt_table = hp_zx1_free_gatt_table,
436 .insert_memory = hp_zx1_insert_memory,
437 .remove_memory = hp_zx1_remove_memory,
438 .alloc_by_type = agp_generic_alloc_by_type,
439 .free_by_type = agp_generic_free_by_type,
440 .agp_alloc_page = agp_generic_alloc_page,
441 .agp_destroy_page = agp_generic_destroy_page,
442 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
443 .cant_use_aperture = 1,
444 };
445
446 static int __init
447 hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa)
448 {
449 struct agp_bridge_data *bridge;
450 int error = 0;
451
452 error = hp_zx1_ioc_init(ioc_hpa);
453 if (error)
454 goto fail;
455
456 error = hp_zx1_lba_init(lba_hpa);
457 if (error)
458 goto fail;
459
460 bridge = agp_alloc_bridge();
461 if (!bridge) {
462 error = -ENOMEM;
463 goto fail;
464 }
465 bridge->driver = &hp_zx1_driver;
466
467 fake_bridge_dev.vendor = PCI_VENDOR_ID_HP;
468 fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA;
469 bridge->dev = &fake_bridge_dev;
470
471 error = agp_add_bridge(bridge);
472 fail:
473 if (error)
474 hp_zx1_cleanup();
475 return error;
476 }
477
478 static acpi_status __init
479 zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret)
480 {
481 acpi_handle handle, parent;
482 acpi_status status;
483 struct acpi_buffer buffer;
484 struct acpi_device_info *info;
485 u64 lba_hpa, sba_hpa, length;
486 int match;
487
488 status = hp_acpi_csr_space(obj, &lba_hpa, &length);
489 if (ACPI_FAILURE(status))
490 return AE_OK; /* keep looking for another bridge */
491
492 /* Look for an enclosing IOC scope and find its CSR space */
493 handle = obj;
494 do {
495 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
496 status = acpi_get_object_info(handle, &buffer);
497 if (ACPI_SUCCESS(status)) {
498 /* TBD check _CID also */
499 info = buffer.pointer;
500 info->hardware_id.value[sizeof(info->hardware_id)-1] = '\0';
501 match = (strcmp(info->hardware_id.value, "HWP0001") == 0);
502 kfree(info);
503 if (match) {
504 status = hp_acpi_csr_space(handle, &sba_hpa, &length);
505 if (ACPI_SUCCESS(status))
506 break;
507 else {
508 printk(KERN_ERR PFX "Detected HP ZX1 "
509 "AGP LBA but no IOC.\n");
510 return AE_OK;
511 }
512 }
513 }
514
515 status = acpi_get_parent(handle, &parent);
516 handle = parent;
517 } while (ACPI_SUCCESS(status));
518
519 if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa))
520 return AE_OK;
521
522 printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset (ioc=%lx, lba=%lx)\n",
523 (char *) context, sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa);
524
525 hp_zx1_gart_found = 1;
526 return AE_CTRL_TERMINATE; /* we only support one bridge; quit looking */
527 }
528
529 static int __init
530 agp_hp_init (void)
531 {
532 if (agp_off)
533 return -EINVAL;
534
535 acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL);
536 if (hp_zx1_gart_found)
537 return 0;
538
539 acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL);
540 if (hp_zx1_gart_found)
541 return 0;
542
543 return -ENODEV;
544 }
545
546 static void __exit
547 agp_hp_cleanup (void)
548 {
549 }
550
551 module_init(agp_hp_init);
552 module_exit(agp_hp_cleanup);
553
554 MODULE_LICENSE("GPL and additional rights");
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