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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / net / arm / ep93xx_eth.c
blob7f016f3d5bf0ea3cd4f7675d50e0dd1c24d8f5f9
1 /*
2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/dma-mapping.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/mii.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/init.h>
20 #include <linux/moduleparam.h>
21 #include <linux/platform_device.h>
22 #include <linux/delay.h>
23 #include <asm/arch/ep93xx-regs.h>
24 #include <asm/arch/platform.h>
25 #include <asm/io.h>
26
27 #define DRV_MODULE_NAME "ep93xx-eth"
28 #define DRV_MODULE_VERSION "0.1"
29
30 #define RX_QUEUE_ENTRIES 64
31 #define TX_QUEUE_ENTRIES 8
32
33 #define MAX_PKT_SIZE 2044
34 #define PKT_BUF_SIZE 2048
35
36 #define REG_RXCTL 0x0000
37 #define REG_RXCTL_DEFAULT 0x00073800
38 #define REG_TXCTL 0x0004
39 #define REG_TXCTL_ENABLE 0x00000001
40 #define REG_MIICMD 0x0010
41 #define REG_MIICMD_READ 0x00008000
42 #define REG_MIICMD_WRITE 0x00004000
43 #define REG_MIIDATA 0x0014
44 #define REG_MIISTS 0x0018
45 #define REG_MIISTS_BUSY 0x00000001
46 #define REG_SELFCTL 0x0020
47 #define REG_SELFCTL_RESET 0x00000001
48 #define REG_INTEN 0x0024
49 #define REG_INTEN_TX 0x00000008
50 #define REG_INTEN_RX 0x00000007
51 #define REG_INTSTSP 0x0028
52 #define REG_INTSTS_TX 0x00000008
53 #define REG_INTSTS_RX 0x00000004
54 #define REG_INTSTSC 0x002c
55 #define REG_AFP 0x004c
56 #define REG_INDAD0 0x0050
57 #define REG_INDAD1 0x0051
58 #define REG_INDAD2 0x0052
59 #define REG_INDAD3 0x0053
60 #define REG_INDAD4 0x0054
61 #define REG_INDAD5 0x0055
62 #define REG_GIINTMSK 0x0064
63 #define REG_GIINTMSK_ENABLE 0x00008000
64 #define REG_BMCTL 0x0080
65 #define REG_BMCTL_ENABLE_TX 0x00000100
66 #define REG_BMCTL_ENABLE_RX 0x00000001
67 #define REG_BMSTS 0x0084
68 #define REG_BMSTS_RX_ACTIVE 0x00000008
69 #define REG_RXDQBADD 0x0090
70 #define REG_RXDQBLEN 0x0094
71 #define REG_RXDCURADD 0x0098
72 #define REG_RXDENQ 0x009c
73 #define REG_RXSTSQBADD 0x00a0
74 #define REG_RXSTSQBLEN 0x00a4
75 #define REG_RXSTSQCURADD 0x00a8
76 #define REG_RXSTSENQ 0x00ac
77 #define REG_TXDQBADD 0x00b0
78 #define REG_TXDQBLEN 0x00b4
79 #define REG_TXDQCURADD 0x00b8
80 #define REG_TXDENQ 0x00bc
81 #define REG_TXSTSQBADD 0x00c0
82 #define REG_TXSTSQBLEN 0x00c4
83 #define REG_TXSTSQCURADD 0x00c8
84 #define REG_MAXFRMLEN 0x00e8
85
86 struct ep93xx_rdesc
87 {
88 u32 buf_addr;
89 u32 rdesc1;
90 };
91
92 #define RDESC1_NSOF 0x80000000
93 #define RDESC1_BUFFER_INDEX 0x7fff0000
94 #define RDESC1_BUFFER_LENGTH 0x0000ffff
95
96 struct ep93xx_rstat
97 {
98 u32 rstat0;
99 u32 rstat1;
100 };
101
102 #define RSTAT0_RFP 0x80000000
103 #define RSTAT0_RWE 0x40000000
104 #define RSTAT0_EOF 0x20000000
105 #define RSTAT0_EOB 0x10000000
106 #define RSTAT0_AM 0x00c00000
107 #define RSTAT0_RX_ERR 0x00200000
108 #define RSTAT0_OE 0x00100000
109 #define RSTAT0_FE 0x00080000
110 #define RSTAT0_RUNT 0x00040000
111 #define RSTAT0_EDATA 0x00020000
112 #define RSTAT0_CRCE 0x00010000
113 #define RSTAT0_CRCI 0x00008000
114 #define RSTAT0_HTI 0x00003f00
115 #define RSTAT1_RFP 0x80000000
116 #define RSTAT1_BUFFER_INDEX 0x7fff0000
117 #define RSTAT1_FRAME_LENGTH 0x0000ffff
118
119 struct ep93xx_tdesc
120 {
121 u32 buf_addr;
122 u32 tdesc1;
123 };
124
125 #define TDESC1_EOF 0x80000000
126 #define TDESC1_BUFFER_INDEX 0x7fff0000
127 #define TDESC1_BUFFER_ABORT 0x00008000
128 #define TDESC1_BUFFER_LENGTH 0x00000fff
129
130 struct ep93xx_tstat
131 {
132 u32 tstat0;
133 };
134
135 #define TSTAT0_TXFP 0x80000000
136 #define TSTAT0_TXWE 0x40000000
137 #define TSTAT0_FA 0x20000000
138 #define TSTAT0_LCRS 0x10000000
139 #define TSTAT0_OW 0x04000000
140 #define TSTAT0_TXU 0x02000000
141 #define TSTAT0_ECOLL 0x01000000
142 #define TSTAT0_NCOLL 0x001f0000
143 #define TSTAT0_BUFFER_INDEX 0x00007fff
144
145 struct ep93xx_descs
146 {
147 struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
148 struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
149 struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
150 struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
151 };
152
153 struct ep93xx_priv
154 {
155 struct resource *res;
156 void *base_addr;
157 int irq;
158
159 struct ep93xx_descs *descs;
160 dma_addr_t descs_dma_addr;
161
162 void *rx_buf[RX_QUEUE_ENTRIES];
163 void *tx_buf[TX_QUEUE_ENTRIES];
164
165 spinlock_t rx_lock;
166 unsigned int rx_pointer;
167 unsigned int tx_clean_pointer;
168 unsigned int tx_pointer;
169 spinlock_t tx_pending_lock;
170 unsigned int tx_pending;
171
172 struct net_device *dev;
173 struct napi_struct napi;
174
175 struct net_device_stats stats;
176
177 struct mii_if_info mii;
178 u8 mdc_divisor;
179 };
180
181 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
182 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
183 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
184 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
185 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
186 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
187
188 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg);
189
190 static struct net_device_stats *ep93xx_get_stats(struct net_device *dev)
191 {
192 struct ep93xx_priv *ep = netdev_priv(dev);
193 return &(ep->stats);
194 }
195
196 static int ep93xx_rx(struct net_device *dev, int processed, int budget)
197 {
198 struct ep93xx_priv *ep = netdev_priv(dev);
199
200 while (processed < budget) {
201 int entry;
202 struct ep93xx_rstat *rstat;
203 u32 rstat0;
204 u32 rstat1;
205 int length;
206 struct sk_buff *skb;
207
208 entry = ep->rx_pointer;
209 rstat = ep->descs->rstat + entry;
210
211 rstat0 = rstat->rstat0;
212 rstat1 = rstat->rstat1;
213 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
214 break;
215
216 rstat->rstat0 = 0;
217 rstat->rstat1 = 0;
218
219 if (!(rstat0 & RSTAT0_EOF))
220 printk(KERN_CRIT "ep93xx_rx: not end-of-frame "
221 " %.8x %.8x\n", rstat0, rstat1);
222 if (!(rstat0 & RSTAT0_EOB))
223 printk(KERN_CRIT "ep93xx_rx: not end-of-buffer "
224 " %.8x %.8x\n", rstat0, rstat1);
225 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
226 printk(KERN_CRIT "ep93xx_rx: entry mismatch "
227 " %.8x %.8x\n", rstat0, rstat1);
228
229 if (!(rstat0 & RSTAT0_RWE)) {
230 ep->stats.rx_errors++;
231 if (rstat0 & RSTAT0_OE)
232 ep->stats.rx_fifo_errors++;
233 if (rstat0 & RSTAT0_FE)
234 ep->stats.rx_frame_errors++;
235 if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
236 ep->stats.rx_length_errors++;
237 if (rstat0 & RSTAT0_CRCE)
238 ep->stats.rx_crc_errors++;
239 goto err;
240 }
241
242 length = rstat1 & RSTAT1_FRAME_LENGTH;
243 if (length > MAX_PKT_SIZE) {
244 printk(KERN_NOTICE "ep93xx_rx: invalid length "
245 " %.8x %.8x\n", rstat0, rstat1);
246 goto err;
247 }
248
249 /* Strip FCS. */
250 if (rstat0 & RSTAT0_CRCI)
251 length -= 4;
252
253 skb = dev_alloc_skb(length + 2);
254 if (likely(skb != NULL)) {
255 skb_reserve(skb, 2);
256 dma_sync_single(NULL, ep->descs->rdesc[entry].buf_addr,
257 length, DMA_FROM_DEVICE);
258 skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
259 skb_put(skb, length);
260 skb->protocol = eth_type_trans(skb, dev);
261
262 dev->last_rx = jiffies;
263
264 netif_receive_skb(skb);
265
266 ep->stats.rx_packets++;
267 ep->stats.rx_bytes += length;
268 } else {
269 ep->stats.rx_dropped++;
270 }
271
272 err:
273 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
274 processed++;
275 }
276
277 if (processed) {
278 wrw(ep, REG_RXDENQ, processed);
279 wrw(ep, REG_RXSTSENQ, processed);
280 }
281
282 return processed;
283 }
284
285 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
286 {
287 struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
288 return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
289 }
290
291 static int ep93xx_poll(struct napi_struct *napi, int budget)
292 {
293 struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
294 struct net_device *dev = ep->dev;
295 int rx = 0;
296
297 poll_some_more:
298 rx = ep93xx_rx(dev, rx, budget);
299 if (rx < budget) {
300 int more = 0;
301
302 spin_lock_irq(&ep->rx_lock);
303 __netif_rx_complete(dev, napi);
304 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
305 if (ep93xx_have_more_rx(ep)) {
306 wrl(ep, REG_INTEN, REG_INTEN_TX);
307 wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
308 more = 1;
309 }
310 spin_unlock_irq(&ep->rx_lock);
311
312 if (more && netif_rx_reschedule(dev, napi))
313 goto poll_some_more;
314 }
315
316 return rx;
317 }
318
319 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
320 {
321 struct ep93xx_priv *ep = netdev_priv(dev);
322 int entry;
323
324 if (unlikely(skb->len > MAX_PKT_SIZE)) {
325 ep->stats.tx_dropped++;
326 dev_kfree_skb(skb);
327 return NETDEV_TX_OK;
328 }
329
330 entry = ep->tx_pointer;
331 ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
332
333 ep->descs->tdesc[entry].tdesc1 =
334 TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
335 skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
336 dma_sync_single(NULL, ep->descs->tdesc[entry].buf_addr,
337 skb->len, DMA_TO_DEVICE);
338 dev_kfree_skb(skb);
339
340 dev->trans_start = jiffies;
341
342 spin_lock_irq(&ep->tx_pending_lock);
343 ep->tx_pending++;
344 if (ep->tx_pending == TX_QUEUE_ENTRIES)
345 netif_stop_queue(dev);
346 spin_unlock_irq(&ep->tx_pending_lock);
347
348 wrl(ep, REG_TXDENQ, 1);
349
350 return NETDEV_TX_OK;
351 }
352
353 static void ep93xx_tx_complete(struct net_device *dev)
354 {
355 struct ep93xx_priv *ep = netdev_priv(dev);
356 int wake;
357
358 wake = 0;
359
360 spin_lock(&ep->tx_pending_lock);
361 while (1) {
362 int entry;
363 struct ep93xx_tstat *tstat;
364 u32 tstat0;
365
366 entry = ep->tx_clean_pointer;
367 tstat = ep->descs->tstat + entry;
368
369 tstat0 = tstat->tstat0;
370 if (!(tstat0 & TSTAT0_TXFP))
371 break;
372
373 tstat->tstat0 = 0;
374
375 if (tstat0 & TSTAT0_FA)
376 printk(KERN_CRIT "ep93xx_tx_complete: frame aborted "
377 " %.8x\n", tstat0);
378 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
379 printk(KERN_CRIT "ep93xx_tx_complete: entry mismatch "
380 " %.8x\n", tstat0);
381
382 if (tstat0 & TSTAT0_TXWE) {
383 int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
384
385 ep->stats.tx_packets++;
386 ep->stats.tx_bytes += length;
387 } else {
388 ep->stats.tx_errors++;
389 }
390
391 if (tstat0 & TSTAT0_OW)
392 ep->stats.tx_window_errors++;
393 if (tstat0 & TSTAT0_TXU)
394 ep->stats.tx_fifo_errors++;
395 ep->stats.collisions += (tstat0 >> 16) & 0x1f;
396
397 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
398 if (ep->tx_pending == TX_QUEUE_ENTRIES)
399 wake = 1;
400 ep->tx_pending--;
401 }
402 spin_unlock(&ep->tx_pending_lock);
403
404 if (wake)
405 netif_wake_queue(dev);
406 }
407
408 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
409 {
410 struct net_device *dev = dev_id;
411 struct ep93xx_priv *ep = netdev_priv(dev);
412 u32 status;
413
414 status = rdl(ep, REG_INTSTSC);
415 if (status == 0)
416 return IRQ_NONE;
417
418 if (status & REG_INTSTS_RX) {
419 spin_lock(&ep->rx_lock);
420 if (likely(__netif_rx_schedule_prep(dev, &ep->napi))) {
421 wrl(ep, REG_INTEN, REG_INTEN_TX);
422 __netif_rx_schedule(dev, &ep->napi);
423 }
424 spin_unlock(&ep->rx_lock);
425 }
426
427 if (status & REG_INTSTS_TX)
428 ep93xx_tx_complete(dev);
429
430 return IRQ_HANDLED;
431 }
432
433 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
434 {
435 int i;
436
437 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
438 dma_addr_t d;
439
440 d = ep->descs->rdesc[i].buf_addr;
441 if (d)
442 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE);
443
444 if (ep->rx_buf[i] != NULL)
445 free_page((unsigned long)ep->rx_buf[i]);
446 }
447
448 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
449 dma_addr_t d;
450
451 d = ep->descs->tdesc[i].buf_addr;
452 if (d)
453 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE);
454
455 if (ep->tx_buf[i] != NULL)
456 free_page((unsigned long)ep->tx_buf[i]);
457 }
458
459 dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs,
460 ep->descs_dma_addr);
461 }
462
463 /*
464 * The hardware enforces a sub-2K maximum packet size, so we put
465 * two buffers on every hardware page.
466 */
467 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
468 {
469 int i;
470
471 ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs),
472 &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA);
473 if (ep->descs == NULL)
474 return 1;
475
476 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
477 void *page;
478 dma_addr_t d;
479
480 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
481 if (page == NULL)
482 goto err;
483
484 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE);
485 if (dma_mapping_error(d)) {
486 free_page((unsigned long)page);
487 goto err;
488 }
489
490 ep->rx_buf[i] = page;
491 ep->descs->rdesc[i].buf_addr = d;
492 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
493
494 ep->rx_buf[i + 1] = page + PKT_BUF_SIZE;
495 ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
496 ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE;
497 }
498
499 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
500 void *page;
501 dma_addr_t d;
502
503 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
504 if (page == NULL)
505 goto err;
506
507 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE);
508 if (dma_mapping_error(d)) {
509 free_page((unsigned long)page);
510 goto err;
511 }
512
513 ep->tx_buf[i] = page;
514 ep->descs->tdesc[i].buf_addr = d;
515
516 ep->tx_buf[i + 1] = page + PKT_BUF_SIZE;
517 ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
518 }
519
520 return 0;
521
522 err:
523 ep93xx_free_buffers(ep);
524 return 1;
525 }
526
527 static int ep93xx_start_hw(struct net_device *dev)
528 {
529 struct ep93xx_priv *ep = netdev_priv(dev);
530 unsigned long addr;
531 int i;
532
533 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
534 for (i = 0; i < 10; i++) {
535 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
536 break;
537 msleep(1);
538 }
539
540 if (i == 10) {
541 printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to reset\n");
542 return 1;
543 }
544
545 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
546
547 /* Does the PHY support preamble suppress? */
548 if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
549 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
550
551 /* Receive descriptor ring. */
552 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
553 wrl(ep, REG_RXDQBADD, addr);
554 wrl(ep, REG_RXDCURADD, addr);
555 wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
556
557 /* Receive status ring. */
558 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
559 wrl(ep, REG_RXSTSQBADD, addr);
560 wrl(ep, REG_RXSTSQCURADD, addr);
561 wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
562
563 /* Transmit descriptor ring. */
564 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
565 wrl(ep, REG_TXDQBADD, addr);
566 wrl(ep, REG_TXDQCURADD, addr);
567 wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
568
569 /* Transmit status ring. */
570 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
571 wrl(ep, REG_TXSTSQBADD, addr);
572 wrl(ep, REG_TXSTSQCURADD, addr);
573 wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
574
575 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
576 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
577 wrl(ep, REG_GIINTMSK, 0);
578
579 for (i = 0; i < 10; i++) {
580 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
581 break;
582 msleep(1);
583 }
584
585 if (i == 10) {
586 printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to start\n");
587 return 1;
588 }
589
590 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
591 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
592
593 wrb(ep, REG_INDAD0, dev->dev_addr[0]);
594 wrb(ep, REG_INDAD1, dev->dev_addr[1]);
595 wrb(ep, REG_INDAD2, dev->dev_addr[2]);
596 wrb(ep, REG_INDAD3, dev->dev_addr[3]);
597 wrb(ep, REG_INDAD4, dev->dev_addr[4]);
598 wrb(ep, REG_INDAD5, dev->dev_addr[5]);
599 wrl(ep, REG_AFP, 0);
600
601 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
602
603 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
604 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
605
606 return 0;
607 }
608
609 static void ep93xx_stop_hw(struct net_device *dev)
610 {
611 struct ep93xx_priv *ep = netdev_priv(dev);
612 int i;
613
614 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
615 for (i = 0; i < 10; i++) {
616 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
617 break;
618 msleep(1);
619 }
620
621 if (i == 10)
622 printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to reset\n");
623 }
624
625 static int ep93xx_open(struct net_device *dev)
626 {
627 struct ep93xx_priv *ep = netdev_priv(dev);
628 int err;
629
630 if (ep93xx_alloc_buffers(ep))
631 return -ENOMEM;
632
633 if (is_zero_ether_addr(dev->dev_addr)) {
634 random_ether_addr(dev->dev_addr);
635 printk(KERN_INFO "%s: generated random MAC address "
636 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev->name,
637 dev->dev_addr[0], dev->dev_addr[1],
638 dev->dev_addr[2], dev->dev_addr[3],
639 dev->dev_addr[4], dev->dev_addr[5]);
640 }
641
642 napi_enable(&ep->napi);
643
644 if (ep93xx_start_hw(dev)) {
645 napi_disable(&ep->napi);
646 ep93xx_free_buffers(ep);
647 return -EIO;
648 }
649
650 spin_lock_init(&ep->rx_lock);
651 ep->rx_pointer = 0;
652 ep->tx_clean_pointer = 0;
653 ep->tx_pointer = 0;
654 spin_lock_init(&ep->tx_pending_lock);
655 ep->tx_pending = 0;
656
657 err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
658 if (err) {
659 napi_disable(&ep->napi);
660 ep93xx_stop_hw(dev);
661 ep93xx_free_buffers(ep);
662 return err;
663 }
664
665 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
666
667 netif_start_queue(dev);
668
669 return 0;
670 }
671
672 static int ep93xx_close(struct net_device *dev)
673 {
674 struct ep93xx_priv *ep = netdev_priv(dev);
675
676 napi_disable(&ep->napi);
677 netif_stop_queue(dev);
678
679 wrl(ep, REG_GIINTMSK, 0);
680 free_irq(ep->irq, dev);
681 ep93xx_stop_hw(dev);
682 ep93xx_free_buffers(ep);
683
684 return 0;
685 }
686
687 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
688 {
689 struct ep93xx_priv *ep = netdev_priv(dev);
690 struct mii_ioctl_data *data = if_mii(ifr);
691
692 return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
693 }
694
695 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
696 {
697 struct ep93xx_priv *ep = netdev_priv(dev);
698 int data;
699 int i;
700
701 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
702
703 for (i = 0; i < 10; i++) {
704 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
705 break;
706 msleep(1);
707 }
708
709 if (i == 10) {
710 printk(KERN_INFO DRV_MODULE_NAME ": mdio read timed out\n");
711 data = 0xffff;
712 } else {
713 data = rdl(ep, REG_MIIDATA);
714 }
715
716 return data;
717 }
718
719 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
720 {
721 struct ep93xx_priv *ep = netdev_priv(dev);
722 int i;
723
724 wrl(ep, REG_MIIDATA, data);
725 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
726
727 for (i = 0; i < 10; i++) {
728 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
729 break;
730 msleep(1);
731 }
732
733 if (i == 10)
734 printk(KERN_INFO DRV_MODULE_NAME ": mdio write timed out\n");
735 }
736
737 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
738 {
739 strcpy(info->driver, DRV_MODULE_NAME);
740 strcpy(info->version, DRV_MODULE_VERSION);
741 }
742
743 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
744 {
745 struct ep93xx_priv *ep = netdev_priv(dev);
746 return mii_ethtool_gset(&ep->mii, cmd);
747 }
748
749 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
750 {
751 struct ep93xx_priv *ep = netdev_priv(dev);
752 return mii_ethtool_sset(&ep->mii, cmd);
753 }
754
755 static int ep93xx_nway_reset(struct net_device *dev)
756 {
757 struct ep93xx_priv *ep = netdev_priv(dev);
758 return mii_nway_restart(&ep->mii);
759 }
760
761 static u32 ep93xx_get_link(struct net_device *dev)
762 {
763 struct ep93xx_priv *ep = netdev_priv(dev);
764 return mii_link_ok(&ep->mii);
765 }
766
767 static struct ethtool_ops ep93xx_ethtool_ops = {
768 .get_drvinfo = ep93xx_get_drvinfo,
769 .get_settings = ep93xx_get_settings,
770 .set_settings = ep93xx_set_settings,
771 .nway_reset = ep93xx_nway_reset,
772 .get_link = ep93xx_get_link,
773 };
774
775 struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
776 {
777 struct net_device *dev;
778
779 dev = alloc_etherdev(sizeof(struct ep93xx_priv));
780 if (dev == NULL)
781 return NULL;
782
783 memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
784
785 dev->get_stats = ep93xx_get_stats;
786 dev->ethtool_ops = &ep93xx_ethtool_ops;
787 dev->hard_start_xmit = ep93xx_xmit;
788 dev->open = ep93xx_open;
789 dev->stop = ep93xx_close;
790 dev->do_ioctl = ep93xx_ioctl;
791
792 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
793
794 return dev;
795 }
796
797
798 static int ep93xx_eth_remove(struct platform_device *pdev)
799 {
800 struct net_device *dev;
801 struct ep93xx_priv *ep;
802
803 dev = platform_get_drvdata(pdev);
804 if (dev == NULL)
805 return 0;
806 platform_set_drvdata(pdev, NULL);
807
808 ep = netdev_priv(dev);
809
810 /* @@@ Force down. */
811 unregister_netdev(dev);
812 ep93xx_free_buffers(ep);
813
814 if (ep->base_addr != NULL)
815 iounmap(ep->base_addr);
816
817 if (ep->res != NULL) {
818 release_resource(ep->res);
819 kfree(ep->res);
820 }
821
822 free_netdev(dev);
823
824 return 0;
825 }
826
827 static int ep93xx_eth_probe(struct platform_device *pdev)
828 {
829 struct ep93xx_eth_data *data;
830 struct net_device *dev;
831 struct ep93xx_priv *ep;
832 int err;
833
834 if (pdev == NULL)
835 return -ENODEV;
836 data = pdev->dev.platform_data;
837
838 dev = ep93xx_dev_alloc(data);
839 if (dev == NULL) {
840 err = -ENOMEM;
841 goto err_out;
842 }
843 ep = netdev_priv(dev);
844 ep->dev = dev;
845 netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
846
847 platform_set_drvdata(pdev, dev);
848
849 ep->res = request_mem_region(pdev->resource[0].start,
850 pdev->resource[0].end - pdev->resource[0].start + 1,
851 pdev->dev.bus_id);
852 if (ep->res == NULL) {
853 dev_err(&pdev->dev, "Could not reserve memory region\n");
854 err = -ENOMEM;
855 goto err_out;
856 }
857
858 ep->base_addr = ioremap(pdev->resource[0].start,
859 pdev->resource[0].end - pdev->resource[0].start);
860 if (ep->base_addr == NULL) {
861 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
862 err = -EIO;
863 goto err_out;
864 }
865 ep->irq = pdev->resource[1].start;
866
867 ep->mii.phy_id = data->phy_id;
868 ep->mii.phy_id_mask = 0x1f;
869 ep->mii.reg_num_mask = 0x1f;
870 ep->mii.dev = dev;
871 ep->mii.mdio_read = ep93xx_mdio_read;
872 ep->mii.mdio_write = ep93xx_mdio_write;
873 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
874
875 err = register_netdev(dev);
876 if (err) {
877 dev_err(&pdev->dev, "Failed to register netdev\n");
878 goto err_out;
879 }
880
881 printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, "
882 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev->name,
883 ep->irq, data->dev_addr[0], data->dev_addr[1],
884 data->dev_addr[2], data->dev_addr[3],
885 data->dev_addr[4], data->dev_addr[5]);
886
887 return 0;
888
889 err_out:
890 ep93xx_eth_remove(pdev);
891 return err;
892 }
893
894
895 static struct platform_driver ep93xx_eth_driver = {
896 .probe = ep93xx_eth_probe,
897 .remove = ep93xx_eth_remove,
898 .driver = {
899 .name = "ep93xx-eth",
900 },
901 };
902
903 static int __init ep93xx_eth_init_module(void)
904 {
905 printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
906 return platform_driver_register(&ep93xx_eth_driver);
907 }
908
909 static void __exit ep93xx_eth_cleanup_module(void)
910 {
911 platform_driver_unregister(&ep93xx_eth_driver);
912 }
913
914 module_init(ep93xx_eth_init_module);
915 module_exit(ep93xx_eth_cleanup_module);
916 MODULE_LICENSE("GPL");
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