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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / net / s2io.c
blob22e4054d4fcb249feac3331eab47b544f85920a8
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 ************************************************************************/
54
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/stddef.h>
68 #include <linux/ioctl.h>
69 #include <linux/timex.h>
70 #include <linux/ethtool.h>
71 #include <linux/workqueue.h>
72 #include <linux/if_vlan.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <net/tcp.h>
76
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
79 #include <asm/io.h>
80 #include <asm/div64.h>
81 #include <asm/irq.h>
82
83 /* local include */
84 #include "s2io.h"
85 #include "s2io-regs.h"
86
87 #define DRV_VERSION "2.0.26.5"
88
89 /* S2io Driver name & version. */
90 static char s2io_driver_name[] = "Neterion";
91 static char s2io_driver_version[] = DRV_VERSION;
92
93 static int rxd_size[2] = {32,48};
94 static int rxd_count[2] = {127,85};
95
96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
97 {
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104 }
105
106 /*
107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
115
116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119 #define PANIC 1
120 #define LOW 2
121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
122 {
123 struct mac_info *mac_control;
124
125 mac_control = &sp->mac_control;
126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
131 }
132
133 static inline int is_s2io_card_up(const struct s2io_nic * sp)
134 {
135 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
136 }
137
138 /* Ethtool related variables and Macros. */
139 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
140 "Register test\t(offline)",
141 "Eeprom test\t(offline)",
142 "Link test\t(online)",
143 "RLDRAM test\t(offline)",
144 "BIST Test\t(offline)"
145 };
146
147 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
148 {"tmac_frms"},
149 {"tmac_data_octets"},
150 {"tmac_drop_frms"},
151 {"tmac_mcst_frms"},
152 {"tmac_bcst_frms"},
153 {"tmac_pause_ctrl_frms"},
154 {"tmac_ttl_octets"},
155 {"tmac_ucst_frms"},
156 {"tmac_nucst_frms"},
157 {"tmac_any_err_frms"},
158 {"tmac_ttl_less_fb_octets"},
159 {"tmac_vld_ip_octets"},
160 {"tmac_vld_ip"},
161 {"tmac_drop_ip"},
162 {"tmac_icmp"},
163 {"tmac_rst_tcp"},
164 {"tmac_tcp"},
165 {"tmac_udp"},
166 {"rmac_vld_frms"},
167 {"rmac_data_octets"},
168 {"rmac_fcs_err_frms"},
169 {"rmac_drop_frms"},
170 {"rmac_vld_mcst_frms"},
171 {"rmac_vld_bcst_frms"},
172 {"rmac_in_rng_len_err_frms"},
173 {"rmac_out_rng_len_err_frms"},
174 {"rmac_long_frms"},
175 {"rmac_pause_ctrl_frms"},
176 {"rmac_unsup_ctrl_frms"},
177 {"rmac_ttl_octets"},
178 {"rmac_accepted_ucst_frms"},
179 {"rmac_accepted_nucst_frms"},
180 {"rmac_discarded_frms"},
181 {"rmac_drop_events"},
182 {"rmac_ttl_less_fb_octets"},
183 {"rmac_ttl_frms"},
184 {"rmac_usized_frms"},
185 {"rmac_osized_frms"},
186 {"rmac_frag_frms"},
187 {"rmac_jabber_frms"},
188 {"rmac_ttl_64_frms"},
189 {"rmac_ttl_65_127_frms"},
190 {"rmac_ttl_128_255_frms"},
191 {"rmac_ttl_256_511_frms"},
192 {"rmac_ttl_512_1023_frms"},
193 {"rmac_ttl_1024_1518_frms"},
194 {"rmac_ip"},
195 {"rmac_ip_octets"},
196 {"rmac_hdr_err_ip"},
197 {"rmac_drop_ip"},
198 {"rmac_icmp"},
199 {"rmac_tcp"},
200 {"rmac_udp"},
201 {"rmac_err_drp_udp"},
202 {"rmac_xgmii_err_sym"},
203 {"rmac_frms_q0"},
204 {"rmac_frms_q1"},
205 {"rmac_frms_q2"},
206 {"rmac_frms_q3"},
207 {"rmac_frms_q4"},
208 {"rmac_frms_q5"},
209 {"rmac_frms_q6"},
210 {"rmac_frms_q7"},
211 {"rmac_full_q0"},
212 {"rmac_full_q1"},
213 {"rmac_full_q2"},
214 {"rmac_full_q3"},
215 {"rmac_full_q4"},
216 {"rmac_full_q5"},
217 {"rmac_full_q6"},
218 {"rmac_full_q7"},
219 {"rmac_pause_cnt"},
220 {"rmac_xgmii_data_err_cnt"},
221 {"rmac_xgmii_ctrl_err_cnt"},
222 {"rmac_accepted_ip"},
223 {"rmac_err_tcp"},
224 {"rd_req_cnt"},
225 {"new_rd_req_cnt"},
226 {"new_rd_req_rtry_cnt"},
227 {"rd_rtry_cnt"},
228 {"wr_rtry_rd_ack_cnt"},
229 {"wr_req_cnt"},
230 {"new_wr_req_cnt"},
231 {"new_wr_req_rtry_cnt"},
232 {"wr_rtry_cnt"},
233 {"wr_disc_cnt"},
234 {"rd_rtry_wr_ack_cnt"},
235 {"txp_wr_cnt"},
236 {"txd_rd_cnt"},
237 {"txd_wr_cnt"},
238 {"rxd_rd_cnt"},
239 {"rxd_wr_cnt"},
240 {"txf_rd_cnt"},
241 {"rxf_wr_cnt"}
242 };
243
244 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
245 {"rmac_ttl_1519_4095_frms"},
246 {"rmac_ttl_4096_8191_frms"},
247 {"rmac_ttl_8192_max_frms"},
248 {"rmac_ttl_gt_max_frms"},
249 {"rmac_osized_alt_frms"},
250 {"rmac_jabber_alt_frms"},
251 {"rmac_gt_max_alt_frms"},
252 {"rmac_vlan_frms"},
253 {"rmac_len_discard"},
254 {"rmac_fcs_discard"},
255 {"rmac_pf_discard"},
256 {"rmac_da_discard"},
257 {"rmac_red_discard"},
258 {"rmac_rts_discard"},
259 {"rmac_ingm_full_discard"},
260 {"link_fault_cnt"}
261 };
262
263 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
264 {"\n DRIVER STATISTICS"},
265 {"single_bit_ecc_errs"},
266 {"double_bit_ecc_errs"},
267 {"parity_err_cnt"},
268 {"serious_err_cnt"},
269 {"soft_reset_cnt"},
270 {"fifo_full_cnt"},
271 {"ring_0_full_cnt"},
272 {"ring_1_full_cnt"},
273 {"ring_2_full_cnt"},
274 {"ring_3_full_cnt"},
275 {"ring_4_full_cnt"},
276 {"ring_5_full_cnt"},
277 {"ring_6_full_cnt"},
278 {"ring_7_full_cnt"},
279 {"alarm_transceiver_temp_high"},
280 {"alarm_transceiver_temp_low"},
281 {"alarm_laser_bias_current_high"},
282 {"alarm_laser_bias_current_low"},
283 {"alarm_laser_output_power_high"},
284 {"alarm_laser_output_power_low"},
285 {"warn_transceiver_temp_high"},
286 {"warn_transceiver_temp_low"},
287 {"warn_laser_bias_current_high"},
288 {"warn_laser_bias_current_low"},
289 {"warn_laser_output_power_high"},
290 {"warn_laser_output_power_low"},
291 {"lro_aggregated_pkts"},
292 {"lro_flush_both_count"},
293 {"lro_out_of_sequence_pkts"},
294 {"lro_flush_due_to_max_pkts"},
295 {"lro_avg_aggr_pkts"},
296 {"mem_alloc_fail_cnt"},
297 {"pci_map_fail_cnt"},
298 {"watchdog_timer_cnt"},
299 {"mem_allocated"},
300 {"mem_freed"},
301 {"link_up_cnt"},
302 {"link_down_cnt"},
303 {"link_up_time"},
304 {"link_down_time"},
305 {"tx_tcode_buf_abort_cnt"},
306 {"tx_tcode_desc_abort_cnt"},
307 {"tx_tcode_parity_err_cnt"},
308 {"tx_tcode_link_loss_cnt"},
309 {"tx_tcode_list_proc_err_cnt"},
310 {"rx_tcode_parity_err_cnt"},
311 {"rx_tcode_abort_cnt"},
312 {"rx_tcode_parity_abort_cnt"},
313 {"rx_tcode_rda_fail_cnt"},
314 {"rx_tcode_unkn_prot_cnt"},
315 {"rx_tcode_fcs_err_cnt"},
316 {"rx_tcode_buf_size_err_cnt"},
317 {"rx_tcode_rxd_corrupt_cnt"},
318 {"rx_tcode_unkn_err_cnt"},
319 {"tda_err_cnt"},
320 {"pfc_err_cnt"},
321 {"pcc_err_cnt"},
322 {"tti_err_cnt"},
323 {"tpa_err_cnt"},
324 {"sm_err_cnt"},
325 {"lso_err_cnt"},
326 {"mac_tmac_err_cnt"},
327 {"mac_rmac_err_cnt"},
328 {"xgxs_txgxs_err_cnt"},
329 {"xgxs_rxgxs_err_cnt"},
330 {"rc_err_cnt"},
331 {"prc_pcix_err_cnt"},
332 {"rpa_err_cnt"},
333 {"rda_err_cnt"},
334 {"rti_err_cnt"},
335 {"mc_err_cnt"}
336 };
337
338 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
339 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
340 ETH_GSTRING_LEN
341 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
342
343 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
344 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
345
346 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
347 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
348
349 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
350 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
351
352 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
353 init_timer(&timer); \
354 timer.function = handle; \
355 timer.data = (unsigned long) arg; \
356 mod_timer(&timer, (jiffies + exp)) \
357
358 /* copy mac addr to def_mac_addr array */
359 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
360 {
361 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
362 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
363 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
364 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
365 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
366 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
367 }
368 /* Add the vlan */
369 static void s2io_vlan_rx_register(struct net_device *dev,
370 struct vlan_group *grp)
371 {
372 struct s2io_nic *nic = dev->priv;
373 unsigned long flags;
374
375 spin_lock_irqsave(&nic->tx_lock, flags);
376 nic->vlgrp = grp;
377 spin_unlock_irqrestore(&nic->tx_lock, flags);
378 }
379
380 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
381 static int vlan_strip_flag;
382
383 /*
384 * Constants to be programmed into the Xena's registers, to configure
385 * the XAUI.
386 */
387
388 #define END_SIGN 0x0
389 static const u64 herc_act_dtx_cfg[] = {
390 /* Set address */
391 0x8000051536750000ULL, 0x80000515367500E0ULL,
392 /* Write data */
393 0x8000051536750004ULL, 0x80000515367500E4ULL,
394 /* Set address */
395 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
396 /* Write data */
397 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
398 /* Set address */
399 0x801205150D440000ULL, 0x801205150D4400E0ULL,
400 /* Write data */
401 0x801205150D440004ULL, 0x801205150D4400E4ULL,
402 /* Set address */
403 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
404 /* Write data */
405 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
406 /* Done */
407 END_SIGN
408 };
409
410 static const u64 xena_dtx_cfg[] = {
411 /* Set address */
412 0x8000051500000000ULL, 0x80000515000000E0ULL,
413 /* Write data */
414 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
415 /* Set address */
416 0x8001051500000000ULL, 0x80010515000000E0ULL,
417 /* Write data */
418 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
419 /* Set address */
420 0x8002051500000000ULL, 0x80020515000000E0ULL,
421 /* Write data */
422 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
423 END_SIGN
424 };
425
426 /*
427 * Constants for Fixing the MacAddress problem seen mostly on
428 * Alpha machines.
429 */
430 static const u64 fix_mac[] = {
431 0x0060000000000000ULL, 0x0060600000000000ULL,
432 0x0040600000000000ULL, 0x0000600000000000ULL,
433 0x0020600000000000ULL, 0x0060600000000000ULL,
434 0x0020600000000000ULL, 0x0060600000000000ULL,
435 0x0020600000000000ULL, 0x0060600000000000ULL,
436 0x0020600000000000ULL, 0x0060600000000000ULL,
437 0x0020600000000000ULL, 0x0060600000000000ULL,
438 0x0020600000000000ULL, 0x0060600000000000ULL,
439 0x0020600000000000ULL, 0x0060600000000000ULL,
440 0x0020600000000000ULL, 0x0060600000000000ULL,
441 0x0020600000000000ULL, 0x0060600000000000ULL,
442 0x0020600000000000ULL, 0x0060600000000000ULL,
443 0x0020600000000000ULL, 0x0000600000000000ULL,
444 0x0040600000000000ULL, 0x0060600000000000ULL,
445 END_SIGN
446 };
447
448 MODULE_LICENSE("GPL");
449 MODULE_VERSION(DRV_VERSION);
450
451
452 /* Module Loadable parameters. */
453 S2IO_PARM_INT(tx_fifo_num, 1);
454 S2IO_PARM_INT(rx_ring_num, 1);
455
456
457 S2IO_PARM_INT(rx_ring_mode, 1);
458 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
459 S2IO_PARM_INT(rmac_pause_time, 0x100);
460 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
461 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
462 S2IO_PARM_INT(shared_splits, 0);
463 S2IO_PARM_INT(tmac_util_period, 5);
464 S2IO_PARM_INT(rmac_util_period, 5);
465 S2IO_PARM_INT(l3l4hdr_size, 128);
466 /* Frequency of Rx desc syncs expressed as power of 2 */
467 S2IO_PARM_INT(rxsync_frequency, 3);
468 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
469 S2IO_PARM_INT(intr_type, 2);
470 /* Large receive offload feature */
471 static unsigned int lro_enable;
472 module_param_named(lro, lro_enable, uint, 0);
473
474 /* Max pkts to be aggregated by LRO at one time. If not specified,
475 * aggregation happens until we hit max IP pkt size(64K)
476 */
477 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
478 S2IO_PARM_INT(indicate_max_pkts, 0);
479
480 S2IO_PARM_INT(napi, 1);
481 S2IO_PARM_INT(ufo, 0);
482 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
483
484 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
485 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
486 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
487 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
488 static unsigned int rts_frm_len[MAX_RX_RINGS] =
489 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
490
491 module_param_array(tx_fifo_len, uint, NULL, 0);
492 module_param_array(rx_ring_sz, uint, NULL, 0);
493 module_param_array(rts_frm_len, uint, NULL, 0);
494
495 /*
496 * S2IO device table.
497 * This table lists all the devices that this driver supports.
498 */
499 static struct pci_device_id s2io_tbl[] __devinitdata = {
500 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
501 PCI_ANY_ID, PCI_ANY_ID},
502 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
503 PCI_ANY_ID, PCI_ANY_ID},
504 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
505 PCI_ANY_ID, PCI_ANY_ID},
506 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
507 PCI_ANY_ID, PCI_ANY_ID},
508 {0,}
509 };
510
511 MODULE_DEVICE_TABLE(pci, s2io_tbl);
512
513 static struct pci_error_handlers s2io_err_handler = {
514 .error_detected = s2io_io_error_detected,
515 .slot_reset = s2io_io_slot_reset,
516 .resume = s2io_io_resume,
517 };
518
519 static struct pci_driver s2io_driver = {
520 .name = "S2IO",
521 .id_table = s2io_tbl,
522 .probe = s2io_init_nic,
523 .remove = __devexit_p(s2io_rem_nic),
524 .err_handler = &s2io_err_handler,
525 };
526
527 /* A simplifier macro used both by init and free shared_mem Fns(). */
528 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
529
530 /**
531 * init_shared_mem - Allocation and Initialization of Memory
532 * @nic: Device private variable.
533 * Description: The function allocates all the memory areas shared
534 * between the NIC and the driver. This includes Tx descriptors,
535 * Rx descriptors and the statistics block.
536 */
537
538 static int init_shared_mem(struct s2io_nic *nic)
539 {
540 u32 size;
541 void *tmp_v_addr, *tmp_v_addr_next;
542 dma_addr_t tmp_p_addr, tmp_p_addr_next;
543 struct RxD_block *pre_rxd_blk = NULL;
544 int i, j, blk_cnt;
545 int lst_size, lst_per_page;
546 struct net_device *dev = nic->dev;
547 unsigned long tmp;
548 struct buffAdd *ba;
549
550 struct mac_info *mac_control;
551 struct config_param *config;
552 unsigned long long mem_allocated = 0;
553
554 mac_control = &nic->mac_control;
555 config = &nic->config;
556
557
558 /* Allocation and initialization of TXDLs in FIOFs */
559 size = 0;
560 for (i = 0; i < config->tx_fifo_num; i++) {
561 size += config->tx_cfg[i].fifo_len;
562 }
563 if (size > MAX_AVAILABLE_TXDS) {
564 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
565 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
566 return -EINVAL;
567 }
568
569 lst_size = (sizeof(struct TxD) * config->max_txds);
570 lst_per_page = PAGE_SIZE / lst_size;
571
572 for (i = 0; i < config->tx_fifo_num; i++) {
573 int fifo_len = config->tx_cfg[i].fifo_len;
574 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
575 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
576 GFP_KERNEL);
577 if (!mac_control->fifos[i].list_info) {
578 DBG_PRINT(INFO_DBG,
579 "Malloc failed for list_info\n");
580 return -ENOMEM;
581 }
582 mem_allocated += list_holder_size;
583 }
584 for (i = 0; i < config->tx_fifo_num; i++) {
585 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
586 lst_per_page);
587 mac_control->fifos[i].tx_curr_put_info.offset = 0;
588 mac_control->fifos[i].tx_curr_put_info.fifo_len =
589 config->tx_cfg[i].fifo_len - 1;
590 mac_control->fifos[i].tx_curr_get_info.offset = 0;
591 mac_control->fifos[i].tx_curr_get_info.fifo_len =
592 config->tx_cfg[i].fifo_len - 1;
593 mac_control->fifos[i].fifo_no = i;
594 mac_control->fifos[i].nic = nic;
595 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
596
597 for (j = 0; j < page_num; j++) {
598 int k = 0;
599 dma_addr_t tmp_p;
600 void *tmp_v;
601 tmp_v = pci_alloc_consistent(nic->pdev,
602 PAGE_SIZE, &tmp_p);
603 if (!tmp_v) {
604 DBG_PRINT(INFO_DBG,
605 "pci_alloc_consistent ");
606 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
607 return -ENOMEM;
608 }
609 /* If we got a zero DMA address(can happen on
610 * certain platforms like PPC), reallocate.
611 * Store virtual address of page we don't want,
612 * to be freed later.
613 */
614 if (!tmp_p) {
615 mac_control->zerodma_virt_addr = tmp_v;
616 DBG_PRINT(INIT_DBG,
617 "%s: Zero DMA address for TxDL. ", dev->name);
618 DBG_PRINT(INIT_DBG,
619 "Virtual address %p\n", tmp_v);
620 tmp_v = pci_alloc_consistent(nic->pdev,
621 PAGE_SIZE, &tmp_p);
622 if (!tmp_v) {
623 DBG_PRINT(INFO_DBG,
624 "pci_alloc_consistent ");
625 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
626 return -ENOMEM;
627 }
628 mem_allocated += PAGE_SIZE;
629 }
630 while (k < lst_per_page) {
631 int l = (j * lst_per_page) + k;
632 if (l == config->tx_cfg[i].fifo_len)
633 break;
634 mac_control->fifos[i].list_info[l].list_virt_addr =
635 tmp_v + (k * lst_size);
636 mac_control->fifos[i].list_info[l].list_phy_addr =
637 tmp_p + (k * lst_size);
638 k++;
639 }
640 }
641 }
642
643 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
644 if (!nic->ufo_in_band_v)
645 return -ENOMEM;
646 mem_allocated += (size * sizeof(u64));
647
648 /* Allocation and initialization of RXDs in Rings */
649 size = 0;
650 for (i = 0; i < config->rx_ring_num; i++) {
651 if (config->rx_cfg[i].num_rxd %
652 (rxd_count[nic->rxd_mode] + 1)) {
653 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
654 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
655 i);
656 DBG_PRINT(ERR_DBG, "RxDs per Block");
657 return FAILURE;
658 }
659 size += config->rx_cfg[i].num_rxd;
660 mac_control->rings[i].block_count =
661 config->rx_cfg[i].num_rxd /
662 (rxd_count[nic->rxd_mode] + 1 );
663 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
664 mac_control->rings[i].block_count;
665 }
666 if (nic->rxd_mode == RXD_MODE_1)
667 size = (size * (sizeof(struct RxD1)));
668 else
669 size = (size * (sizeof(struct RxD3)));
670
671 for (i = 0; i < config->rx_ring_num; i++) {
672 mac_control->rings[i].rx_curr_get_info.block_index = 0;
673 mac_control->rings[i].rx_curr_get_info.offset = 0;
674 mac_control->rings[i].rx_curr_get_info.ring_len =
675 config->rx_cfg[i].num_rxd - 1;
676 mac_control->rings[i].rx_curr_put_info.block_index = 0;
677 mac_control->rings[i].rx_curr_put_info.offset = 0;
678 mac_control->rings[i].rx_curr_put_info.ring_len =
679 config->rx_cfg[i].num_rxd - 1;
680 mac_control->rings[i].nic = nic;
681 mac_control->rings[i].ring_no = i;
682
683 blk_cnt = config->rx_cfg[i].num_rxd /
684 (rxd_count[nic->rxd_mode] + 1);
685 /* Allocating all the Rx blocks */
686 for (j = 0; j < blk_cnt; j++) {
687 struct rx_block_info *rx_blocks;
688 int l;
689
690 rx_blocks = &mac_control->rings[i].rx_blocks[j];
691 size = SIZE_OF_BLOCK; //size is always page size
692 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
693 &tmp_p_addr);
694 if (tmp_v_addr == NULL) {
695 /*
696 * In case of failure, free_shared_mem()
697 * is called, which should free any
698 * memory that was alloced till the
699 * failure happened.
700 */
701 rx_blocks->block_virt_addr = tmp_v_addr;
702 return -ENOMEM;
703 }
704 mem_allocated += size;
705 memset(tmp_v_addr, 0, size);
706 rx_blocks->block_virt_addr = tmp_v_addr;
707 rx_blocks->block_dma_addr = tmp_p_addr;
708 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
709 rxd_count[nic->rxd_mode],
710 GFP_KERNEL);
711 if (!rx_blocks->rxds)
712 return -ENOMEM;
713 mem_allocated +=
714 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
715 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
716 rx_blocks->rxds[l].virt_addr =
717 rx_blocks->block_virt_addr +
718 (rxd_size[nic->rxd_mode] * l);
719 rx_blocks->rxds[l].dma_addr =
720 rx_blocks->block_dma_addr +
721 (rxd_size[nic->rxd_mode] * l);
722 }
723 }
724 /* Interlinking all Rx Blocks */
725 for (j = 0; j < blk_cnt; j++) {
726 tmp_v_addr =
727 mac_control->rings[i].rx_blocks[j].block_virt_addr;
728 tmp_v_addr_next =
729 mac_control->rings[i].rx_blocks[(j + 1) %
730 blk_cnt].block_virt_addr;
731 tmp_p_addr =
732 mac_control->rings[i].rx_blocks[j].block_dma_addr;
733 tmp_p_addr_next =
734 mac_control->rings[i].rx_blocks[(j + 1) %
735 blk_cnt].block_dma_addr;
736
737 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
738 pre_rxd_blk->reserved_2_pNext_RxD_block =
739 (unsigned long) tmp_v_addr_next;
740 pre_rxd_blk->pNext_RxD_Blk_physical =
741 (u64) tmp_p_addr_next;
742 }
743 }
744 if (nic->rxd_mode == RXD_MODE_3B) {
745 /*
746 * Allocation of Storages for buffer addresses in 2BUFF mode
747 * and the buffers as well.
748 */
749 for (i = 0; i < config->rx_ring_num; i++) {
750 blk_cnt = config->rx_cfg[i].num_rxd /
751 (rxd_count[nic->rxd_mode]+ 1);
752 mac_control->rings[i].ba =
753 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
754 GFP_KERNEL);
755 if (!mac_control->rings[i].ba)
756 return -ENOMEM;
757 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
758 for (j = 0; j < blk_cnt; j++) {
759 int k = 0;
760 mac_control->rings[i].ba[j] =
761 kmalloc((sizeof(struct buffAdd) *
762 (rxd_count[nic->rxd_mode] + 1)),
763 GFP_KERNEL);
764 if (!mac_control->rings[i].ba[j])
765 return -ENOMEM;
766 mem_allocated += (sizeof(struct buffAdd) * \
767 (rxd_count[nic->rxd_mode] + 1));
768 while (k != rxd_count[nic->rxd_mode]) {
769 ba = &mac_control->rings[i].ba[j][k];
770
771 ba->ba_0_org = (void *) kmalloc
772 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
773 if (!ba->ba_0_org)
774 return -ENOMEM;
775 mem_allocated +=
776 (BUF0_LEN + ALIGN_SIZE);
777 tmp = (unsigned long)ba->ba_0_org;
778 tmp += ALIGN_SIZE;
779 tmp &= ~((unsigned long) ALIGN_SIZE);
780 ba->ba_0 = (void *) tmp;
781
782 ba->ba_1_org = (void *) kmalloc
783 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
784 if (!ba->ba_1_org)
785 return -ENOMEM;
786 mem_allocated
787 += (BUF1_LEN + ALIGN_SIZE);
788 tmp = (unsigned long) ba->ba_1_org;
789 tmp += ALIGN_SIZE;
790 tmp &= ~((unsigned long) ALIGN_SIZE);
791 ba->ba_1 = (void *) tmp;
792 k++;
793 }
794 }
795 }
796 }
797
798 /* Allocation and initialization of Statistics block */
799 size = sizeof(struct stat_block);
800 mac_control->stats_mem = pci_alloc_consistent
801 (nic->pdev, size, &mac_control->stats_mem_phy);
802
803 if (!mac_control->stats_mem) {
804 /*
805 * In case of failure, free_shared_mem() is called, which
806 * should free any memory that was alloced till the
807 * failure happened.
808 */
809 return -ENOMEM;
810 }
811 mem_allocated += size;
812 mac_control->stats_mem_sz = size;
813
814 tmp_v_addr = mac_control->stats_mem;
815 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
816 memset(tmp_v_addr, 0, size);
817 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
818 (unsigned long long) tmp_p_addr);
819 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
820 return SUCCESS;
821 }
822
823 /**
824 * free_shared_mem - Free the allocated Memory
825 * @nic: Device private variable.
826 * Description: This function is to free all memory locations allocated by
827 * the init_shared_mem() function and return it to the kernel.
828 */
829
830 static void free_shared_mem(struct s2io_nic *nic)
831 {
832 int i, j, blk_cnt, size;
833 u32 ufo_size = 0;
834 void *tmp_v_addr;
835 dma_addr_t tmp_p_addr;
836 struct mac_info *mac_control;
837 struct config_param *config;
838 int lst_size, lst_per_page;
839 struct net_device *dev;
840 int page_num = 0;
841
842 if (!nic)
843 return;
844
845 dev = nic->dev;
846
847 mac_control = &nic->mac_control;
848 config = &nic->config;
849
850 lst_size = (sizeof(struct TxD) * config->max_txds);
851 lst_per_page = PAGE_SIZE / lst_size;
852
853 for (i = 0; i < config->tx_fifo_num; i++) {
854 ufo_size += config->tx_cfg[i].fifo_len;
855 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
856 lst_per_page);
857 for (j = 0; j < page_num; j++) {
858 int mem_blks = (j * lst_per_page);
859 if (!mac_control->fifos[i].list_info)
860 return;
861 if (!mac_control->fifos[i].list_info[mem_blks].
862 list_virt_addr)
863 break;
864 pci_free_consistent(nic->pdev, PAGE_SIZE,
865 mac_control->fifos[i].
866 list_info[mem_blks].
867 list_virt_addr,
868 mac_control->fifos[i].
869 list_info[mem_blks].
870 list_phy_addr);
871 nic->mac_control.stats_info->sw_stat.mem_freed
872 += PAGE_SIZE;
873 }
874 /* If we got a zero DMA address during allocation,
875 * free the page now
876 */
877 if (mac_control->zerodma_virt_addr) {
878 pci_free_consistent(nic->pdev, PAGE_SIZE,
879 mac_control->zerodma_virt_addr,
880 (dma_addr_t)0);
881 DBG_PRINT(INIT_DBG,
882 "%s: Freeing TxDL with zero DMA addr. ",
883 dev->name);
884 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
885 mac_control->zerodma_virt_addr);
886 nic->mac_control.stats_info->sw_stat.mem_freed
887 += PAGE_SIZE;
888 }
889 kfree(mac_control->fifos[i].list_info);
890 nic->mac_control.stats_info->sw_stat.mem_freed +=
891 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
892 }
893
894 size = SIZE_OF_BLOCK;
895 for (i = 0; i < config->rx_ring_num; i++) {
896 blk_cnt = mac_control->rings[i].block_count;
897 for (j = 0; j < blk_cnt; j++) {
898 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
899 block_virt_addr;
900 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
901 block_dma_addr;
902 if (tmp_v_addr == NULL)
903 break;
904 pci_free_consistent(nic->pdev, size,
905 tmp_v_addr, tmp_p_addr);
906 nic->mac_control.stats_info->sw_stat.mem_freed += size;
907 kfree(mac_control->rings[i].rx_blocks[j].rxds);
908 nic->mac_control.stats_info->sw_stat.mem_freed +=
909 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
910 }
911 }
912
913 if (nic->rxd_mode == RXD_MODE_3B) {
914 /* Freeing buffer storage addresses in 2BUFF mode. */
915 for (i = 0; i < config->rx_ring_num; i++) {
916 blk_cnt = config->rx_cfg[i].num_rxd /
917 (rxd_count[nic->rxd_mode] + 1);
918 for (j = 0; j < blk_cnt; j++) {
919 int k = 0;
920 if (!mac_control->rings[i].ba[j])
921 continue;
922 while (k != rxd_count[nic->rxd_mode]) {
923 struct buffAdd *ba =
924 &mac_control->rings[i].ba[j][k];
925 kfree(ba->ba_0_org);
926 nic->mac_control.stats_info->sw_stat.\
927 mem_freed += (BUF0_LEN + ALIGN_SIZE);
928 kfree(ba->ba_1_org);
929 nic->mac_control.stats_info->sw_stat.\
930 mem_freed += (BUF1_LEN + ALIGN_SIZE);
931 k++;
932 }
933 kfree(mac_control->rings[i].ba[j]);
934 nic->mac_control.stats_info->sw_stat.mem_freed +=
935 (sizeof(struct buffAdd) *
936 (rxd_count[nic->rxd_mode] + 1));
937 }
938 kfree(mac_control->rings[i].ba);
939 nic->mac_control.stats_info->sw_stat.mem_freed +=
940 (sizeof(struct buffAdd *) * blk_cnt);
941 }
942 }
943
944 if (mac_control->stats_mem) {
945 pci_free_consistent(nic->pdev,
946 mac_control->stats_mem_sz,
947 mac_control->stats_mem,
948 mac_control->stats_mem_phy);
949 nic->mac_control.stats_info->sw_stat.mem_freed +=
950 mac_control->stats_mem_sz;
951 }
952 if (nic->ufo_in_band_v) {
953 kfree(nic->ufo_in_band_v);
954 nic->mac_control.stats_info->sw_stat.mem_freed
955 += (ufo_size * sizeof(u64));
956 }
957 }
958
959 /**
960 * s2io_verify_pci_mode -
961 */
962
963 static int s2io_verify_pci_mode(struct s2io_nic *nic)
964 {
965 struct XENA_dev_config __iomem *bar0 = nic->bar0;
966 register u64 val64 = 0;
967 int mode;
968
969 val64 = readq(&bar0->pci_mode);
970 mode = (u8)GET_PCI_MODE(val64);
971
972 if ( val64 & PCI_MODE_UNKNOWN_MODE)
973 return -1; /* Unknown PCI mode */
974 return mode;
975 }
976
977 #define NEC_VENID 0x1033
978 #define NEC_DEVID 0x0125
979 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
980 {
981 struct pci_dev *tdev = NULL;
982 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
983 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
984 if (tdev->bus == s2io_pdev->bus->parent)
985 pci_dev_put(tdev);
986 return 1;
987 }
988 }
989 return 0;
990 }
991
992 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
993 /**
994 * s2io_print_pci_mode -
995 */
996 static int s2io_print_pci_mode(struct s2io_nic *nic)
997 {
998 struct XENA_dev_config __iomem *bar0 = nic->bar0;
999 register u64 val64 = 0;
1000 int mode;
1001 struct config_param *config = &nic->config;
1002
1003 val64 = readq(&bar0->pci_mode);
1004 mode = (u8)GET_PCI_MODE(val64);
1005
1006 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1007 return -1; /* Unknown PCI mode */
1008
1009 config->bus_speed = bus_speed[mode];
1010
1011 if (s2io_on_nec_bridge(nic->pdev)) {
1012 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1013 nic->dev->name);
1014 return mode;
1015 }
1016
1017 if (val64 & PCI_MODE_32_BITS) {
1018 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1019 } else {
1020 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1021 }
1022
1023 switch(mode) {
1024 case PCI_MODE_PCI_33:
1025 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1026 break;
1027 case PCI_MODE_PCI_66:
1028 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1029 break;
1030 case PCI_MODE_PCIX_M1_66:
1031 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1032 break;
1033 case PCI_MODE_PCIX_M1_100:
1034 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1035 break;
1036 case PCI_MODE_PCIX_M1_133:
1037 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1038 break;
1039 case PCI_MODE_PCIX_M2_66:
1040 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1041 break;
1042 case PCI_MODE_PCIX_M2_100:
1043 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1044 break;
1045 case PCI_MODE_PCIX_M2_133:
1046 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1047 break;
1048 default:
1049 return -1; /* Unsupported bus speed */
1050 }
1051
1052 return mode;
1053 }
1054
1055 /**
1056 * init_nic - Initialization of hardware
1057 * @nic: device peivate variable
1058 * Description: The function sequentially configures every block
1059 * of the H/W from their reset values.
1060 * Return Value: SUCCESS on success and
1061 * '-1' on failure (endian settings incorrect).
1062 */
1063
1064 static int init_nic(struct s2io_nic *nic)
1065 {
1066 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1067 struct net_device *dev = nic->dev;
1068 register u64 val64 = 0;
1069 void __iomem *add;
1070 u32 time;
1071 int i, j;
1072 struct mac_info *mac_control;
1073 struct config_param *config;
1074 int dtx_cnt = 0;
1075 unsigned long long mem_share;
1076 int mem_size;
1077
1078 mac_control = &nic->mac_control;
1079 config = &nic->config;
1080
1081 /* to set the swapper controle on the card */
1082 if(s2io_set_swapper(nic)) {
1083 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1084 return -1;
1085 }
1086
1087 /*
1088 * Herc requires EOI to be removed from reset before XGXS, so..
1089 */
1090 if (nic->device_type & XFRAME_II_DEVICE) {
1091 val64 = 0xA500000000ULL;
1092 writeq(val64, &bar0->sw_reset);
1093 msleep(500);
1094 val64 = readq(&bar0->sw_reset);
1095 }
1096
1097 /* Remove XGXS from reset state */
1098 val64 = 0;
1099 writeq(val64, &bar0->sw_reset);
1100 msleep(500);
1101 val64 = readq(&bar0->sw_reset);
1102
1103 /* Enable Receiving broadcasts */
1104 add = &bar0->mac_cfg;
1105 val64 = readq(&bar0->mac_cfg);
1106 val64 |= MAC_RMAC_BCAST_ENABLE;
1107 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1108 writel((u32) val64, add);
1109 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1110 writel((u32) (val64 >> 32), (add + 4));
1111
1112 /* Read registers in all blocks */
1113 val64 = readq(&bar0->mac_int_mask);
1114 val64 = readq(&bar0->mc_int_mask);
1115 val64 = readq(&bar0->xgxs_int_mask);
1116
1117 /* Set MTU */
1118 val64 = dev->mtu;
1119 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1120
1121 if (nic->device_type & XFRAME_II_DEVICE) {
1122 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1123 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1124 &bar0->dtx_control, UF);
1125 if (dtx_cnt & 0x1)
1126 msleep(1); /* Necessary!! */
1127 dtx_cnt++;
1128 }
1129 } else {
1130 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1131 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1132 &bar0->dtx_control, UF);
1133 val64 = readq(&bar0->dtx_control);
1134 dtx_cnt++;
1135 }
1136 }
1137
1138 /* Tx DMA Initialization */
1139 val64 = 0;
1140 writeq(val64, &bar0->tx_fifo_partition_0);
1141 writeq(val64, &bar0->tx_fifo_partition_1);
1142 writeq(val64, &bar0->tx_fifo_partition_2);
1143 writeq(val64, &bar0->tx_fifo_partition_3);
1144
1145
1146 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1147 val64 |=
1148 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1149 13) | vBIT(config->tx_cfg[i].fifo_priority,
1150 ((i * 32) + 5), 3);
1151
1152 if (i == (config->tx_fifo_num - 1)) {
1153 if (i % 2 == 0)
1154 i++;
1155 }
1156
1157 switch (i) {
1158 case 1:
1159 writeq(val64, &bar0->tx_fifo_partition_0);
1160 val64 = 0;
1161 break;
1162 case 3:
1163 writeq(val64, &bar0->tx_fifo_partition_1);
1164 val64 = 0;
1165 break;
1166 case 5:
1167 writeq(val64, &bar0->tx_fifo_partition_2);
1168 val64 = 0;
1169 break;
1170 case 7:
1171 writeq(val64, &bar0->tx_fifo_partition_3);
1172 break;
1173 }
1174 }
1175
1176 /*
1177 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1178 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1179 */
1180 if ((nic->device_type == XFRAME_I_DEVICE) &&
1181 (nic->pdev->revision < 4))
1182 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1183
1184 val64 = readq(&bar0->tx_fifo_partition_0);
1185 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1186 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1187
1188 /*
1189 * Initialization of Tx_PA_CONFIG register to ignore packet
1190 * integrity checking.
1191 */
1192 val64 = readq(&bar0->tx_pa_cfg);
1193 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1194 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1195 writeq(val64, &bar0->tx_pa_cfg);
1196
1197 /* Rx DMA intialization. */
1198 val64 = 0;
1199 for (i = 0; i < config->rx_ring_num; i++) {
1200 val64 |=
1201 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1202 3);
1203 }
1204 writeq(val64, &bar0->rx_queue_priority);
1205
1206 /*
1207 * Allocating equal share of memory to all the
1208 * configured Rings.
1209 */
1210 val64 = 0;
1211 if (nic->device_type & XFRAME_II_DEVICE)
1212 mem_size = 32;
1213 else
1214 mem_size = 64;
1215
1216 for (i = 0; i < config->rx_ring_num; i++) {
1217 switch (i) {
1218 case 0:
1219 mem_share = (mem_size / config->rx_ring_num +
1220 mem_size % config->rx_ring_num);
1221 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1222 continue;
1223 case 1:
1224 mem_share = (mem_size / config->rx_ring_num);
1225 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1226 continue;
1227 case 2:
1228 mem_share = (mem_size / config->rx_ring_num);
1229 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1230 continue;
1231 case 3:
1232 mem_share = (mem_size / config->rx_ring_num);
1233 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1234 continue;
1235 case 4:
1236 mem_share = (mem_size / config->rx_ring_num);
1237 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1238 continue;
1239 case 5:
1240 mem_share = (mem_size / config->rx_ring_num);
1241 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1242 continue;
1243 case 6:
1244 mem_share = (mem_size / config->rx_ring_num);
1245 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1246 continue;
1247 case 7:
1248 mem_share = (mem_size / config->rx_ring_num);
1249 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1250 continue;
1251 }
1252 }
1253 writeq(val64, &bar0->rx_queue_cfg);
1254
1255 /*
1256 * Filling Tx round robin registers
1257 * as per the number of FIFOs
1258 */
1259 switch (config->tx_fifo_num) {
1260 case 1:
1261 val64 = 0x0000000000000000ULL;
1262 writeq(val64, &bar0->tx_w_round_robin_0);
1263 writeq(val64, &bar0->tx_w_round_robin_1);
1264 writeq(val64, &bar0->tx_w_round_robin_2);
1265 writeq(val64, &bar0->tx_w_round_robin_3);
1266 writeq(val64, &bar0->tx_w_round_robin_4);
1267 break;
1268 case 2:
1269 val64 = 0x0000010000010000ULL;
1270 writeq(val64, &bar0->tx_w_round_robin_0);
1271 val64 = 0x0100000100000100ULL;
1272 writeq(val64, &bar0->tx_w_round_robin_1);
1273 val64 = 0x0001000001000001ULL;
1274 writeq(val64, &bar0->tx_w_round_robin_2);
1275 val64 = 0x0000010000010000ULL;
1276 writeq(val64, &bar0->tx_w_round_robin_3);
1277 val64 = 0x0100000000000000ULL;
1278 writeq(val64, &bar0->tx_w_round_robin_4);
1279 break;
1280 case 3:
1281 val64 = 0x0001000102000001ULL;
1282 writeq(val64, &bar0->tx_w_round_robin_0);
1283 val64 = 0x0001020000010001ULL;
1284 writeq(val64, &bar0->tx_w_round_robin_1);
1285 val64 = 0x0200000100010200ULL;
1286 writeq(val64, &bar0->tx_w_round_robin_2);
1287 val64 = 0x0001000102000001ULL;
1288 writeq(val64, &bar0->tx_w_round_robin_3);
1289 val64 = 0x0001020000000000ULL;
1290 writeq(val64, &bar0->tx_w_round_robin_4);
1291 break;
1292 case 4:
1293 val64 = 0x0001020300010200ULL;
1294 writeq(val64, &bar0->tx_w_round_robin_0);
1295 val64 = 0x0100000102030001ULL;
1296 writeq(val64, &bar0->tx_w_round_robin_1);
1297 val64 = 0x0200010000010203ULL;
1298 writeq(val64, &bar0->tx_w_round_robin_2);
1299 val64 = 0x0001020001000001ULL;
1300 writeq(val64, &bar0->tx_w_round_robin_3);
1301 val64 = 0x0203000100000000ULL;
1302 writeq(val64, &bar0->tx_w_round_robin_4);
1303 break;
1304 case 5:
1305 val64 = 0x0001000203000102ULL;
1306 writeq(val64, &bar0->tx_w_round_robin_0);
1307 val64 = 0x0001020001030004ULL;
1308 writeq(val64, &bar0->tx_w_round_robin_1);
1309 val64 = 0x0001000203000102ULL;
1310 writeq(val64, &bar0->tx_w_round_robin_2);
1311 val64 = 0x0001020001030004ULL;
1312 writeq(val64, &bar0->tx_w_round_robin_3);
1313 val64 = 0x0001000000000000ULL;
1314 writeq(val64, &bar0->tx_w_round_robin_4);
1315 break;
1316 case 6:
1317 val64 = 0x0001020304000102ULL;
1318 writeq(val64, &bar0->tx_w_round_robin_0);
1319 val64 = 0x0304050001020001ULL;
1320 writeq(val64, &bar0->tx_w_round_robin_1);
1321 val64 = 0x0203000100000102ULL;
1322 writeq(val64, &bar0->tx_w_round_robin_2);
1323 val64 = 0x0304000102030405ULL;
1324 writeq(val64, &bar0->tx_w_round_robin_3);
1325 val64 = 0x0001000200000000ULL;
1326 writeq(val64, &bar0->tx_w_round_robin_4);
1327 break;
1328 case 7:
1329 val64 = 0x0001020001020300ULL;
1330 writeq(val64, &bar0->tx_w_round_robin_0);
1331 val64 = 0x0102030400010203ULL;
1332 writeq(val64, &bar0->tx_w_round_robin_1);
1333 val64 = 0x0405060001020001ULL;
1334 writeq(val64, &bar0->tx_w_round_robin_2);
1335 val64 = 0x0304050000010200ULL;
1336 writeq(val64, &bar0->tx_w_round_robin_3);
1337 val64 = 0x0102030000000000ULL;
1338 writeq(val64, &bar0->tx_w_round_robin_4);
1339 break;
1340 case 8:
1341 val64 = 0x0001020300040105ULL;
1342 writeq(val64, &bar0->tx_w_round_robin_0);
1343 val64 = 0x0200030106000204ULL;
1344 writeq(val64, &bar0->tx_w_round_robin_1);
1345 val64 = 0x0103000502010007ULL;
1346 writeq(val64, &bar0->tx_w_round_robin_2);
1347 val64 = 0x0304010002060500ULL;
1348 writeq(val64, &bar0->tx_w_round_robin_3);
1349 val64 = 0x0103020400000000ULL;
1350 writeq(val64, &bar0->tx_w_round_robin_4);
1351 break;
1352 }
1353
1354 /* Enable all configured Tx FIFO partitions */
1355 val64 = readq(&bar0->tx_fifo_partition_0);
1356 val64 |= (TX_FIFO_PARTITION_EN);
1357 writeq(val64, &bar0->tx_fifo_partition_0);
1358
1359 /* Filling the Rx round robin registers as per the
1360 * number of Rings and steering based on QoS.
1361 */
1362 switch (config->rx_ring_num) {
1363 case 1:
1364 val64 = 0x8080808080808080ULL;
1365 writeq(val64, &bar0->rts_qos_steering);
1366 break;
1367 case 2:
1368 val64 = 0x0000010000010000ULL;
1369 writeq(val64, &bar0->rx_w_round_robin_0);
1370 val64 = 0x0100000100000100ULL;
1371 writeq(val64, &bar0->rx_w_round_robin_1);
1372 val64 = 0x0001000001000001ULL;
1373 writeq(val64, &bar0->rx_w_round_robin_2);
1374 val64 = 0x0000010000010000ULL;
1375 writeq(val64, &bar0->rx_w_round_robin_3);
1376 val64 = 0x0100000000000000ULL;
1377 writeq(val64, &bar0->rx_w_round_robin_4);
1378
1379 val64 = 0x8080808040404040ULL;
1380 writeq(val64, &bar0->rts_qos_steering);
1381 break;
1382 case 3:
1383 val64 = 0x0001000102000001ULL;
1384 writeq(val64, &bar0->rx_w_round_robin_0);
1385 val64 = 0x0001020000010001ULL;
1386 writeq(val64, &bar0->rx_w_round_robin_1);
1387 val64 = 0x0200000100010200ULL;
1388 writeq(val64, &bar0->rx_w_round_robin_2);
1389 val64 = 0x0001000102000001ULL;
1390 writeq(val64, &bar0->rx_w_round_robin_3);
1391 val64 = 0x0001020000000000ULL;
1392 writeq(val64, &bar0->rx_w_round_robin_4);
1393
1394 val64 = 0x8080804040402020ULL;
1395 writeq(val64, &bar0->rts_qos_steering);
1396 break;
1397 case 4:
1398 val64 = 0x0001020300010200ULL;
1399 writeq(val64, &bar0->rx_w_round_robin_0);
1400 val64 = 0x0100000102030001ULL;
1401 writeq(val64, &bar0->rx_w_round_robin_1);
1402 val64 = 0x0200010000010203ULL;
1403 writeq(val64, &bar0->rx_w_round_robin_2);
1404 val64 = 0x0001020001000001ULL;
1405 writeq(val64, &bar0->rx_w_round_robin_3);
1406 val64 = 0x0203000100000000ULL;
1407 writeq(val64, &bar0->rx_w_round_robin_4);
1408
1409 val64 = 0x8080404020201010ULL;
1410 writeq(val64, &bar0->rts_qos_steering);
1411 break;
1412 case 5:
1413 val64 = 0x0001000203000102ULL;
1414 writeq(val64, &bar0->rx_w_round_robin_0);
1415 val64 = 0x0001020001030004ULL;
1416 writeq(val64, &bar0->rx_w_round_robin_1);
1417 val64 = 0x0001000203000102ULL;
1418 writeq(val64, &bar0->rx_w_round_robin_2);
1419 val64 = 0x0001020001030004ULL;
1420 writeq(val64, &bar0->rx_w_round_robin_3);
1421 val64 = 0x0001000000000000ULL;
1422 writeq(val64, &bar0->rx_w_round_robin_4);
1423
1424 val64 = 0x8080404020201008ULL;
1425 writeq(val64, &bar0->rts_qos_steering);
1426 break;
1427 case 6:
1428 val64 = 0x0001020304000102ULL;
1429 writeq(val64, &bar0->rx_w_round_robin_0);
1430 val64 = 0x0304050001020001ULL;
1431 writeq(val64, &bar0->rx_w_round_robin_1);
1432 val64 = 0x0203000100000102ULL;
1433 writeq(val64, &bar0->rx_w_round_robin_2);
1434 val64 = 0x0304000102030405ULL;
1435 writeq(val64, &bar0->rx_w_round_robin_3);
1436 val64 = 0x0001000200000000ULL;
1437 writeq(val64, &bar0->rx_w_round_robin_4);
1438
1439 val64 = 0x8080404020100804ULL;
1440 writeq(val64, &bar0->rts_qos_steering);
1441 break;
1442 case 7:
1443 val64 = 0x0001020001020300ULL;
1444 writeq(val64, &bar0->rx_w_round_robin_0);
1445 val64 = 0x0102030400010203ULL;
1446 writeq(val64, &bar0->rx_w_round_robin_1);
1447 val64 = 0x0405060001020001ULL;
1448 writeq(val64, &bar0->rx_w_round_robin_2);
1449 val64 = 0x0304050000010200ULL;
1450 writeq(val64, &bar0->rx_w_round_robin_3);
1451 val64 = 0x0102030000000000ULL;
1452 writeq(val64, &bar0->rx_w_round_robin_4);
1453
1454 val64 = 0x8080402010080402ULL;
1455 writeq(val64, &bar0->rts_qos_steering);
1456 break;
1457 case 8:
1458 val64 = 0x0001020300040105ULL;
1459 writeq(val64, &bar0->rx_w_round_robin_0);
1460 val64 = 0x0200030106000204ULL;
1461 writeq(val64, &bar0->rx_w_round_robin_1);
1462 val64 = 0x0103000502010007ULL;
1463 writeq(val64, &bar0->rx_w_round_robin_2);
1464 val64 = 0x0304010002060500ULL;
1465 writeq(val64, &bar0->rx_w_round_robin_3);
1466 val64 = 0x0103020400000000ULL;
1467 writeq(val64, &bar0->rx_w_round_robin_4);
1468
1469 val64 = 0x8040201008040201ULL;
1470 writeq(val64, &bar0->rts_qos_steering);
1471 break;
1472 }
1473
1474 /* UDP Fix */
1475 val64 = 0;
1476 for (i = 0; i < 8; i++)
1477 writeq(val64, &bar0->rts_frm_len_n[i]);
1478
1479 /* Set the default rts frame length for the rings configured */
1480 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1481 for (i = 0 ; i < config->rx_ring_num ; i++)
1482 writeq(val64, &bar0->rts_frm_len_n[i]);
1483
1484 /* Set the frame length for the configured rings
1485 * desired by the user
1486 */
1487 for (i = 0; i < config->rx_ring_num; i++) {
1488 /* If rts_frm_len[i] == 0 then it is assumed that user not
1489 * specified frame length steering.
1490 * If the user provides the frame length then program
1491 * the rts_frm_len register for those values or else
1492 * leave it as it is.
1493 */
1494 if (rts_frm_len[i] != 0) {
1495 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1496 &bar0->rts_frm_len_n[i]);
1497 }
1498 }
1499
1500 /* Disable differentiated services steering logic */
1501 for (i = 0; i < 64; i++) {
1502 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1503 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1504 dev->name);
1505 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1506 return FAILURE;
1507 }
1508 }
1509
1510 /* Program statistics memory */
1511 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1512
1513 if (nic->device_type == XFRAME_II_DEVICE) {
1514 val64 = STAT_BC(0x320);
1515 writeq(val64, &bar0->stat_byte_cnt);
1516 }
1517
1518 /*
1519 * Initializing the sampling rate for the device to calculate the
1520 * bandwidth utilization.
1521 */
1522 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1523 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1524 writeq(val64, &bar0->mac_link_util);
1525
1526
1527 /*
1528 * Initializing the Transmit and Receive Traffic Interrupt
1529 * Scheme.
1530 */
1531 /*
1532 * TTI Initialization. Default Tx timer gets us about
1533 * 250 interrupts per sec. Continuous interrupts are enabled
1534 * by default.
1535 */
1536 if (nic->device_type == XFRAME_II_DEVICE) {
1537 int count = (nic->config.bus_speed * 125)/2;
1538 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1539 } else {
1540
1541 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1542 }
1543 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1544 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1545 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1546 if (use_continuous_tx_intrs)
1547 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1548 writeq(val64, &bar0->tti_data1_mem);
1549
1550 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1551 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1552 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1553 writeq(val64, &bar0->tti_data2_mem);
1554
1555 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1556 writeq(val64, &bar0->tti_command_mem);
1557
1558 /*
1559 * Once the operation completes, the Strobe bit of the command
1560 * register will be reset. We poll for this particular condition
1561 * We wait for a maximum of 500ms for the operation to complete,
1562 * if it's not complete by then we return error.
1563 */
1564 time = 0;
1565 while (TRUE) {
1566 val64 = readq(&bar0->tti_command_mem);
1567 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1568 break;
1569 }
1570 if (time > 10) {
1571 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1572 dev->name);
1573 return -1;
1574 }
1575 msleep(50);
1576 time++;
1577 }
1578
1579 /* RTI Initialization */
1580 if (nic->device_type == XFRAME_II_DEVICE) {
1581 /*
1582 * Programmed to generate Apprx 500 Intrs per
1583 * second
1584 */
1585 int count = (nic->config.bus_speed * 125)/4;
1586 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1587 } else
1588 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1589 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1590 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1591 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1592
1593 writeq(val64, &bar0->rti_data1_mem);
1594
1595 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1596 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1597 if (nic->config.intr_type == MSI_X)
1598 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1599 RTI_DATA2_MEM_RX_UFC_D(0x40));
1600 else
1601 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1602 RTI_DATA2_MEM_RX_UFC_D(0x80));
1603 writeq(val64, &bar0->rti_data2_mem);
1604
1605 for (i = 0; i < config->rx_ring_num; i++) {
1606 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1607 | RTI_CMD_MEM_OFFSET(i);
1608 writeq(val64, &bar0->rti_command_mem);
1609
1610 /*
1611 * Once the operation completes, the Strobe bit of the
1612 * command register will be reset. We poll for this
1613 * particular condition. We wait for a maximum of 500ms
1614 * for the operation to complete, if it's not complete
1615 * by then we return error.
1616 */
1617 time = 0;
1618 while (TRUE) {
1619 val64 = readq(&bar0->rti_command_mem);
1620 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1621 break;
1622
1623 if (time > 10) {
1624 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1625 dev->name);
1626 return -1;
1627 }
1628 time++;
1629 msleep(50);
1630 }
1631 }
1632
1633 /*
1634 * Initializing proper values as Pause threshold into all
1635 * the 8 Queues on Rx side.
1636 */
1637 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1638 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1639
1640 /* Disable RMAC PAD STRIPPING */
1641 add = &bar0->mac_cfg;
1642 val64 = readq(&bar0->mac_cfg);
1643 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1644 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1645 writel((u32) (val64), add);
1646 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1647 writel((u32) (val64 >> 32), (add + 4));
1648 val64 = readq(&bar0->mac_cfg);
1649
1650 /* Enable FCS stripping by adapter */
1651 add = &bar0->mac_cfg;
1652 val64 = readq(&bar0->mac_cfg);
1653 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1654 if (nic->device_type == XFRAME_II_DEVICE)
1655 writeq(val64, &bar0->mac_cfg);
1656 else {
1657 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1658 writel((u32) (val64), add);
1659 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1660 writel((u32) (val64 >> 32), (add + 4));
1661 }
1662
1663 /*
1664 * Set the time value to be inserted in the pause frame
1665 * generated by xena.
1666 */
1667 val64 = readq(&bar0->rmac_pause_cfg);
1668 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1669 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1670 writeq(val64, &bar0->rmac_pause_cfg);
1671
1672 /*
1673 * Set the Threshold Limit for Generating the pause frame
1674 * If the amount of data in any Queue exceeds ratio of
1675 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1676 * pause frame is generated
1677 */
1678 val64 = 0;
1679 for (i = 0; i < 4; i++) {
1680 val64 |=
1681 (((u64) 0xFF00 | nic->mac_control.
1682 mc_pause_threshold_q0q3)
1683 << (i * 2 * 8));
1684 }
1685 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1686
1687 val64 = 0;
1688 for (i = 0; i < 4; i++) {
1689 val64 |=
1690 (((u64) 0xFF00 | nic->mac_control.
1691 mc_pause_threshold_q4q7)
1692 << (i * 2 * 8));
1693 }
1694 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1695
1696 /*
1697 * TxDMA will stop Read request if the number of read split has
1698 * exceeded the limit pointed by shared_splits
1699 */
1700 val64 = readq(&bar0->pic_control);
1701 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1702 writeq(val64, &bar0->pic_control);
1703
1704 if (nic->config.bus_speed == 266) {
1705 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1706 writeq(0x0, &bar0->read_retry_delay);
1707 writeq(0x0, &bar0->write_retry_delay);
1708 }
1709
1710 /*
1711 * Programming the Herc to split every write transaction
1712 * that does not start on an ADB to reduce disconnects.
1713 */
1714 if (nic->device_type == XFRAME_II_DEVICE) {
1715 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1716 MISC_LINK_STABILITY_PRD(3);
1717 writeq(val64, &bar0->misc_control);
1718 val64 = readq(&bar0->pic_control2);
1719 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1720 writeq(val64, &bar0->pic_control2);
1721 }
1722 if (strstr(nic->product_name, "CX4")) {
1723 val64 = TMAC_AVG_IPG(0x17);
1724 writeq(val64, &bar0->tmac_avg_ipg);
1725 }
1726
1727 return SUCCESS;
1728 }
1729 #define LINK_UP_DOWN_INTERRUPT 1
1730 #define MAC_RMAC_ERR_TIMER 2
1731
1732 static int s2io_link_fault_indication(struct s2io_nic *nic)
1733 {
1734 if (nic->config.intr_type != INTA)
1735 return MAC_RMAC_ERR_TIMER;
1736 if (nic->device_type == XFRAME_II_DEVICE)
1737 return LINK_UP_DOWN_INTERRUPT;
1738 else
1739 return MAC_RMAC_ERR_TIMER;
1740 }
1741
1742 /**
1743 * do_s2io_write_bits - update alarm bits in alarm register
1744 * @value: alarm bits
1745 * @flag: interrupt status
1746 * @addr: address value
1747 * Description: update alarm bits in alarm register
1748 * Return Value:
1749 * NONE.
1750 */
1751 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1752 {
1753 u64 temp64;
1754
1755 temp64 = readq(addr);
1756
1757 if(flag == ENABLE_INTRS)
1758 temp64 &= ~((u64) value);
1759 else
1760 temp64 |= ((u64) value);
1761 writeq(temp64, addr);
1762 }
1763
1764 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1765 {
1766 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1767 register u64 gen_int_mask = 0;
1768
1769 if (mask & TX_DMA_INTR) {
1770
1771 gen_int_mask |= TXDMA_INT_M;
1772
1773 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1774 TXDMA_PCC_INT | TXDMA_TTI_INT |
1775 TXDMA_LSO_INT | TXDMA_TPA_INT |
1776 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1777
1778 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1779 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1780 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1781 &bar0->pfc_err_mask);
1782
1783 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1784 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1785 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1786
1787 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1788 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1789 PCC_N_SERR | PCC_6_COF_OV_ERR |
1790 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1791 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1792 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1793
1794 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1795 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1796
1797 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1798 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1799 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1800 flag, &bar0->lso_err_mask);
1801
1802 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1803 flag, &bar0->tpa_err_mask);
1804
1805 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1806
1807 }
1808
1809 if (mask & TX_MAC_INTR) {
1810 gen_int_mask |= TXMAC_INT_M;
1811 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1812 &bar0->mac_int_mask);
1813 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1814 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1815 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1816 flag, &bar0->mac_tmac_err_mask);
1817 }
1818
1819 if (mask & TX_XGXS_INTR) {
1820 gen_int_mask |= TXXGXS_INT_M;
1821 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1822 &bar0->xgxs_int_mask);
1823 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1824 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1825 flag, &bar0->xgxs_txgxs_err_mask);
1826 }
1827
1828 if (mask & RX_DMA_INTR) {
1829 gen_int_mask |= RXDMA_INT_M;
1830 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1831 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1832 flag, &bar0->rxdma_int_mask);
1833 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1834 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1835 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1836 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1837 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1838 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1839 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1840 &bar0->prc_pcix_err_mask);
1841 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1842 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1843 &bar0->rpa_err_mask);
1844 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1845 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1846 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1847 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1848 flag, &bar0->rda_err_mask);
1849 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1850 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1851 flag, &bar0->rti_err_mask);
1852 }
1853
1854 if (mask & RX_MAC_INTR) {
1855 gen_int_mask |= RXMAC_INT_M;
1856 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1857 &bar0->mac_int_mask);
1858 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1859 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1860 RMAC_DOUBLE_ECC_ERR |
1861 RMAC_LINK_STATE_CHANGE_INT,
1862 flag, &bar0->mac_rmac_err_mask);
1863 }
1864
1865 if (mask & RX_XGXS_INTR)
1866 {
1867 gen_int_mask |= RXXGXS_INT_M;
1868 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1869 &bar0->xgxs_int_mask);
1870 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1871 &bar0->xgxs_rxgxs_err_mask);
1872 }
1873
1874 if (mask & MC_INTR) {
1875 gen_int_mask |= MC_INT_M;
1876 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1877 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1878 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1879 &bar0->mc_err_mask);
1880 }
1881 nic->general_int_mask = gen_int_mask;
1882
1883 /* Remove this line when alarm interrupts are enabled */
1884 nic->general_int_mask = 0;
1885 }
1886 /**
1887 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1888 * @nic: device private variable,
1889 * @mask: A mask indicating which Intr block must be modified and,
1890 * @flag: A flag indicating whether to enable or disable the Intrs.
1891 * Description: This function will either disable or enable the interrupts
1892 * depending on the flag argument. The mask argument can be used to
1893 * enable/disable any Intr block.
1894 * Return Value: NONE.
1895 */
1896
1897 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1898 {
1899 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1900 register u64 temp64 = 0, intr_mask = 0;
1901
1902 intr_mask = nic->general_int_mask;
1903
1904 /* Top level interrupt classification */
1905 /* PIC Interrupts */
1906 if (mask & TX_PIC_INTR) {
1907 /* Enable PIC Intrs in the general intr mask register */
1908 intr_mask |= TXPIC_INT_M;
1909 if (flag == ENABLE_INTRS) {
1910 /*
1911 * If Hercules adapter enable GPIO otherwise
1912 * disable all PCIX, Flash, MDIO, IIC and GPIO
1913 * interrupts for now.
1914 * TODO
1915 */
1916 if (s2io_link_fault_indication(nic) ==
1917 LINK_UP_DOWN_INTERRUPT ) {
1918 do_s2io_write_bits(PIC_INT_GPIO, flag,
1919 &bar0->pic_int_mask);
1920 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1921 &bar0->gpio_int_mask);
1922 } else
1923 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1924 } else if (flag == DISABLE_INTRS) {
1925 /*
1926 * Disable PIC Intrs in the general
1927 * intr mask register
1928 */
1929 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1930 }
1931 }
1932
1933 /* Tx traffic interrupts */
1934 if (mask & TX_TRAFFIC_INTR) {
1935 intr_mask |= TXTRAFFIC_INT_M;
1936 if (flag == ENABLE_INTRS) {
1937 /*
1938 * Enable all the Tx side interrupts
1939 * writing 0 Enables all 64 TX interrupt levels
1940 */
1941 writeq(0x0, &bar0->tx_traffic_mask);
1942 } else if (flag == DISABLE_INTRS) {
1943 /*
1944 * Disable Tx Traffic Intrs in the general intr mask
1945 * register.
1946 */
1947 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1948 }
1949 }
1950
1951 /* Rx traffic interrupts */
1952 if (mask & RX_TRAFFIC_INTR) {
1953 intr_mask |= RXTRAFFIC_INT_M;
1954 if (flag == ENABLE_INTRS) {
1955 /* writing 0 Enables all 8 RX interrupt levels */
1956 writeq(0x0, &bar0->rx_traffic_mask);
1957 } else if (flag == DISABLE_INTRS) {
1958 /*
1959 * Disable Rx Traffic Intrs in the general intr mask
1960 * register.
1961 */
1962 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1963 }
1964 }
1965
1966 temp64 = readq(&bar0->general_int_mask);
1967 if (flag == ENABLE_INTRS)
1968 temp64 &= ~((u64) intr_mask);
1969 else
1970 temp64 = DISABLE_ALL_INTRS;
1971 writeq(temp64, &bar0->general_int_mask);
1972
1973 nic->general_int_mask = readq(&bar0->general_int_mask);
1974 }
1975
1976 /**
1977 * verify_pcc_quiescent- Checks for PCC quiescent state
1978 * Return: 1 If PCC is quiescence
1979 * 0 If PCC is not quiescence
1980 */
1981 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
1982 {
1983 int ret = 0, herc;
1984 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1985 u64 val64 = readq(&bar0->adapter_status);
1986
1987 herc = (sp->device_type == XFRAME_II_DEVICE);
1988
1989 if (flag == FALSE) {
1990 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
1991 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1992 ret = 1;
1993 } else {
1994 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1995 ret = 1;
1996 }
1997 } else {
1998 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
1999 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2000 ADAPTER_STATUS_RMAC_PCC_IDLE))
2001 ret = 1;
2002 } else {
2003 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2004 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2005 ret = 1;
2006 }
2007 }
2008
2009 return ret;
2010 }
2011 /**
2012 * verify_xena_quiescence - Checks whether the H/W is ready
2013 * Description: Returns whether the H/W is ready to go or not. Depending
2014 * on whether adapter enable bit was written or not the comparison
2015 * differs and the calling function passes the input argument flag to
2016 * indicate this.
2017 * Return: 1 If xena is quiescence
2018 * 0 If Xena is not quiescence
2019 */
2020
2021 static int verify_xena_quiescence(struct s2io_nic *sp)
2022 {
2023 int mode;
2024 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2025 u64 val64 = readq(&bar0->adapter_status);
2026 mode = s2io_verify_pci_mode(sp);
2027
2028 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2029 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2030 return 0;
2031 }
2032 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2033 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2034 return 0;
2035 }
2036 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2037 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2038 return 0;
2039 }
2040 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2041 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2042 return 0;
2043 }
2044 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2045 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2046 return 0;
2047 }
2048 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2049 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2050 return 0;
2051 }
2052 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2053 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2054 return 0;
2055 }
2056 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2057 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2058 return 0;
2059 }
2060
2061 /*
2062 * In PCI 33 mode, the P_PLL is not used, and therefore,
2063 * the the P_PLL_LOCK bit in the adapter_status register will
2064 * not be asserted.
2065 */
2066 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2067 sp->device_type == XFRAME_II_DEVICE && mode !=
2068 PCI_MODE_PCI_33) {
2069 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2070 return 0;
2071 }
2072 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2073 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2074 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2075 return 0;
2076 }
2077 return 1;
2078 }
2079
2080 /**
2081 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2082 * @sp: Pointer to device specifc structure
2083 * Description :
2084 * New procedure to clear mac address reading problems on Alpha platforms
2085 *
2086 */
2087
2088 static void fix_mac_address(struct s2io_nic * sp)
2089 {
2090 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2091 u64 val64;
2092 int i = 0;
2093
2094 while (fix_mac[i] != END_SIGN) {
2095 writeq(fix_mac[i++], &bar0->gpio_control);
2096 udelay(10);
2097 val64 = readq(&bar0->gpio_control);
2098 }
2099 }
2100
2101 /**
2102 * start_nic - Turns the device on
2103 * @nic : device private variable.
2104 * Description:
2105 * This function actually turns the device on. Before this function is
2106 * called,all Registers are configured from their reset states
2107 * and shared memory is allocated but the NIC is still quiescent. On
2108 * calling this function, the device interrupts are cleared and the NIC is
2109 * literally switched on by writing into the adapter control register.
2110 * Return Value:
2111 * SUCCESS on success and -1 on failure.
2112 */
2113
2114 static int start_nic(struct s2io_nic *nic)
2115 {
2116 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2117 struct net_device *dev = nic->dev;
2118 register u64 val64 = 0;
2119 u16 subid, i;
2120 struct mac_info *mac_control;
2121 struct config_param *config;
2122
2123 mac_control = &nic->mac_control;
2124 config = &nic->config;
2125
2126 /* PRC Initialization and configuration */
2127 for (i = 0; i < config->rx_ring_num; i++) {
2128 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2129 &bar0->prc_rxd0_n[i]);
2130
2131 val64 = readq(&bar0->prc_ctrl_n[i]);
2132 if (nic->rxd_mode == RXD_MODE_1)
2133 val64 |= PRC_CTRL_RC_ENABLED;
2134 else
2135 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2136 if (nic->device_type == XFRAME_II_DEVICE)
2137 val64 |= PRC_CTRL_GROUP_READS;
2138 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2139 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2140 writeq(val64, &bar0->prc_ctrl_n[i]);
2141 }
2142
2143 if (nic->rxd_mode == RXD_MODE_3B) {
2144 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2145 val64 = readq(&bar0->rx_pa_cfg);
2146 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2147 writeq(val64, &bar0->rx_pa_cfg);
2148 }
2149
2150 if (vlan_tag_strip == 0) {
2151 val64 = readq(&bar0->rx_pa_cfg);
2152 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2153 writeq(val64, &bar0->rx_pa_cfg);
2154 vlan_strip_flag = 0;
2155 }
2156
2157 /*
2158 * Enabling MC-RLDRAM. After enabling the device, we timeout
2159 * for around 100ms, which is approximately the time required
2160 * for the device to be ready for operation.
2161 */
2162 val64 = readq(&bar0->mc_rldram_mrs);
2163 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2164 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2165 val64 = readq(&bar0->mc_rldram_mrs);
2166
2167 msleep(100); /* Delay by around 100 ms. */
2168
2169 /* Enabling ECC Protection. */
2170 val64 = readq(&bar0->adapter_control);
2171 val64 &= ~ADAPTER_ECC_EN;
2172 writeq(val64, &bar0->adapter_control);
2173
2174 /*
2175 * Verify if the device is ready to be enabled, if so enable
2176 * it.
2177 */
2178 val64 = readq(&bar0->adapter_status);
2179 if (!verify_xena_quiescence(nic)) {
2180 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2181 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2182 (unsigned long long) val64);
2183 return FAILURE;
2184 }
2185
2186 /*
2187 * With some switches, link might be already up at this point.
2188 * Because of this weird behavior, when we enable laser,
2189 * we may not get link. We need to handle this. We cannot
2190 * figure out which switch is misbehaving. So we are forced to
2191 * make a global change.
2192 */
2193
2194 /* Enabling Laser. */
2195 val64 = readq(&bar0->adapter_control);
2196 val64 |= ADAPTER_EOI_TX_ON;
2197 writeq(val64, &bar0->adapter_control);
2198
2199 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2200 /*
2201 * Dont see link state interrupts initally on some switches,
2202 * so directly scheduling the link state task here.
2203 */
2204 schedule_work(&nic->set_link_task);
2205 }
2206 /* SXE-002: Initialize link and activity LED */
2207 subid = nic->pdev->subsystem_device;
2208 if (((subid & 0xFF) >= 0x07) &&
2209 (nic->device_type == XFRAME_I_DEVICE)) {
2210 val64 = readq(&bar0->gpio_control);
2211 val64 |= 0x0000800000000000ULL;
2212 writeq(val64, &bar0->gpio_control);
2213 val64 = 0x0411040400000000ULL;
2214 writeq(val64, (void __iomem *)bar0 + 0x2700);
2215 }
2216
2217 return SUCCESS;
2218 }
2219 /**
2220 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2221 */
2222 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2223 TxD *txdlp, int get_off)
2224 {
2225 struct s2io_nic *nic = fifo_data->nic;
2226 struct sk_buff *skb;
2227 struct TxD *txds;
2228 u16 j, frg_cnt;
2229
2230 txds = txdlp;
2231 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2232 pci_unmap_single(nic->pdev, (dma_addr_t)
2233 txds->Buffer_Pointer, sizeof(u64),
2234 PCI_DMA_TODEVICE);
2235 txds++;
2236 }
2237
2238 skb = (struct sk_buff *) ((unsigned long)
2239 txds->Host_Control);
2240 if (!skb) {
2241 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2242 return NULL;
2243 }
2244 pci_unmap_single(nic->pdev, (dma_addr_t)
2245 txds->Buffer_Pointer,
2246 skb->len - skb->data_len,
2247 PCI_DMA_TODEVICE);
2248 frg_cnt = skb_shinfo(skb)->nr_frags;
2249 if (frg_cnt) {
2250 txds++;
2251 for (j = 0; j < frg_cnt; j++, txds++) {
2252 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2253 if (!txds->Buffer_Pointer)
2254 break;
2255 pci_unmap_page(nic->pdev, (dma_addr_t)
2256 txds->Buffer_Pointer,
2257 frag->size, PCI_DMA_TODEVICE);
2258 }
2259 }
2260 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2261 return(skb);
2262 }
2263
2264 /**
2265 * free_tx_buffers - Free all queued Tx buffers
2266 * @nic : device private variable.
2267 * Description:
2268 * Free all queued Tx buffers.
2269 * Return Value: void
2270 */
2271
2272 static void free_tx_buffers(struct s2io_nic *nic)
2273 {
2274 struct net_device *dev = nic->dev;
2275 struct sk_buff *skb;
2276 struct TxD *txdp;
2277 int i, j;
2278 struct mac_info *mac_control;
2279 struct config_param *config;
2280 int cnt = 0;
2281
2282 mac_control = &nic->mac_control;
2283 config = &nic->config;
2284
2285 for (i = 0; i < config->tx_fifo_num; i++) {
2286 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2287 txdp = (struct TxD *) \
2288 mac_control->fifos[i].list_info[j].list_virt_addr;
2289 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2290 if (skb) {
2291 nic->mac_control.stats_info->sw_stat.mem_freed
2292 += skb->truesize;
2293 dev_kfree_skb(skb);
2294 cnt++;
2295 }
2296 }
2297 DBG_PRINT(INTR_DBG,
2298 "%s:forcibly freeing %d skbs on FIFO%d\n",
2299 dev->name, cnt, i);
2300 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2301 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2302 }
2303 }
2304
2305 /**
2306 * stop_nic - To stop the nic
2307 * @nic ; device private variable.
2308 * Description:
2309 * This function does exactly the opposite of what the start_nic()
2310 * function does. This function is called to stop the device.
2311 * Return Value:
2312 * void.
2313 */
2314
2315 static void stop_nic(struct s2io_nic *nic)
2316 {
2317 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2318 register u64 val64 = 0;
2319 u16 interruptible;
2320 struct mac_info *mac_control;
2321 struct config_param *config;
2322
2323 mac_control = &nic->mac_control;
2324 config = &nic->config;
2325
2326 /* Disable all interrupts */
2327 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2328 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2329 interruptible |= TX_PIC_INTR;
2330 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2331
2332 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2333 val64 = readq(&bar0->adapter_control);
2334 val64 &= ~(ADAPTER_CNTL_EN);
2335 writeq(val64, &bar0->adapter_control);
2336 }
2337
2338 /**
2339 * fill_rx_buffers - Allocates the Rx side skbs
2340 * @nic: device private variable
2341 * @ring_no: ring number
2342 * Description:
2343 * The function allocates Rx side skbs and puts the physical
2344 * address of these buffers into the RxD buffer pointers, so that the NIC
2345 * can DMA the received frame into these locations.
2346 * The NIC supports 3 receive modes, viz
2347 * 1. single buffer,
2348 * 2. three buffer and
2349 * 3. Five buffer modes.
2350 * Each mode defines how many fragments the received frame will be split
2351 * up into by the NIC. The frame is split into L3 header, L4 Header,
2352 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2353 * is split into 3 fragments. As of now only single buffer mode is
2354 * supported.
2355 * Return Value:
2356 * SUCCESS on success or an appropriate -ve value on failure.
2357 */
2358
2359 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2360 {
2361 struct net_device *dev = nic->dev;
2362 struct sk_buff *skb;
2363 struct RxD_t *rxdp;
2364 int off, off1, size, block_no, block_no1;
2365 u32 alloc_tab = 0;
2366 u32 alloc_cnt;
2367 struct mac_info *mac_control;
2368 struct config_param *config;
2369 u64 tmp;
2370 struct buffAdd *ba;
2371 unsigned long flags;
2372 struct RxD_t *first_rxdp = NULL;
2373 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2374 struct RxD1 *rxdp1;
2375 struct RxD3 *rxdp3;
2376 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
2377
2378 mac_control = &nic->mac_control;
2379 config = &nic->config;
2380 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2381 atomic_read(&nic->rx_bufs_left[ring_no]);
2382
2383 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2384 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2385 while (alloc_tab < alloc_cnt) {
2386 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2387 block_index;
2388 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2389
2390 rxdp = mac_control->rings[ring_no].
2391 rx_blocks[block_no].rxds[off].virt_addr;
2392
2393 if ((block_no == block_no1) && (off == off1) &&
2394 (rxdp->Host_Control)) {
2395 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2396 dev->name);
2397 DBG_PRINT(INTR_DBG, " info equated\n");
2398 goto end;
2399 }
2400 if (off && (off == rxd_count[nic->rxd_mode])) {
2401 mac_control->rings[ring_no].rx_curr_put_info.
2402 block_index++;
2403 if (mac_control->rings[ring_no].rx_curr_put_info.
2404 block_index == mac_control->rings[ring_no].
2405 block_count)
2406 mac_control->rings[ring_no].rx_curr_put_info.
2407 block_index = 0;
2408 block_no = mac_control->rings[ring_no].
2409 rx_curr_put_info.block_index;
2410 if (off == rxd_count[nic->rxd_mode])
2411 off = 0;
2412 mac_control->rings[ring_no].rx_curr_put_info.
2413 offset = off;
2414 rxdp = mac_control->rings[ring_no].
2415 rx_blocks[block_no].block_virt_addr;
2416 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2417 dev->name, rxdp);
2418 }
2419 if(!napi) {
2420 spin_lock_irqsave(&nic->put_lock, flags);
2421 mac_control->rings[ring_no].put_pos =
2422 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2423 spin_unlock_irqrestore(&nic->put_lock, flags);
2424 } else {
2425 mac_control->rings[ring_no].put_pos =
2426 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2427 }
2428 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2429 ((nic->rxd_mode == RXD_MODE_3B) &&
2430 (rxdp->Control_2 & BIT(0)))) {
2431 mac_control->rings[ring_no].rx_curr_put_info.
2432 offset = off;
2433 goto end;
2434 }
2435 /* calculate size of skb based on ring mode */
2436 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2437 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2438 if (nic->rxd_mode == RXD_MODE_1)
2439 size += NET_IP_ALIGN;
2440 else
2441 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2442
2443 /* allocate skb */
2444 skb = dev_alloc_skb(size);
2445 if(!skb) {
2446 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2447 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2448 if (first_rxdp) {
2449 wmb();
2450 first_rxdp->Control_1 |= RXD_OWN_XENA;
2451 }
2452 nic->mac_control.stats_info->sw_stat. \
2453 mem_alloc_fail_cnt++;
2454 return -ENOMEM ;
2455 }
2456 nic->mac_control.stats_info->sw_stat.mem_allocated
2457 += skb->truesize;
2458 if (nic->rxd_mode == RXD_MODE_1) {
2459 /* 1 buffer mode - normal operation mode */
2460 rxdp1 = (struct RxD1*)rxdp;
2461 memset(rxdp, 0, sizeof(struct RxD1));
2462 skb_reserve(skb, NET_IP_ALIGN);
2463 rxdp1->Buffer0_ptr = pci_map_single
2464 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2465 PCI_DMA_FROMDEVICE);
2466 if( (rxdp1->Buffer0_ptr == 0) ||
2467 (rxdp1->Buffer0_ptr ==
2468 DMA_ERROR_CODE))
2469 goto pci_map_failed;
2470
2471 rxdp->Control_2 =
2472 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2473
2474 } else if (nic->rxd_mode == RXD_MODE_3B) {
2475 /*
2476 * 2 buffer mode -
2477 * 2 buffer mode provides 128
2478 * byte aligned receive buffers.
2479 */
2480
2481 rxdp3 = (struct RxD3*)rxdp;
2482 /* save buffer pointers to avoid frequent dma mapping */
2483 Buffer0_ptr = rxdp3->Buffer0_ptr;
2484 Buffer1_ptr = rxdp3->Buffer1_ptr;
2485 memset(rxdp, 0, sizeof(struct RxD3));
2486 /* restore the buffer pointers for dma sync*/
2487 rxdp3->Buffer0_ptr = Buffer0_ptr;
2488 rxdp3->Buffer1_ptr = Buffer1_ptr;
2489
2490 ba = &mac_control->rings[ring_no].ba[block_no][off];
2491 skb_reserve(skb, BUF0_LEN);
2492 tmp = (u64)(unsigned long) skb->data;
2493 tmp += ALIGN_SIZE;
2494 tmp &= ~ALIGN_SIZE;
2495 skb->data = (void *) (unsigned long)tmp;
2496 skb_reset_tail_pointer(skb);
2497
2498 if (!(rxdp3->Buffer0_ptr))
2499 rxdp3->Buffer0_ptr =
2500 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2501 PCI_DMA_FROMDEVICE);
2502 else
2503 pci_dma_sync_single_for_device(nic->pdev,
2504 (dma_addr_t) rxdp3->Buffer0_ptr,
2505 BUF0_LEN, PCI_DMA_FROMDEVICE);
2506 if( (rxdp3->Buffer0_ptr == 0) ||
2507 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2508 goto pci_map_failed;
2509
2510 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2511 if (nic->rxd_mode == RXD_MODE_3B) {
2512 /* Two buffer mode */
2513
2514 /*
2515 * Buffer2 will have L3/L4 header plus
2516 * L4 payload
2517 */
2518 rxdp3->Buffer2_ptr = pci_map_single
2519 (nic->pdev, skb->data, dev->mtu + 4,
2520 PCI_DMA_FROMDEVICE);
2521
2522 if( (rxdp3->Buffer2_ptr == 0) ||
2523 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2524 goto pci_map_failed;
2525
2526 rxdp3->Buffer1_ptr =
2527 pci_map_single(nic->pdev,
2528 ba->ba_1, BUF1_LEN,
2529 PCI_DMA_FROMDEVICE);
2530 if( (rxdp3->Buffer1_ptr == 0) ||
2531 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2532 pci_unmap_single
2533 (nic->pdev,
2534 (dma_addr_t)rxdp3->Buffer2_ptr,
2535 dev->mtu + 4,
2536 PCI_DMA_FROMDEVICE);
2537 goto pci_map_failed;
2538 }
2539 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2540 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2541 (dev->mtu + 4);
2542 }
2543 rxdp->Control_2 |= BIT(0);
2544 }
2545 rxdp->Host_Control = (unsigned long) (skb);
2546 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2547 rxdp->Control_1 |= RXD_OWN_XENA;
2548 off++;
2549 if (off == (rxd_count[nic->rxd_mode] + 1))
2550 off = 0;
2551 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2552
2553 rxdp->Control_2 |= SET_RXD_MARKER;
2554 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2555 if (first_rxdp) {
2556 wmb();
2557 first_rxdp->Control_1 |= RXD_OWN_XENA;
2558 }
2559 first_rxdp = rxdp;
2560 }
2561 atomic_inc(&nic->rx_bufs_left[ring_no]);
2562 alloc_tab++;
2563 }
2564
2565 end:
2566 /* Transfer ownership of first descriptor to adapter just before
2567 * exiting. Before that, use memory barrier so that ownership
2568 * and other fields are seen by adapter correctly.
2569 */
2570 if (first_rxdp) {
2571 wmb();
2572 first_rxdp->Control_1 |= RXD_OWN_XENA;
2573 }
2574
2575 return SUCCESS;
2576 pci_map_failed:
2577 stats->pci_map_fail_cnt++;
2578 stats->mem_freed += skb->truesize;
2579 dev_kfree_skb_irq(skb);
2580 return -ENOMEM;
2581 }
2582
2583 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2584 {
2585 struct net_device *dev = sp->dev;
2586 int j;
2587 struct sk_buff *skb;
2588 struct RxD_t *rxdp;
2589 struct mac_info *mac_control;
2590 struct buffAdd *ba;
2591 struct RxD1 *rxdp1;
2592 struct RxD3 *rxdp3;
2593
2594 mac_control = &sp->mac_control;
2595 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2596 rxdp = mac_control->rings[ring_no].
2597 rx_blocks[blk].rxds[j].virt_addr;
2598 skb = (struct sk_buff *)
2599 ((unsigned long) rxdp->Host_Control);
2600 if (!skb) {
2601 continue;
2602 }
2603 if (sp->rxd_mode == RXD_MODE_1) {
2604 rxdp1 = (struct RxD1*)rxdp;
2605 pci_unmap_single(sp->pdev, (dma_addr_t)
2606 rxdp1->Buffer0_ptr,
2607 dev->mtu +
2608 HEADER_ETHERNET_II_802_3_SIZE
2609 + HEADER_802_2_SIZE +
2610 HEADER_SNAP_SIZE,
2611 PCI_DMA_FROMDEVICE);
2612 memset(rxdp, 0, sizeof(struct RxD1));
2613 } else if(sp->rxd_mode == RXD_MODE_3B) {
2614 rxdp3 = (struct RxD3*)rxdp;
2615 ba = &mac_control->rings[ring_no].
2616 ba[blk][j];
2617 pci_unmap_single(sp->pdev, (dma_addr_t)
2618 rxdp3->Buffer0_ptr,
2619 BUF0_LEN,
2620 PCI_DMA_FROMDEVICE);
2621 pci_unmap_single(sp->pdev, (dma_addr_t)
2622 rxdp3->Buffer1_ptr,
2623 BUF1_LEN,
2624 PCI_DMA_FROMDEVICE);
2625 pci_unmap_single(sp->pdev, (dma_addr_t)
2626 rxdp3->Buffer2_ptr,
2627 dev->mtu + 4,
2628 PCI_DMA_FROMDEVICE);
2629 memset(rxdp, 0, sizeof(struct RxD3));
2630 }
2631 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2632 dev_kfree_skb(skb);
2633 atomic_dec(&sp->rx_bufs_left[ring_no]);
2634 }
2635 }
2636
2637 /**
2638 * free_rx_buffers - Frees all Rx buffers
2639 * @sp: device private variable.
2640 * Description:
2641 * This function will free all Rx buffers allocated by host.
2642 * Return Value:
2643 * NONE.
2644 */
2645
2646 static void free_rx_buffers(struct s2io_nic *sp)
2647 {
2648 struct net_device *dev = sp->dev;
2649 int i, blk = 0, buf_cnt = 0;
2650 struct mac_info *mac_control;
2651 struct config_param *config;
2652
2653 mac_control = &sp->mac_control;
2654 config = &sp->config;
2655
2656 for (i = 0; i < config->rx_ring_num; i++) {
2657 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2658 free_rxd_blk(sp,i,blk);
2659
2660 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2661 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2662 mac_control->rings[i].rx_curr_put_info.offset = 0;
2663 mac_control->rings[i].rx_curr_get_info.offset = 0;
2664 atomic_set(&sp->rx_bufs_left[i], 0);
2665 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2666 dev->name, buf_cnt, i);
2667 }
2668 }
2669
2670 /**
2671 * s2io_poll - Rx interrupt handler for NAPI support
2672 * @napi : pointer to the napi structure.
2673 * @budget : The number of packets that were budgeted to be processed
2674 * during one pass through the 'Poll" function.
2675 * Description:
2676 * Comes into picture only if NAPI support has been incorporated. It does
2677 * the same thing that rx_intr_handler does, but not in a interrupt context
2678 * also It will process only a given number of packets.
2679 * Return value:
2680 * 0 on success and 1 if there are No Rx packets to be processed.
2681 */
2682
2683 static int s2io_poll(struct napi_struct *napi, int budget)
2684 {
2685 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2686 struct net_device *dev = nic->dev;
2687 int pkt_cnt = 0, org_pkts_to_process;
2688 struct mac_info *mac_control;
2689 struct config_param *config;
2690 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2691 int i;
2692
2693 if (!is_s2io_card_up(nic))
2694 return 0;
2695
2696 mac_control = &nic->mac_control;
2697 config = &nic->config;
2698
2699 nic->pkts_to_process = budget;
2700 org_pkts_to_process = nic->pkts_to_process;
2701
2702 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2703 readl(&bar0->rx_traffic_int);
2704
2705 for (i = 0; i < config->rx_ring_num; i++) {
2706 rx_intr_handler(&mac_control->rings[i]);
2707 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2708 if (!nic->pkts_to_process) {
2709 /* Quota for the current iteration has been met */
2710 goto no_rx;
2711 }
2712 }
2713
2714 netif_rx_complete(dev, napi);
2715
2716 for (i = 0; i < config->rx_ring_num; i++) {
2717 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2718 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2719 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2720 break;
2721 }
2722 }
2723 /* Re enable the Rx interrupts. */
2724 writeq(0x0, &bar0->rx_traffic_mask);
2725 readl(&bar0->rx_traffic_mask);
2726 return pkt_cnt;
2727
2728 no_rx:
2729 for (i = 0; i < config->rx_ring_num; i++) {
2730 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2731 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2732 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2733 break;
2734 }
2735 }
2736 return pkt_cnt;
2737 }
2738
2739 #ifdef CONFIG_NET_POLL_CONTROLLER
2740 /**
2741 * s2io_netpoll - netpoll event handler entry point
2742 * @dev : pointer to the device structure.
2743 * Description:
2744 * This function will be called by upper layer to check for events on the
2745 * interface in situations where interrupts are disabled. It is used for
2746 * specific in-kernel networking tasks, such as remote consoles and kernel
2747 * debugging over the network (example netdump in RedHat).
2748 */
2749 static void s2io_netpoll(struct net_device *dev)
2750 {
2751 struct s2io_nic *nic = dev->priv;
2752 struct mac_info *mac_control;
2753 struct config_param *config;
2754 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2755 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2756 int i;
2757
2758 if (pci_channel_offline(nic->pdev))
2759 return;
2760
2761 disable_irq(dev->irq);
2762
2763 mac_control = &nic->mac_control;
2764 config = &nic->config;
2765
2766 writeq(val64, &bar0->rx_traffic_int);
2767 writeq(val64, &bar0->tx_traffic_int);
2768
2769 /* we need to free up the transmitted skbufs or else netpoll will
2770 * run out of skbs and will fail and eventually netpoll application such
2771 * as netdump will fail.
2772 */
2773 for (i = 0; i < config->tx_fifo_num; i++)
2774 tx_intr_handler(&mac_control->fifos[i]);
2775
2776 /* check for received packet and indicate up to network */
2777 for (i = 0; i < config->rx_ring_num; i++)
2778 rx_intr_handler(&mac_control->rings[i]);
2779
2780 for (i = 0; i < config->rx_ring_num; i++) {
2781 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2782 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2783 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2784 break;
2785 }
2786 }
2787 enable_irq(dev->irq);
2788 return;
2789 }
2790 #endif
2791
2792 /**
2793 * rx_intr_handler - Rx interrupt handler
2794 * @nic: device private variable.
2795 * Description:
2796 * If the interrupt is because of a received frame or if the
2797 * receive ring contains fresh as yet un-processed frames,this function is
2798 * called. It picks out the RxD at which place the last Rx processing had
2799 * stopped and sends the skb to the OSM's Rx handler and then increments
2800 * the offset.
2801 * Return Value:
2802 * NONE.
2803 */
2804 static void rx_intr_handler(struct ring_info *ring_data)
2805 {
2806 struct s2io_nic *nic = ring_data->nic;
2807 struct net_device *dev = (struct net_device *) nic->dev;
2808 int get_block, put_block, put_offset;
2809 struct rx_curr_get_info get_info, put_info;
2810 struct RxD_t *rxdp;
2811 struct sk_buff *skb;
2812 int pkt_cnt = 0;
2813 int i;
2814 struct RxD1* rxdp1;
2815 struct RxD3* rxdp3;
2816
2817 spin_lock(&nic->rx_lock);
2818
2819 get_info = ring_data->rx_curr_get_info;
2820 get_block = get_info.block_index;
2821 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2822 put_block = put_info.block_index;
2823 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2824 if (!napi) {
2825 spin_lock(&nic->put_lock);
2826 put_offset = ring_data->put_pos;
2827 spin_unlock(&nic->put_lock);
2828 } else
2829 put_offset = ring_data->put_pos;
2830
2831 while (RXD_IS_UP2DT(rxdp)) {
2832 /*
2833 * If your are next to put index then it's
2834 * FIFO full condition
2835 */
2836 if ((get_block == put_block) &&
2837 (get_info.offset + 1) == put_info.offset) {
2838 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2839 break;
2840 }
2841 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2842 if (skb == NULL) {
2843 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2844 dev->name);
2845 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2846 spin_unlock(&nic->rx_lock);
2847 return;
2848 }
2849 if (nic->rxd_mode == RXD_MODE_1) {
2850 rxdp1 = (struct RxD1*)rxdp;
2851 pci_unmap_single(nic->pdev, (dma_addr_t)
2852 rxdp1->Buffer0_ptr,
2853 dev->mtu +
2854 HEADER_ETHERNET_II_802_3_SIZE +
2855 HEADER_802_2_SIZE +
2856 HEADER_SNAP_SIZE,
2857 PCI_DMA_FROMDEVICE);
2858 } else if (nic->rxd_mode == RXD_MODE_3B) {
2859 rxdp3 = (struct RxD3*)rxdp;
2860 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2861 rxdp3->Buffer0_ptr,
2862 BUF0_LEN, PCI_DMA_FROMDEVICE);
2863 pci_unmap_single(nic->pdev, (dma_addr_t)
2864 rxdp3->Buffer2_ptr,
2865 dev->mtu + 4,
2866 PCI_DMA_FROMDEVICE);
2867 }
2868 prefetch(skb->data);
2869 rx_osm_handler(ring_data, rxdp);
2870 get_info.offset++;
2871 ring_data->rx_curr_get_info.offset = get_info.offset;
2872 rxdp = ring_data->rx_blocks[get_block].
2873 rxds[get_info.offset].virt_addr;
2874 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2875 get_info.offset = 0;
2876 ring_data->rx_curr_get_info.offset = get_info.offset;
2877 get_block++;
2878 if (get_block == ring_data->block_count)
2879 get_block = 0;
2880 ring_data->rx_curr_get_info.block_index = get_block;
2881 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2882 }
2883
2884 nic->pkts_to_process -= 1;
2885 if ((napi) && (!nic->pkts_to_process))
2886 break;
2887 pkt_cnt++;
2888 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2889 break;
2890 }
2891 if (nic->lro) {
2892 /* Clear all LRO sessions before exiting */
2893 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2894 struct lro *lro = &nic->lro0_n[i];
2895 if (lro->in_use) {
2896 update_L3L4_header(nic, lro);
2897 queue_rx_frame(lro->parent);
2898 clear_lro_session(lro);
2899 }
2900 }
2901 }
2902
2903 spin_unlock(&nic->rx_lock);
2904 }
2905
2906 /**
2907 * tx_intr_handler - Transmit interrupt handler
2908 * @nic : device private variable
2909 * Description:
2910 * If an interrupt was raised to indicate DMA complete of the
2911 * Tx packet, this function is called. It identifies the last TxD
2912 * whose buffer was freed and frees all skbs whose data have already
2913 * DMA'ed into the NICs internal memory.
2914 * Return Value:
2915 * NONE
2916 */
2917
2918 static void tx_intr_handler(struct fifo_info *fifo_data)
2919 {
2920 struct s2io_nic *nic = fifo_data->nic;
2921 struct net_device *dev = (struct net_device *) nic->dev;
2922 struct tx_curr_get_info get_info, put_info;
2923 struct sk_buff *skb;
2924 struct TxD *txdlp;
2925 u8 err_mask;
2926
2927 get_info = fifo_data->tx_curr_get_info;
2928 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2929 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2930 list_virt_addr;
2931 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2932 (get_info.offset != put_info.offset) &&
2933 (txdlp->Host_Control)) {
2934 /* Check for TxD errors */
2935 if (txdlp->Control_1 & TXD_T_CODE) {
2936 unsigned long long err;
2937 err = txdlp->Control_1 & TXD_T_CODE;
2938 if (err & 0x1) {
2939 nic->mac_control.stats_info->sw_stat.
2940 parity_err_cnt++;
2941 }
2942
2943 /* update t_code statistics */
2944 err_mask = err >> 48;
2945 switch(err_mask) {
2946 case 2:
2947 nic->mac_control.stats_info->sw_stat.
2948 tx_buf_abort_cnt++;
2949 break;
2950
2951 case 3:
2952 nic->mac_control.stats_info->sw_stat.
2953 tx_desc_abort_cnt++;
2954 break;
2955
2956 case 7:
2957 nic->mac_control.stats_info->sw_stat.
2958 tx_parity_err_cnt++;
2959 break;
2960
2961 case 10:
2962 nic->mac_control.stats_info->sw_stat.
2963 tx_link_loss_cnt++;
2964 break;
2965
2966 case 15:
2967 nic->mac_control.stats_info->sw_stat.
2968 tx_list_proc_err_cnt++;
2969 break;
2970 }
2971 }
2972
2973 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2974 if (skb == NULL) {
2975 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2976 __FUNCTION__);
2977 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2978 return;
2979 }
2980
2981 /* Updating the statistics block */
2982 nic->stats.tx_bytes += skb->len;
2983 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2984 dev_kfree_skb_irq(skb);
2985
2986 get_info.offset++;
2987 if (get_info.offset == get_info.fifo_len + 1)
2988 get_info.offset = 0;
2989 txdlp = (struct TxD *) fifo_data->list_info
2990 [get_info.offset].list_virt_addr;
2991 fifo_data->tx_curr_get_info.offset =
2992 get_info.offset;
2993 }
2994
2995 spin_lock(&nic->tx_lock);
2996 if (netif_queue_stopped(dev))
2997 netif_wake_queue(dev);
2998 spin_unlock(&nic->tx_lock);
2999 }
3000
3001 /**
3002 * s2io_mdio_write - Function to write in to MDIO registers
3003 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3004 * @addr : address value
3005 * @value : data value
3006 * @dev : pointer to net_device structure
3007 * Description:
3008 * This function is used to write values to the MDIO registers
3009 * NONE
3010 */
3011 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3012 {
3013 u64 val64 = 0x0;
3014 struct s2io_nic *sp = dev->priv;
3015 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3016
3017 //address transaction
3018 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3019 | MDIO_MMD_DEV_ADDR(mmd_type)
3020 | MDIO_MMS_PRT_ADDR(0x0);
3021 writeq(val64, &bar0->mdio_control);
3022 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3023 writeq(val64, &bar0->mdio_control);
3024 udelay(100);
3025
3026 //Data transaction
3027 val64 = 0x0;
3028 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3029 | MDIO_MMD_DEV_ADDR(mmd_type)
3030 | MDIO_MMS_PRT_ADDR(0x0)
3031 | MDIO_MDIO_DATA(value)
3032 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3033 writeq(val64, &bar0->mdio_control);
3034 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3035 writeq(val64, &bar0->mdio_control);
3036 udelay(100);
3037
3038 val64 = 0x0;
3039 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3040 | MDIO_MMD_DEV_ADDR(mmd_type)
3041 | MDIO_MMS_PRT_ADDR(0x0)
3042 | MDIO_OP(MDIO_OP_READ_TRANS);
3043 writeq(val64, &bar0->mdio_control);
3044 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3045 writeq(val64, &bar0->mdio_control);
3046 udelay(100);
3047
3048 }
3049
3050 /**
3051 * s2io_mdio_read - Function to write in to MDIO registers
3052 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3053 * @addr : address value
3054 * @dev : pointer to net_device structure
3055 * Description:
3056 * This function is used to read values to the MDIO registers
3057 * NONE
3058 */
3059 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3060 {
3061 u64 val64 = 0x0;
3062 u64 rval64 = 0x0;
3063 struct s2io_nic *sp = dev->priv;
3064 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3065
3066 /* address transaction */
3067 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3068 | MDIO_MMD_DEV_ADDR(mmd_type)
3069 | MDIO_MMS_PRT_ADDR(0x0);
3070 writeq(val64, &bar0->mdio_control);
3071 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3072 writeq(val64, &bar0->mdio_control);
3073 udelay(100);
3074
3075 /* Data transaction */
3076 val64 = 0x0;
3077 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3078 | MDIO_MMD_DEV_ADDR(mmd_type)
3079 | MDIO_MMS_PRT_ADDR(0x0)
3080 | MDIO_OP(MDIO_OP_READ_TRANS);
3081 writeq(val64, &bar0->mdio_control);
3082 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3083 writeq(val64, &bar0->mdio_control);
3084 udelay(100);
3085
3086 /* Read the value from regs */
3087 rval64 = readq(&bar0->mdio_control);
3088 rval64 = rval64 & 0xFFFF0000;
3089 rval64 = rval64 >> 16;
3090 return rval64;
3091 }
3092 /**
3093 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3094 * @counter : couter value to be updated
3095 * @flag : flag to indicate the status
3096 * @type : counter type
3097 * Description:
3098 * This function is to check the status of the xpak counters value
3099 * NONE
3100 */
3101
3102 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3103 {
3104 u64 mask = 0x3;
3105 u64 val64;
3106 int i;
3107 for(i = 0; i <index; i++)
3108 mask = mask << 0x2;
3109
3110 if(flag > 0)
3111 {
3112 *counter = *counter + 1;
3113 val64 = *regs_stat & mask;
3114 val64 = val64 >> (index * 0x2);
3115 val64 = val64 + 1;
3116 if(val64 == 3)
3117 {
3118 switch(type)
3119 {
3120 case 1:
3121 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3122 "service. Excessive temperatures may "
3123 "result in premature transceiver "
3124 "failure \n");
3125 break;
3126 case 2:
3127 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3128 "service Excessive bias currents may "
3129 "indicate imminent laser diode "
3130 "failure \n");
3131 break;
3132 case 3:
3133 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3134 "service Excessive laser output "
3135 "power may saturate far-end "
3136 "receiver\n");
3137 break;
3138 default:
3139 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3140 "type \n");
3141 }
3142 val64 = 0x0;
3143 }
3144 val64 = val64 << (index * 0x2);
3145 *regs_stat = (*regs_stat & (~mask)) | (val64);
3146
3147 } else {
3148 *regs_stat = *regs_stat & (~mask);
3149 }
3150 }
3151
3152 /**
3153 * s2io_updt_xpak_counter - Function to update the xpak counters
3154 * @dev : pointer to net_device struct
3155 * Description:
3156 * This function is to upate the status of the xpak counters value
3157 * NONE
3158 */
3159 static void s2io_updt_xpak_counter(struct net_device *dev)
3160 {
3161 u16 flag = 0x0;
3162 u16 type = 0x0;
3163 u16 val16 = 0x0;
3164 u64 val64 = 0x0;
3165 u64 addr = 0x0;
3166
3167 struct s2io_nic *sp = dev->priv;
3168 struct stat_block *stat_info = sp->mac_control.stats_info;
3169
3170 /* Check the communication with the MDIO slave */
3171 addr = 0x0000;
3172 val64 = 0x0;
3173 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3174 if((val64 == 0xFFFF) || (val64 == 0x0000))
3175 {
3176 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3177 "Returned %llx\n", (unsigned long long)val64);
3178 return;
3179 }
3180
3181 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3182 if(val64 != 0x2040)
3183 {
3184 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3185 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3186 (unsigned long long)val64);
3187 return;
3188 }
3189
3190 /* Loading the DOM register to MDIO register */
3191 addr = 0xA100;
3192 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3193 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3194
3195 /* Reading the Alarm flags */
3196 addr = 0xA070;
3197 val64 = 0x0;
3198 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3199
3200 flag = CHECKBIT(val64, 0x7);
3201 type = 1;
3202 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3203 &stat_info->xpak_stat.xpak_regs_stat,
3204 0x0, flag, type);
3205
3206 if(CHECKBIT(val64, 0x6))
3207 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3208
3209 flag = CHECKBIT(val64, 0x3);
3210 type = 2;
3211 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3212 &stat_info->xpak_stat.xpak_regs_stat,
3213 0x2, flag, type);
3214
3215 if(CHECKBIT(val64, 0x2))
3216 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3217
3218 flag = CHECKBIT(val64, 0x1);
3219 type = 3;
3220 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3221 &stat_info->xpak_stat.xpak_regs_stat,
3222 0x4, flag, type);
3223
3224 if(CHECKBIT(val64, 0x0))
3225 stat_info->xpak_stat.alarm_laser_output_power_low++;
3226
3227 /* Reading the Warning flags */
3228 addr = 0xA074;
3229 val64 = 0x0;
3230 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3231
3232 if(CHECKBIT(val64, 0x7))
3233 stat_info->xpak_stat.warn_transceiver_temp_high++;
3234
3235 if(CHECKBIT(val64, 0x6))
3236 stat_info->xpak_stat.warn_transceiver_temp_low++;
3237
3238 if(CHECKBIT(val64, 0x3))
3239 stat_info->xpak_stat.warn_laser_bias_current_high++;
3240
3241 if(CHECKBIT(val64, 0x2))
3242 stat_info->xpak_stat.warn_laser_bias_current_low++;
3243
3244 if(CHECKBIT(val64, 0x1))
3245 stat_info->xpak_stat.warn_laser_output_power_high++;
3246
3247 if(CHECKBIT(val64, 0x0))
3248 stat_info->xpak_stat.warn_laser_output_power_low++;
3249 }
3250
3251 /**
3252 * wait_for_cmd_complete - waits for a command to complete.
3253 * @sp : private member of the device structure, which is a pointer to the
3254 * s2io_nic structure.
3255 * Description: Function that waits for a command to Write into RMAC
3256 * ADDR DATA registers to be completed and returns either success or
3257 * error depending on whether the command was complete or not.
3258 * Return value:
3259 * SUCCESS on success and FAILURE on failure.
3260 */
3261
3262 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3263 int bit_state)
3264 {
3265 int ret = FAILURE, cnt = 0, delay = 1;
3266 u64 val64;
3267
3268 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3269 return FAILURE;
3270
3271 do {
3272 val64 = readq(addr);
3273 if (bit_state == S2IO_BIT_RESET) {
3274 if (!(val64 & busy_bit)) {
3275 ret = SUCCESS;
3276 break;
3277 }
3278 } else {
3279 if (!(val64 & busy_bit)) {
3280 ret = SUCCESS;
3281 break;
3282 }
3283 }
3284
3285 if(in_interrupt())
3286 mdelay(delay);
3287 else
3288 msleep(delay);
3289
3290 if (++cnt >= 10)
3291 delay = 50;
3292 } while (cnt < 20);
3293 return ret;
3294 }
3295 /*
3296 * check_pci_device_id - Checks if the device id is supported
3297 * @id : device id
3298 * Description: Function to check if the pci device id is supported by driver.
3299 * Return value: Actual device id if supported else PCI_ANY_ID
3300 */
3301 static u16 check_pci_device_id(u16 id)
3302 {
3303 switch (id) {
3304 case PCI_DEVICE_ID_HERC_WIN:
3305 case PCI_DEVICE_ID_HERC_UNI:
3306 return XFRAME_II_DEVICE;
3307 case PCI_DEVICE_ID_S2IO_UNI:
3308 case PCI_DEVICE_ID_S2IO_WIN:
3309 return XFRAME_I_DEVICE;
3310 default:
3311 return PCI_ANY_ID;
3312 }
3313 }
3314
3315 /**
3316 * s2io_reset - Resets the card.
3317 * @sp : private member of the device structure.
3318 * Description: Function to Reset the card. This function then also
3319 * restores the previously saved PCI configuration space registers as
3320 * the card reset also resets the configuration space.
3321 * Return value:
3322 * void.
3323 */
3324
3325 static void s2io_reset(struct s2io_nic * sp)
3326 {
3327 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3328 u64 val64;
3329 u16 subid, pci_cmd;
3330 int i;
3331 u16 val16;
3332 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3333 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3334
3335 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3336 __FUNCTION__, sp->dev->name);
3337
3338 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3339 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3340
3341 val64 = SW_RESET_ALL;
3342 writeq(val64, &bar0->sw_reset);
3343 if (strstr(sp->product_name, "CX4")) {
3344 msleep(750);
3345 }
3346 msleep(250);
3347 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3348
3349 /* Restore the PCI state saved during initialization. */
3350 pci_restore_state(sp->pdev);
3351 pci_read_config_word(sp->pdev, 0x2, &val16);
3352 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3353 break;
3354 msleep(200);
3355 }
3356
3357 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3358 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3359 }
3360
3361 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3362
3363 s2io_init_pci(sp);
3364
3365 /* Set swapper to enable I/O register access */
3366 s2io_set_swapper(sp);
3367
3368 /* Restore the MSIX table entries from local variables */
3369 restore_xmsi_data(sp);
3370
3371 /* Clear certain PCI/PCI-X fields after reset */
3372 if (sp->device_type == XFRAME_II_DEVICE) {
3373 /* Clear "detected parity error" bit */
3374 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3375
3376 /* Clearing PCIX Ecc status register */
3377 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3378
3379 /* Clearing PCI_STATUS error reflected here */
3380 writeq(BIT(62), &bar0->txpic_int_reg);
3381 }
3382
3383 /* Reset device statistics maintained by OS */
3384 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3385
3386 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3387 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3388 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3389 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3390 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3391 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3392 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3393 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3394 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3395 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3396 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3397 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3398 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3399 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3400 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3401 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3402 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3403 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3404 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3405
3406 /* SXE-002: Configure link and activity LED to turn it off */
3407 subid = sp->pdev->subsystem_device;
3408 if (((subid & 0xFF) >= 0x07) &&
3409 (sp->device_type == XFRAME_I_DEVICE)) {
3410 val64 = readq(&bar0->gpio_control);
3411 val64 |= 0x0000800000000000ULL;
3412 writeq(val64, &bar0->gpio_control);
3413 val64 = 0x0411040400000000ULL;
3414 writeq(val64, (void __iomem *)bar0 + 0x2700);
3415 }
3416
3417 /*
3418 * Clear spurious ECC interrupts that would have occured on
3419 * XFRAME II cards after reset.
3420 */
3421 if (sp->device_type == XFRAME_II_DEVICE) {
3422 val64 = readq(&bar0->pcc_err_reg);
3423 writeq(val64, &bar0->pcc_err_reg);
3424 }
3425
3426 /* restore the previously assigned mac address */
3427 do_s2io_prog_unicast(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3428
3429 sp->device_enabled_once = FALSE;
3430 }
3431
3432 /**
3433 * s2io_set_swapper - to set the swapper controle on the card
3434 * @sp : private member of the device structure,
3435 * pointer to the s2io_nic structure.
3436 * Description: Function to set the swapper control on the card
3437 * correctly depending on the 'endianness' of the system.
3438 * Return value:
3439 * SUCCESS on success and FAILURE on failure.
3440 */
3441
3442 static int s2io_set_swapper(struct s2io_nic * sp)
3443 {
3444 struct net_device *dev = sp->dev;
3445 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3446 u64 val64, valt, valr;
3447
3448 /*
3449 * Set proper endian settings and verify the same by reading
3450 * the PIF Feed-back register.
3451 */
3452
3453 val64 = readq(&bar0->pif_rd_swapper_fb);
3454 if (val64 != 0x0123456789ABCDEFULL) {
3455 int i = 0;
3456 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3457 0x8100008181000081ULL, /* FE=1, SE=0 */
3458 0x4200004242000042ULL, /* FE=0, SE=1 */
3459 0}; /* FE=0, SE=0 */
3460
3461 while(i<4) {
3462 writeq(value[i], &bar0->swapper_ctrl);
3463 val64 = readq(&bar0->pif_rd_swapper_fb);
3464 if (val64 == 0x0123456789ABCDEFULL)
3465 break;
3466 i++;
3467 }
3468 if (i == 4) {
3469 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3470 dev->name);
3471 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3472 (unsigned long long) val64);
3473 return FAILURE;
3474 }
3475 valr = value[i];
3476 } else {
3477 valr = readq(&bar0->swapper_ctrl);
3478 }
3479
3480 valt = 0x0123456789ABCDEFULL;
3481 writeq(valt, &bar0->xmsi_address);
3482 val64 = readq(&bar0->xmsi_address);
3483
3484 if(val64 != valt) {
3485 int i = 0;
3486 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3487 0x0081810000818100ULL, /* FE=1, SE=0 */
3488 0x0042420000424200ULL, /* FE=0, SE=1 */
3489 0}; /* FE=0, SE=0 */
3490
3491 while(i<4) {
3492 writeq((value[i] | valr), &bar0->swapper_ctrl);
3493 writeq(valt, &bar0->xmsi_address);
3494 val64 = readq(&bar0->xmsi_address);
3495 if(val64 == valt)
3496 break;
3497 i++;
3498 }
3499 if(i == 4) {
3500 unsigned long long x = val64;
3501 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3502 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3503 return FAILURE;
3504 }
3505 }
3506 val64 = readq(&bar0->swapper_ctrl);
3507 val64 &= 0xFFFF000000000000ULL;
3508
3509 #ifdef __BIG_ENDIAN
3510 /*
3511 * The device by default set to a big endian format, so a
3512 * big endian driver need not set anything.
3513 */
3514 val64 |= (SWAPPER_CTRL_TXP_FE |
3515 SWAPPER_CTRL_TXP_SE |
3516 SWAPPER_CTRL_TXD_R_FE |
3517 SWAPPER_CTRL_TXD_W_FE |
3518 SWAPPER_CTRL_TXF_R_FE |
3519 SWAPPER_CTRL_RXD_R_FE |
3520 SWAPPER_CTRL_RXD_W_FE |
3521 SWAPPER_CTRL_RXF_W_FE |
3522 SWAPPER_CTRL_XMSI_FE |
3523 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3524 if (sp->config.intr_type == INTA)
3525 val64 |= SWAPPER_CTRL_XMSI_SE;
3526 writeq(val64, &bar0->swapper_ctrl);
3527 #else
3528 /*
3529 * Initially we enable all bits to make it accessible by the
3530 * driver, then we selectively enable only those bits that
3531 * we want to set.
3532 */
3533 val64 |= (SWAPPER_CTRL_TXP_FE |
3534 SWAPPER_CTRL_TXP_SE |
3535 SWAPPER_CTRL_TXD_R_FE |
3536 SWAPPER_CTRL_TXD_R_SE |
3537 SWAPPER_CTRL_TXD_W_FE |
3538 SWAPPER_CTRL_TXD_W_SE |
3539 SWAPPER_CTRL_TXF_R_FE |
3540 SWAPPER_CTRL_RXD_R_FE |
3541 SWAPPER_CTRL_RXD_R_SE |
3542 SWAPPER_CTRL_RXD_W_FE |
3543 SWAPPER_CTRL_RXD_W_SE |
3544 SWAPPER_CTRL_RXF_W_FE |
3545 SWAPPER_CTRL_XMSI_FE |
3546 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3547 if (sp->config.intr_type == INTA)
3548 val64 |= SWAPPER_CTRL_XMSI_SE;
3549 writeq(val64, &bar0->swapper_ctrl);
3550 #endif
3551 val64 = readq(&bar0->swapper_ctrl);
3552
3553 /*
3554 * Verifying if endian settings are accurate by reading a
3555 * feedback register.
3556 */
3557 val64 = readq(&bar0->pif_rd_swapper_fb);
3558 if (val64 != 0x0123456789ABCDEFULL) {
3559 /* Endian settings are incorrect, calls for another dekko. */
3560 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3561 dev->name);
3562 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3563 (unsigned long long) val64);
3564 return FAILURE;
3565 }
3566
3567 return SUCCESS;
3568 }
3569
3570 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3571 {
3572 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3573 u64 val64;
3574 int ret = 0, cnt = 0;
3575
3576 do {
3577 val64 = readq(&bar0->xmsi_access);
3578 if (!(val64 & BIT(15)))
3579 break;
3580 mdelay(1);
3581 cnt++;
3582 } while(cnt < 5);
3583 if (cnt == 5) {
3584 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3585 ret = 1;
3586 }
3587
3588 return ret;
3589 }
3590
3591 static void restore_xmsi_data(struct s2io_nic *nic)
3592 {
3593 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3594 u64 val64;
3595 int i;
3596
3597 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3598 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3599 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3600 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3601 writeq(val64, &bar0->xmsi_access);
3602 if (wait_for_msix_trans(nic, i)) {
3603 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3604 continue;
3605 }
3606 }
3607 }
3608
3609 static void store_xmsi_data(struct s2io_nic *nic)
3610 {
3611 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3612 u64 val64, addr, data;
3613 int i;
3614
3615 /* Store and display */
3616 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3617 val64 = (BIT(15) | vBIT(i, 26, 6));
3618 writeq(val64, &bar0->xmsi_access);
3619 if (wait_for_msix_trans(nic, i)) {
3620 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3621 continue;
3622 }
3623 addr = readq(&bar0->xmsi_address);
3624 data = readq(&bar0->xmsi_data);
3625 if (addr && data) {
3626 nic->msix_info[i].addr = addr;
3627 nic->msix_info[i].data = data;
3628 }
3629 }
3630 }
3631
3632 static int s2io_enable_msi_x(struct s2io_nic *nic)
3633 {
3634 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3635 u64 tx_mat, rx_mat;
3636 u16 msi_control; /* Temp variable */
3637 int ret, i, j, msix_indx = 1;
3638
3639 nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
3640 GFP_KERNEL);
3641 if (!nic->entries) {
3642 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3643 __FUNCTION__);
3644 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3645 return -ENOMEM;
3646 }
3647 nic->mac_control.stats_info->sw_stat.mem_allocated
3648 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3649
3650 nic->s2io_entries =
3651 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
3652 GFP_KERNEL);
3653 if (!nic->s2io_entries) {
3654 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3655 __FUNCTION__);
3656 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3657 kfree(nic->entries);
3658 nic->mac_control.stats_info->sw_stat.mem_freed
3659 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3660 return -ENOMEM;
3661 }
3662 nic->mac_control.stats_info->sw_stat.mem_allocated
3663 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3664
3665 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3666 nic->entries[i].entry = i;
3667 nic->s2io_entries[i].entry = i;
3668 nic->s2io_entries[i].arg = NULL;
3669 nic->s2io_entries[i].in_use = 0;
3670 }
3671
3672 tx_mat = readq(&bar0->tx_mat0_n[0]);
3673 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3674 tx_mat |= TX_MAT_SET(i, msix_indx);
3675 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3676 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3677 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3678 }
3679 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3680
3681 rx_mat = readq(&bar0->rx_mat);
3682 for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3683 rx_mat |= RX_MAT_SET(j, msix_indx);
3684 nic->s2io_entries[msix_indx].arg
3685 = &nic->mac_control.rings[j];
3686 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3687 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3688 }
3689 writeq(rx_mat, &bar0->rx_mat);
3690
3691 nic->avail_msix_vectors = 0;
3692 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3693 /* We fail init if error or we get less vectors than min required */
3694 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3695 nic->avail_msix_vectors = ret;
3696 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3697 }
3698 if (ret) {
3699 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3700 kfree(nic->entries);
3701 nic->mac_control.stats_info->sw_stat.mem_freed
3702 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3703 kfree(nic->s2io_entries);
3704 nic->mac_control.stats_info->sw_stat.mem_freed
3705 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3706 nic->entries = NULL;
3707 nic->s2io_entries = NULL;
3708 nic->avail_msix_vectors = 0;
3709 return -ENOMEM;
3710 }
3711 if (!nic->avail_msix_vectors)
3712 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3713
3714 /*
3715 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3716 * in the herc NIC. (Temp change, needs to be removed later)
3717 */
3718 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3719 msi_control |= 0x1; /* Enable MSI */
3720 pci_write_config_word(nic->pdev, 0x42, msi_control);
3721
3722 return 0;
3723 }
3724
3725 /* Handle software interrupt used during MSI(X) test */
3726 static irqreturn_t __devinit s2io_test_intr(int irq, void *dev_id)
3727 {
3728 struct s2io_nic *sp = dev_id;
3729
3730 sp->msi_detected = 1;
3731 wake_up(&sp->msi_wait);
3732
3733 return IRQ_HANDLED;
3734 }
3735
3736 /* Test interrupt path by forcing a a software IRQ */
3737 static int __devinit s2io_test_msi(struct s2io_nic *sp)
3738 {
3739 struct pci_dev *pdev = sp->pdev;
3740 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3741 int err;
3742 u64 val64, saved64;
3743
3744 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3745 sp->name, sp);
3746 if (err) {
3747 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3748 sp->dev->name, pci_name(pdev), pdev->irq);
3749 return err;
3750 }
3751
3752 init_waitqueue_head (&sp->msi_wait);
3753 sp->msi_detected = 0;
3754
3755 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3756 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3757 val64 |= SCHED_INT_CTRL_TIMER_EN;
3758 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3759 writeq(val64, &bar0->scheduled_int_ctrl);
3760
3761 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3762
3763 if (!sp->msi_detected) {
3764 /* MSI(X) test failed, go back to INTx mode */
3765 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated"
3766 "using MSI(X) during test\n", sp->dev->name,
3767 pci_name(pdev));
3768
3769 err = -EOPNOTSUPP;
3770 }
3771
3772 free_irq(sp->entries[1].vector, sp);
3773
3774 writeq(saved64, &bar0->scheduled_int_ctrl);
3775
3776 return err;
3777 }
3778 /* ********************************************************* *
3779 * Functions defined below concern the OS part of the driver *
3780 * ********************************************************* */
3781
3782 /**
3783 * s2io_open - open entry point of the driver
3784 * @dev : pointer to the device structure.
3785 * Description:
3786 * This function is the open entry point of the driver. It mainly calls a
3787 * function to allocate Rx buffers and inserts them into the buffer
3788 * descriptors and then enables the Rx part of the NIC.
3789 * Return value:
3790 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3791 * file on failure.
3792 */
3793
3794 static int s2io_open(struct net_device *dev)
3795 {
3796 struct s2io_nic *sp = dev->priv;
3797 int err = 0;
3798
3799 /*
3800 * Make sure you have link off by default every time
3801 * Nic is initialized
3802 */
3803 netif_carrier_off(dev);
3804 sp->last_link_state = 0;
3805
3806 napi_enable(&sp->napi);
3807
3808 if (sp->config.intr_type == MSI_X) {
3809 int ret = s2io_enable_msi_x(sp);
3810
3811 if (!ret) {
3812 u16 msi_control;
3813
3814 ret = s2io_test_msi(sp);
3815
3816 /* rollback MSI-X, will re-enable during add_isr() */
3817 kfree(sp->entries);
3818 sp->mac_control.stats_info->sw_stat.mem_freed +=
3819 (MAX_REQUESTED_MSI_X *
3820 sizeof(struct msix_entry));
3821 kfree(sp->s2io_entries);
3822 sp->mac_control.stats_info->sw_stat.mem_freed +=
3823 (MAX_REQUESTED_MSI_X *
3824 sizeof(struct s2io_msix_entry));
3825 sp->entries = NULL;
3826 sp->s2io_entries = NULL;
3827
3828 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3829 msi_control &= 0xFFFE; /* Disable MSI */
3830 pci_write_config_word(sp->pdev, 0x42, msi_control);
3831
3832 pci_disable_msix(sp->pdev);
3833
3834 }
3835 if (ret) {
3836
3837 DBG_PRINT(ERR_DBG,
3838 "%s: MSI-X requested but failed to enable\n",
3839 dev->name);
3840 sp->config.intr_type = INTA;
3841 }
3842 }
3843
3844 /* NAPI doesn't work well with MSI(X) */
3845 if (sp->config.intr_type != INTA) {
3846 if(sp->config.napi)
3847 sp->config.napi = 0;
3848 }
3849
3850 /* Initialize H/W and enable interrupts */
3851 err = s2io_card_up(sp);
3852 if (err) {
3853 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3854 dev->name);
3855 goto hw_init_failed;
3856 }
3857
3858 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3859 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3860 s2io_card_down(sp);
3861 err = -ENODEV;
3862 goto hw_init_failed;
3863 }
3864
3865 netif_start_queue(dev);
3866 return 0;
3867
3868 hw_init_failed:
3869 napi_disable(&sp->napi);
3870 if (sp->config.intr_type == MSI_X) {
3871 if (sp->entries) {
3872 kfree(sp->entries);
3873 sp->mac_control.stats_info->sw_stat.mem_freed
3874 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3875 }
3876 if (sp->s2io_entries) {
3877 kfree(sp->s2io_entries);
3878 sp->mac_control.stats_info->sw_stat.mem_freed
3879 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3880 }
3881 }
3882 return err;
3883 }
3884
3885 /**
3886 * s2io_close -close entry point of the driver
3887 * @dev : device pointer.
3888 * Description:
3889 * This is the stop entry point of the driver. It needs to undo exactly
3890 * whatever was done by the open entry point,thus it's usually referred to
3891 * as the close function.Among other things this function mainly stops the
3892 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3893 * Return value:
3894 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3895 * file on failure.
3896 */
3897
3898 static int s2io_close(struct net_device *dev)
3899 {
3900 struct s2io_nic *sp = dev->priv;
3901
3902 netif_stop_queue(dev);
3903 napi_disable(&sp->napi);
3904 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3905 s2io_card_down(sp);
3906
3907 return 0;
3908 }
3909
3910 /**
3911 * s2io_xmit - Tx entry point of te driver
3912 * @skb : the socket buffer containing the Tx data.
3913 * @dev : device pointer.
3914 * Description :
3915 * This function is the Tx entry point of the driver. S2IO NIC supports
3916 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3917 * NOTE: when device cant queue the pkt,just the trans_start variable will
3918 * not be upadted.
3919 * Return value:
3920 * 0 on success & 1 on failure.
3921 */
3922
3923 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3924 {
3925 struct s2io_nic *sp = dev->priv;
3926 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3927 register u64 val64;
3928 struct TxD *txdp;
3929 struct TxFIFO_element __iomem *tx_fifo;
3930 unsigned long flags;
3931 u16 vlan_tag = 0;
3932 int vlan_priority = 0;
3933 struct mac_info *mac_control;
3934 struct config_param *config;
3935 int offload_type;
3936 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
3937
3938 mac_control = &sp->mac_control;
3939 config = &sp->config;
3940
3941 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3942
3943 if (unlikely(skb->len <= 0)) {
3944 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3945 dev_kfree_skb_any(skb);
3946 return 0;
3947 }
3948
3949 spin_lock_irqsave(&sp->tx_lock, flags);
3950 if (!is_s2io_card_up(sp)) {
3951 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3952 dev->name);
3953 spin_unlock_irqrestore(&sp->tx_lock, flags);
3954 dev_kfree_skb(skb);
3955 return 0;
3956 }
3957
3958 queue = 0;
3959 /* Get Fifo number to Transmit based on vlan priority */
3960 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3961 vlan_tag = vlan_tx_tag_get(skb);
3962 vlan_priority = vlan_tag >> 13;
3963 queue = config->fifo_mapping[vlan_priority];
3964 }
3965
3966 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3967 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3968 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
3969 list_virt_addr;
3970
3971 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3972 /* Avoid "put" pointer going beyond "get" pointer */
3973 if (txdp->Host_Control ||
3974 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3975 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3976 netif_stop_queue(dev);
3977 dev_kfree_skb(skb);
3978 spin_unlock_irqrestore(&sp->tx_lock, flags);
3979 return 0;
3980 }
3981
3982 offload_type = s2io_offload_type(skb);
3983 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3984 txdp->Control_1 |= TXD_TCP_LSO_EN;
3985 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3986 }
3987 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3988 txdp->Control_2 |=
3989 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3990 TXD_TX_CKO_UDP_EN);
3991 }
3992 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3993 txdp->Control_1 |= TXD_LIST_OWN_XENA;
3994 txdp->Control_2 |= config->tx_intr_type;
3995
3996 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3997 txdp->Control_2 |= TXD_VLAN_ENABLE;
3998 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3999 }
4000
4001 frg_len = skb->len - skb->data_len;
4002 if (offload_type == SKB_GSO_UDP) {
4003 int ufo_size;
4004
4005 ufo_size = s2io_udp_mss(skb);
4006 ufo_size &= ~7;
4007 txdp->Control_1 |= TXD_UFO_EN;
4008 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4009 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4010 #ifdef __BIG_ENDIAN
4011 sp->ufo_in_band_v[put_off] =
4012 (u64)skb_shinfo(skb)->ip6_frag_id;
4013 #else
4014 sp->ufo_in_band_v[put_off] =
4015 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4016 #endif
4017 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4018 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4019 sp->ufo_in_band_v,
4020 sizeof(u64), PCI_DMA_TODEVICE);
4021 if((txdp->Buffer_Pointer == 0) ||
4022 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4023 goto pci_map_failed;
4024 txdp++;
4025 }
4026
4027 txdp->Buffer_Pointer = pci_map_single
4028 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4029 if((txdp->Buffer_Pointer == 0) ||
4030 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4031 goto pci_map_failed;
4032
4033 txdp->Host_Control = (unsigned long) skb;
4034 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4035 if (offload_type == SKB_GSO_UDP)
4036 txdp->Control_1 |= TXD_UFO_EN;
4037
4038 frg_cnt = skb_shinfo(skb)->nr_frags;
4039 /* For fragmented SKB. */
4040 for (i = 0; i < frg_cnt; i++) {
4041 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4042 /* A '0' length fragment will be ignored */
4043 if (!frag->size)
4044 continue;
4045 txdp++;
4046 txdp->Buffer_Pointer = (u64) pci_map_page
4047 (sp->pdev, frag->page, frag->page_offset,
4048 frag->size, PCI_DMA_TODEVICE);
4049 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4050 if (offload_type == SKB_GSO_UDP)
4051 txdp->Control_1 |= TXD_UFO_EN;
4052 }
4053 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4054
4055 if (offload_type == SKB_GSO_UDP)
4056 frg_cnt++; /* as Txd0 was used for inband header */
4057
4058 tx_fifo = mac_control->tx_FIFO_start[queue];
4059 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
4060 writeq(val64, &tx_fifo->TxDL_Pointer);
4061
4062 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4063 TX_FIFO_LAST_LIST);
4064 if (offload_type)
4065 val64 |= TX_FIFO_SPECIAL_FUNC;
4066
4067 writeq(val64, &tx_fifo->List_Control);
4068
4069 mmiowb();
4070
4071 put_off++;
4072 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4073 put_off = 0;
4074 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
4075
4076 /* Avoid "put" pointer going beyond "get" pointer */
4077 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4078 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4079 DBG_PRINT(TX_DBG,
4080 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4081 put_off, get_off);
4082 netif_stop_queue(dev);
4083 }
4084 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4085 dev->trans_start = jiffies;
4086 spin_unlock_irqrestore(&sp->tx_lock, flags);
4087
4088 return 0;
4089 pci_map_failed:
4090 stats->pci_map_fail_cnt++;
4091 netif_stop_queue(dev);
4092 stats->mem_freed += skb->truesize;
4093 dev_kfree_skb(skb);
4094 spin_unlock_irqrestore(&sp->tx_lock, flags);
4095 return 0;
4096 }
4097
4098 static void
4099 s2io_alarm_handle(unsigned long data)
4100 {
4101 struct s2io_nic *sp = (struct s2io_nic *)data;
4102 struct net_device *dev = sp->dev;
4103
4104 s2io_handle_errors(dev);
4105 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4106 }
4107
4108 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4109 {
4110 int rxb_size, level;
4111
4112 if (!sp->lro) {
4113 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4114 level = rx_buffer_level(sp, rxb_size, rng_n);
4115
4116 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4117 int ret;
4118 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4119 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4120 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4121 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4122 __FUNCTION__);
4123 clear_bit(0, (&sp->tasklet_status));
4124 return -1;
4125 }
4126 clear_bit(0, (&sp->tasklet_status));
4127 } else if (level == LOW)
4128 tasklet_schedule(&sp->task);
4129
4130 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4131 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4132 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4133 }
4134 return 0;
4135 }
4136
4137 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4138 {
4139 struct ring_info *ring = (struct ring_info *)dev_id;
4140 struct s2io_nic *sp = ring->nic;
4141
4142 if (!is_s2io_card_up(sp))
4143 return IRQ_HANDLED;
4144
4145 rx_intr_handler(ring);
4146 s2io_chk_rx_buffers(sp, ring->ring_no);
4147
4148 return IRQ_HANDLED;
4149 }
4150
4151 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4152 {
4153 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4154 struct s2io_nic *sp = fifo->nic;
4155
4156 if (!is_s2io_card_up(sp))
4157 return IRQ_HANDLED;
4158
4159 tx_intr_handler(fifo);
4160 return IRQ_HANDLED;
4161 }
4162 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4163 {
4164 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4165 u64 val64;
4166
4167 val64 = readq(&bar0->pic_int_status);
4168 if (val64 & PIC_INT_GPIO) {
4169 val64 = readq(&bar0->gpio_int_reg);
4170 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4171 (val64 & GPIO_INT_REG_LINK_UP)) {
4172 /*
4173 * This is unstable state so clear both up/down
4174 * interrupt and adapter to re-evaluate the link state.
4175 */
4176 val64 |= GPIO_INT_REG_LINK_DOWN;
4177 val64 |= GPIO_INT_REG_LINK_UP;
4178 writeq(val64, &bar0->gpio_int_reg);
4179 val64 = readq(&bar0->gpio_int_mask);
4180 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4181 GPIO_INT_MASK_LINK_DOWN);
4182 writeq(val64, &bar0->gpio_int_mask);
4183 }
4184 else if (val64 & GPIO_INT_REG_LINK_UP) {
4185 val64 = readq(&bar0->adapter_status);
4186 /* Enable Adapter */
4187 val64 = readq(&bar0->adapter_control);
4188 val64 |= ADAPTER_CNTL_EN;
4189 writeq(val64, &bar0->adapter_control);
4190 val64 |= ADAPTER_LED_ON;
4191 writeq(val64, &bar0->adapter_control);
4192 if (!sp->device_enabled_once)
4193 sp->device_enabled_once = 1;
4194
4195 s2io_link(sp, LINK_UP);
4196 /*
4197 * unmask link down interrupt and mask link-up
4198 * intr
4199 */
4200 val64 = readq(&bar0->gpio_int_mask);
4201 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4202 val64 |= GPIO_INT_MASK_LINK_UP;
4203 writeq(val64, &bar0->gpio_int_mask);
4204
4205 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4206 val64 = readq(&bar0->adapter_status);
4207 s2io_link(sp, LINK_DOWN);
4208 /* Link is down so unmaks link up interrupt */
4209 val64 = readq(&bar0->gpio_int_mask);
4210 val64 &= ~GPIO_INT_MASK_LINK_UP;
4211 val64 |= GPIO_INT_MASK_LINK_DOWN;
4212 writeq(val64, &bar0->gpio_int_mask);
4213
4214 /* turn off LED */
4215 val64 = readq(&bar0->adapter_control);
4216 val64 = val64 &(~ADAPTER_LED_ON);
4217 writeq(val64, &bar0->adapter_control);
4218 }
4219 }
4220 val64 = readq(&bar0->gpio_int_mask);
4221 }
4222
4223 /**
4224 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4225 * @value: alarm bits
4226 * @addr: address value
4227 * @cnt: counter variable
4228 * Description: Check for alarm and increment the counter
4229 * Return Value:
4230 * 1 - if alarm bit set
4231 * 0 - if alarm bit is not set
4232 */
4233 static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4234 unsigned long long *cnt)
4235 {
4236 u64 val64;
4237 val64 = readq(addr);
4238 if ( val64 & value ) {
4239 writeq(val64, addr);
4240 (*cnt)++;
4241 return 1;
4242 }
4243 return 0;
4244
4245 }
4246
4247 /**
4248 * s2io_handle_errors - Xframe error indication handler
4249 * @nic: device private variable
4250 * Description: Handle alarms such as loss of link, single or
4251 * double ECC errors, critical and serious errors.
4252 * Return Value:
4253 * NONE
4254 */
4255 static void s2io_handle_errors(void * dev_id)
4256 {
4257 struct net_device *dev = (struct net_device *) dev_id;
4258 struct s2io_nic *sp = dev->priv;
4259 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4260 u64 temp64 = 0,val64=0;
4261 int i = 0;
4262
4263 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4264 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4265
4266 if (!is_s2io_card_up(sp))
4267 return;
4268
4269 if (pci_channel_offline(sp->pdev))
4270 return;
4271
4272 memset(&sw_stat->ring_full_cnt, 0,
4273 sizeof(sw_stat->ring_full_cnt));
4274
4275 /* Handling the XPAK counters update */
4276 if(stats->xpak_timer_count < 72000) {
4277 /* waiting for an hour */
4278 stats->xpak_timer_count++;
4279 } else {
4280 s2io_updt_xpak_counter(dev);
4281 /* reset the count to zero */
4282 stats->xpak_timer_count = 0;
4283 }
4284
4285 /* Handling link status change error Intr */
4286 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4287 val64 = readq(&bar0->mac_rmac_err_reg);
4288 writeq(val64, &bar0->mac_rmac_err_reg);
4289 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4290 schedule_work(&sp->set_link_task);
4291 }
4292
4293 /* In case of a serious error, the device will be Reset. */
4294 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4295 &sw_stat->serious_err_cnt))
4296 goto reset;
4297
4298 /* Check for data parity error */
4299 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4300 &sw_stat->parity_err_cnt))
4301 goto reset;
4302
4303 /* Check for ring full counter */
4304 if (sp->device_type == XFRAME_II_DEVICE) {
4305 val64 = readq(&bar0->ring_bump_counter1);
4306 for (i=0; i<4; i++) {
4307 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4308 temp64 >>= 64 - ((i+1)*16);
4309 sw_stat->ring_full_cnt[i] += temp64;
4310 }
4311
4312 val64 = readq(&bar0->ring_bump_counter2);
4313 for (i=0; i<4; i++) {
4314 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4315 temp64 >>= 64 - ((i+1)*16);
4316 sw_stat->ring_full_cnt[i+4] += temp64;
4317 }
4318 }
4319
4320 val64 = readq(&bar0->txdma_int_status);
4321 /*check for pfc_err*/
4322 if (val64 & TXDMA_PFC_INT) {
4323 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4324 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4325 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4326 &sw_stat->pfc_err_cnt))
4327 goto reset;
4328 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4329 &sw_stat->pfc_err_cnt);
4330 }
4331
4332 /*check for tda_err*/
4333 if (val64 & TXDMA_TDA_INT) {
4334 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4335 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4336 &sw_stat->tda_err_cnt))
4337 goto reset;
4338 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4339 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4340 }
4341 /*check for pcc_err*/
4342 if (val64 & TXDMA_PCC_INT) {
4343 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4344 | PCC_N_SERR | PCC_6_COF_OV_ERR
4345 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4346 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4347 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4348 &sw_stat->pcc_err_cnt))
4349 goto reset;
4350 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4351 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4352 }
4353
4354 /*check for tti_err*/
4355 if (val64 & TXDMA_TTI_INT) {
4356 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4357 &sw_stat->tti_err_cnt))
4358 goto reset;
4359 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4360 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4361 }
4362
4363 /*check for lso_err*/
4364 if (val64 & TXDMA_LSO_INT) {
4365 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4366 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4367 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4368 goto reset;
4369 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4370 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4371 }
4372
4373 /*check for tpa_err*/
4374 if (val64 & TXDMA_TPA_INT) {
4375 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4376 &sw_stat->tpa_err_cnt))
4377 goto reset;
4378 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4379 &sw_stat->tpa_err_cnt);
4380 }
4381
4382 /*check for sm_err*/
4383 if (val64 & TXDMA_SM_INT) {
4384 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4385 &sw_stat->sm_err_cnt))
4386 goto reset;
4387 }
4388
4389 val64 = readq(&bar0->mac_int_status);
4390 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4391 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4392 &bar0->mac_tmac_err_reg,
4393 &sw_stat->mac_tmac_err_cnt))
4394 goto reset;
4395 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4396 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4397 &bar0->mac_tmac_err_reg,
4398 &sw_stat->mac_tmac_err_cnt);
4399 }
4400
4401 val64 = readq(&bar0->xgxs_int_status);
4402 if (val64 & XGXS_INT_STATUS_TXGXS) {
4403 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4404 &bar0->xgxs_txgxs_err_reg,
4405 &sw_stat->xgxs_txgxs_err_cnt))
4406 goto reset;
4407 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4408 &bar0->xgxs_txgxs_err_reg,
4409 &sw_stat->xgxs_txgxs_err_cnt);
4410 }
4411
4412 val64 = readq(&bar0->rxdma_int_status);
4413 if (val64 & RXDMA_INT_RC_INT_M) {
4414 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4415 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4416 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4417 goto reset;
4418 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4419 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4420 &sw_stat->rc_err_cnt);
4421 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4422 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4423 &sw_stat->prc_pcix_err_cnt))
4424 goto reset;
4425 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4426 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4427 &sw_stat->prc_pcix_err_cnt);
4428 }
4429
4430 if (val64 & RXDMA_INT_RPA_INT_M) {
4431 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4432 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4433 goto reset;
4434 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4435 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4436 }
4437
4438 if (val64 & RXDMA_INT_RDA_INT_M) {
4439 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4440 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4441 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4442 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4443 goto reset;
4444 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4445 | RDA_MISC_ERR | RDA_PCIX_ERR,
4446 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4447 }
4448
4449 if (val64 & RXDMA_INT_RTI_INT_M) {
4450 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4451 &sw_stat->rti_err_cnt))
4452 goto reset;
4453 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4454 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4455 }
4456
4457 val64 = readq(&bar0->mac_int_status);
4458 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4459 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4460 &bar0->mac_rmac_err_reg,
4461 &sw_stat->mac_rmac_err_cnt))
4462 goto reset;
4463 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4464 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4465 &sw_stat->mac_rmac_err_cnt);
4466 }
4467
4468 val64 = readq(&bar0->xgxs_int_status);
4469 if (val64 & XGXS_INT_STATUS_RXGXS) {
4470 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4471 &bar0->xgxs_rxgxs_err_reg,
4472 &sw_stat->xgxs_rxgxs_err_cnt))
4473 goto reset;
4474 }
4475
4476 val64 = readq(&bar0->mc_int_status);
4477 if(val64 & MC_INT_STATUS_MC_INT) {
4478 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4479 &sw_stat->mc_err_cnt))
4480 goto reset;
4481
4482 /* Handling Ecc errors */
4483 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4484 writeq(val64, &bar0->mc_err_reg);
4485 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4486 sw_stat->double_ecc_errs++;
4487 if (sp->device_type != XFRAME_II_DEVICE) {
4488 /*
4489 * Reset XframeI only if critical error
4490 */
4491 if (val64 &
4492 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4493 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4494 goto reset;
4495 }
4496 } else
4497 sw_stat->single_ecc_errs++;
4498 }
4499 }
4500 return;
4501
4502 reset:
4503 netif_stop_queue(dev);
4504 schedule_work(&sp->rst_timer_task);
4505 sw_stat->soft_reset_cnt++;
4506 return;
4507 }
4508
4509 /**
4510 * s2io_isr - ISR handler of the device .
4511 * @irq: the irq of the device.
4512 * @dev_id: a void pointer to the dev structure of the NIC.
4513 * Description: This function is the ISR handler of the device. It
4514 * identifies the reason for the interrupt and calls the relevant
4515 * service routines. As a contongency measure, this ISR allocates the
4516 * recv buffers, if their numbers are below the panic value which is
4517 * presently set to 25% of the original number of rcv buffers allocated.
4518 * Return value:
4519 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4520 * IRQ_NONE: will be returned if interrupt is not from our device
4521 */
4522 static irqreturn_t s2io_isr(int irq, void *dev_id)
4523 {
4524 struct net_device *dev = (struct net_device *) dev_id;
4525 struct s2io_nic *sp = dev->priv;
4526 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4527 int i;
4528 u64 reason = 0;
4529 struct mac_info *mac_control;
4530 struct config_param *config;
4531
4532 /* Pretend we handled any irq's from a disconnected card */
4533 if (pci_channel_offline(sp->pdev))
4534 return IRQ_NONE;
4535
4536 if (!is_s2io_card_up(sp))
4537 return IRQ_NONE;
4538
4539 mac_control = &sp->mac_control;
4540 config = &sp->config;
4541
4542 /*
4543 * Identify the cause for interrupt and call the appropriate
4544 * interrupt handler. Causes for the interrupt could be;
4545 * 1. Rx of packet.
4546 * 2. Tx complete.
4547 * 3. Link down.
4548 */
4549 reason = readq(&bar0->general_int_status);
4550
4551 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4552 /* Nothing much can be done. Get out */
4553 return IRQ_HANDLED;
4554 }
4555
4556 if (reason & (GEN_INTR_RXTRAFFIC |
4557 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4558 {
4559 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4560
4561 if (config->napi) {
4562 if (reason & GEN_INTR_RXTRAFFIC) {
4563 if (likely(netif_rx_schedule_prep(dev,
4564 &sp->napi))) {
4565 __netif_rx_schedule(dev, &sp->napi);
4566 writeq(S2IO_MINUS_ONE,
4567 &bar0->rx_traffic_mask);
4568 } else
4569 writeq(S2IO_MINUS_ONE,
4570 &bar0->rx_traffic_int);
4571 }
4572 } else {
4573 /*
4574 * rx_traffic_int reg is an R1 register, writing all 1's
4575 * will ensure that the actual interrupt causing bit
4576 * get's cleared and hence a read can be avoided.
4577 */
4578 if (reason & GEN_INTR_RXTRAFFIC)
4579 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4580
4581 for (i = 0; i < config->rx_ring_num; i++)
4582 rx_intr_handler(&mac_control->rings[i]);
4583 }
4584
4585 /*
4586 * tx_traffic_int reg is an R1 register, writing all 1's
4587 * will ensure that the actual interrupt causing bit get's
4588 * cleared and hence a read can be avoided.
4589 */
4590 if (reason & GEN_INTR_TXTRAFFIC)
4591 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4592
4593 for (i = 0; i < config->tx_fifo_num; i++)
4594 tx_intr_handler(&mac_control->fifos[i]);
4595
4596 if (reason & GEN_INTR_TXPIC)
4597 s2io_txpic_intr_handle(sp);
4598
4599 /*
4600 * Reallocate the buffers from the interrupt handler itself.
4601 */
4602 if (!config->napi) {
4603 for (i = 0; i < config->rx_ring_num; i++)
4604 s2io_chk_rx_buffers(sp, i);
4605 }
4606 writeq(sp->general_int_mask, &bar0->general_int_mask);
4607 readl(&bar0->general_int_status);
4608
4609 return IRQ_HANDLED;
4610
4611 }
4612 else if (!reason) {
4613 /* The interrupt was not raised by us */
4614 return IRQ_NONE;
4615 }
4616
4617 return IRQ_HANDLED;
4618 }
4619
4620 /**
4621 * s2io_updt_stats -
4622 */
4623 static void s2io_updt_stats(struct s2io_nic *sp)
4624 {
4625 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4626 u64 val64;
4627 int cnt = 0;
4628
4629 if (is_s2io_card_up(sp)) {
4630 /* Apprx 30us on a 133 MHz bus */
4631 val64 = SET_UPDT_CLICKS(10) |
4632 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4633 writeq(val64, &bar0->stat_cfg);
4634 do {
4635 udelay(100);
4636 val64 = readq(&bar0->stat_cfg);
4637 if (!(val64 & BIT(0)))
4638 break;
4639 cnt++;
4640 if (cnt == 5)
4641 break; /* Updt failed */
4642 } while(1);
4643 }
4644 }
4645
4646 /**
4647 * s2io_get_stats - Updates the device statistics structure.
4648 * @dev : pointer to the device structure.
4649 * Description:
4650 * This function updates the device statistics structure in the s2io_nic
4651 * structure and returns a pointer to the same.
4652 * Return value:
4653 * pointer to the updated net_device_stats structure.
4654 */
4655
4656 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4657 {
4658 struct s2io_nic *sp = dev->priv;
4659 struct mac_info *mac_control;
4660 struct config_param *config;
4661
4662
4663 mac_control = &sp->mac_control;
4664 config = &sp->config;
4665
4666 /* Configure Stats for immediate updt */
4667 s2io_updt_stats(sp);
4668
4669 sp->stats.tx_packets =
4670 le32_to_cpu(mac_control->stats_info->tmac_frms);
4671 sp->stats.tx_errors =
4672 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4673 sp->stats.rx_errors =
4674 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4675 sp->stats.multicast =
4676 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4677 sp->stats.rx_length_errors =
4678 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4679
4680 return (&sp->stats);
4681 }
4682
4683 /**
4684 * s2io_set_multicast - entry point for multicast address enable/disable.
4685 * @dev : pointer to the device structure
4686 * Description:
4687 * This function is a driver entry point which gets called by the kernel
4688 * whenever multicast addresses must be enabled/disabled. This also gets
4689 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4690 * determine, if multicast address must be enabled or if promiscuous mode
4691 * is to be disabled etc.
4692 * Return value:
4693 * void.
4694 */
4695
4696 static void s2io_set_multicast(struct net_device *dev)
4697 {
4698 int i, j, prev_cnt;
4699 struct dev_mc_list *mclist;
4700 struct s2io_nic *sp = dev->priv;
4701 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4702 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4703 0xfeffffffffffULL;
4704 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4705 void __iomem *add;
4706
4707 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4708 /* Enable all Multicast addresses */
4709 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4710 &bar0->rmac_addr_data0_mem);
4711 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4712 &bar0->rmac_addr_data1_mem);
4713 val64 = RMAC_ADDR_CMD_MEM_WE |
4714 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4715 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4716 writeq(val64, &bar0->rmac_addr_cmd_mem);
4717 /* Wait till command completes */
4718 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4719 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4720 S2IO_BIT_RESET);
4721
4722 sp->m_cast_flg = 1;
4723 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4724 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4725 /* Disable all Multicast addresses */
4726 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4727 &bar0->rmac_addr_data0_mem);
4728 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4729 &bar0->rmac_addr_data1_mem);
4730 val64 = RMAC_ADDR_CMD_MEM_WE |
4731 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4732 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4733 writeq(val64, &bar0->rmac_addr_cmd_mem);
4734 /* Wait till command completes */
4735 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4736 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4737 S2IO_BIT_RESET);
4738
4739 sp->m_cast_flg = 0;
4740 sp->all_multi_pos = 0;
4741 }
4742
4743 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4744 /* Put the NIC into promiscuous mode */
4745 add = &bar0->mac_cfg;
4746 val64 = readq(&bar0->mac_cfg);
4747 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4748
4749 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4750 writel((u32) val64, add);
4751 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4752 writel((u32) (val64 >> 32), (add + 4));
4753
4754 if (vlan_tag_strip != 1) {
4755 val64 = readq(&bar0->rx_pa_cfg);
4756 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4757 writeq(val64, &bar0->rx_pa_cfg);
4758 vlan_strip_flag = 0;
4759 }
4760
4761 val64 = readq(&bar0->mac_cfg);
4762 sp->promisc_flg = 1;
4763 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4764 dev->name);
4765 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4766 /* Remove the NIC from promiscuous mode */
4767 add = &bar0->mac_cfg;
4768 val64 = readq(&bar0->mac_cfg);
4769 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4770
4771 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4772 writel((u32) val64, add);
4773 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4774 writel((u32) (val64 >> 32), (add + 4));
4775
4776 if (vlan_tag_strip != 0) {
4777 val64 = readq(&bar0->rx_pa_cfg);
4778 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4779 writeq(val64, &bar0->rx_pa_cfg);
4780 vlan_strip_flag = 1;
4781 }
4782
4783 val64 = readq(&bar0->mac_cfg);
4784 sp->promisc_flg = 0;
4785 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4786 dev->name);
4787 }
4788
4789 /* Update individual M_CAST address list */
4790 if ((!sp->m_cast_flg) && dev->mc_count) {
4791 if (dev->mc_count >
4792 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4793 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4794 dev->name);
4795 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4796 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4797 return;
4798 }
4799
4800 prev_cnt = sp->mc_addr_count;
4801 sp->mc_addr_count = dev->mc_count;
4802
4803 /* Clear out the previous list of Mc in the H/W. */
4804 for (i = 0; i < prev_cnt; i++) {
4805 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4806 &bar0->rmac_addr_data0_mem);
4807 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4808 &bar0->rmac_addr_data1_mem);
4809 val64 = RMAC_ADDR_CMD_MEM_WE |
4810 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4811 RMAC_ADDR_CMD_MEM_OFFSET
4812 (MAC_MC_ADDR_START_OFFSET + i);
4813 writeq(val64, &bar0->rmac_addr_cmd_mem);
4814
4815 /* Wait for command completes */
4816 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4817 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4818 S2IO_BIT_RESET)) {
4819 DBG_PRINT(ERR_DBG, "%s: Adding ",
4820 dev->name);
4821 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4822 return;
4823 }
4824 }
4825
4826 /* Create the new Rx filter list and update the same in H/W. */
4827 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4828 i++, mclist = mclist->next) {
4829 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4830 ETH_ALEN);
4831 mac_addr = 0;
4832 for (j = 0; j < ETH_ALEN; j++) {
4833 mac_addr |= mclist->dmi_addr[j];
4834 mac_addr <<= 8;
4835 }
4836 mac_addr >>= 8;
4837 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4838 &bar0->rmac_addr_data0_mem);
4839 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4840 &bar0->rmac_addr_data1_mem);
4841 val64 = RMAC_ADDR_CMD_MEM_WE |
4842 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4843 RMAC_ADDR_CMD_MEM_OFFSET
4844 (i + MAC_MC_ADDR_START_OFFSET);
4845 writeq(val64, &bar0->rmac_addr_cmd_mem);
4846
4847 /* Wait for command completes */
4848 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4849 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4850 S2IO_BIT_RESET)) {
4851 DBG_PRINT(ERR_DBG, "%s: Adding ",
4852 dev->name);
4853 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4854 return;
4855 }
4856 }
4857 }
4858 }
4859
4860 /* add unicast MAC address to CAM */
4861 static int do_s2io_add_unicast(struct s2io_nic *sp, u64 addr, int off)
4862 {
4863 u64 val64;
4864 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4865
4866 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
4867 &bar0->rmac_addr_data0_mem);
4868
4869 val64 =
4870 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4871 RMAC_ADDR_CMD_MEM_OFFSET(off);
4872 writeq(val64, &bar0->rmac_addr_cmd_mem);
4873
4874 /* Wait till command completes */
4875 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4876 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4877 S2IO_BIT_RESET)) {
4878 DBG_PRINT(INFO_DBG, "add_mac_addr failed\n");
4879 return FAILURE;
4880 }
4881 return SUCCESS;
4882 }
4883
4884 /**
4885 * s2io_set_mac_addr driver entry point
4886 */
4887 static int s2io_set_mac_addr(struct net_device *dev, void *p)
4888 {
4889 struct sockaddr *addr = p;
4890
4891 if (!is_valid_ether_addr(addr->sa_data))
4892 return -EINVAL;
4893
4894 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4895
4896 /* store the MAC address in CAM */
4897 return (do_s2io_prog_unicast(dev, dev->dev_addr));
4898 }
4899
4900 /**
4901 * do_s2io_prog_unicast - Programs the Xframe mac address
4902 * @dev : pointer to the device structure.
4903 * @addr: a uchar pointer to the new mac address which is to be set.
4904 * Description : This procedure will program the Xframe to receive
4905 * frames with new Mac Address
4906 * Return value: SUCCESS on success and an appropriate (-)ve integer
4907 * as defined in errno.h file on failure.
4908 */
4909 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
4910 {
4911 struct s2io_nic *sp = dev->priv;
4912 register u64 mac_addr = 0, perm_addr = 0;
4913 int i;
4914
4915 /*
4916 * Set the new MAC address as the new unicast filter and reflect this
4917 * change on the device address registered with the OS. It will be
4918 * at offset 0.
4919 */
4920 for (i = 0; i < ETH_ALEN; i++) {
4921 mac_addr <<= 8;
4922 mac_addr |= addr[i];
4923 perm_addr <<= 8;
4924 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
4925 }
4926
4927 /* check if the dev_addr is different than perm_addr */
4928 if (mac_addr == perm_addr)
4929 return SUCCESS;
4930
4931 /* Update the internal structure with this new mac address */
4932 do_s2io_copy_mac_addr(sp, 0, mac_addr);
4933 return (do_s2io_add_unicast(sp, mac_addr, 0));
4934 }
4935
4936 /**
4937 * s2io_ethtool_sset - Sets different link parameters.
4938 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4939 * @info: pointer to the structure with parameters given by ethtool to set
4940 * link information.
4941 * Description:
4942 * The function sets different link parameters provided by the user onto
4943 * the NIC.
4944 * Return value:
4945 * 0 on success.
4946 */
4947
4948 static int s2io_ethtool_sset(struct net_device *dev,
4949 struct ethtool_cmd *info)
4950 {
4951 struct s2io_nic *sp = dev->priv;
4952 if ((info->autoneg == AUTONEG_ENABLE) ||
4953 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4954 return -EINVAL;
4955 else {
4956 s2io_close(sp->dev);
4957 s2io_open(sp->dev);
4958 }
4959
4960 return 0;
4961 }
4962
4963 /**
4964 * s2io_ethtol_gset - Return link specific information.
4965 * @sp : private member of the device structure, pointer to the
4966 * s2io_nic structure.
4967 * @info : pointer to the structure with parameters given by ethtool
4968 * to return link information.
4969 * Description:
4970 * Returns link specific information like speed, duplex etc.. to ethtool.
4971 * Return value :
4972 * return 0 on success.
4973 */
4974
4975 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4976 {
4977 struct s2io_nic *sp = dev->priv;
4978 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4979 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4980 info->port = PORT_FIBRE;
4981
4982 /* info->transceiver */
4983 info->transceiver = XCVR_EXTERNAL;
4984
4985 if (netif_carrier_ok(sp->dev)) {
4986 info->speed = 10000;
4987 info->duplex = DUPLEX_FULL;
4988 } else {
4989 info->speed = -1;
4990 info->duplex = -1;
4991 }
4992
4993 info->autoneg = AUTONEG_DISABLE;
4994 return 0;
4995 }
4996
4997 /**
4998 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4999 * @sp : private member of the device structure, which is a pointer to the
5000 * s2io_nic structure.
5001 * @info : pointer to the structure with parameters given by ethtool to
5002 * return driver information.
5003 * Description:
5004 * Returns driver specefic information like name, version etc.. to ethtool.
5005 * Return value:
5006 * void
5007 */
5008
5009 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5010 struct ethtool_drvinfo *info)
5011 {
5012 struct s2io_nic *sp = dev->priv;
5013
5014 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5015 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5016 strncpy(info->fw_version, "", sizeof(info->fw_version));
5017 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5018 info->regdump_len = XENA_REG_SPACE;
5019 info->eedump_len = XENA_EEPROM_SPACE;
5020 }
5021
5022 /**
5023 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5024 * @sp: private member of the device structure, which is a pointer to the
5025 * s2io_nic structure.
5026 * @regs : pointer to the structure with parameters given by ethtool for
5027 * dumping the registers.
5028 * @reg_space: The input argumnet into which all the registers are dumped.
5029 * Description:
5030 * Dumps the entire register space of xFrame NIC into the user given
5031 * buffer area.
5032 * Return value :
5033 * void .
5034 */
5035
5036 static void s2io_ethtool_gregs(struct net_device *dev,
5037 struct ethtool_regs *regs, void *space)
5038 {
5039 int i;
5040 u64 reg;
5041 u8 *reg_space = (u8 *) space;
5042 struct s2io_nic *sp = dev->priv;
5043
5044 regs->len = XENA_REG_SPACE;
5045 regs->version = sp->pdev->subsystem_device;
5046
5047 for (i = 0; i < regs->len; i += 8) {
5048 reg = readq(sp->bar0 + i);
5049 memcpy((reg_space + i), &reg, 8);
5050 }
5051 }
5052
5053 /**
5054 * s2io_phy_id - timer function that alternates adapter LED.
5055 * @data : address of the private member of the device structure, which
5056 * is a pointer to the s2io_nic structure, provided as an u32.
5057 * Description: This is actually the timer function that alternates the
5058 * adapter LED bit of the adapter control bit to set/reset every time on
5059 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5060 * once every second.
5061 */
5062 static void s2io_phy_id(unsigned long data)
5063 {
5064 struct s2io_nic *sp = (struct s2io_nic *) data;
5065 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5066 u64 val64 = 0;
5067 u16 subid;
5068
5069 subid = sp->pdev->subsystem_device;
5070 if ((sp->device_type == XFRAME_II_DEVICE) ||
5071 ((subid & 0xFF) >= 0x07)) {
5072 val64 = readq(&bar0->gpio_control);
5073 val64 ^= GPIO_CTRL_GPIO_0;
5074 writeq(val64, &bar0->gpio_control);
5075 } else {
5076 val64 = readq(&bar0->adapter_control);
5077 val64 ^= ADAPTER_LED_ON;
5078 writeq(val64, &bar0->adapter_control);
5079 }
5080
5081 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5082 }
5083
5084 /**
5085 * s2io_ethtool_idnic - To physically identify the nic on the system.
5086 * @sp : private member of the device structure, which is a pointer to the
5087 * s2io_nic structure.
5088 * @id : pointer to the structure with identification parameters given by
5089 * ethtool.
5090 * Description: Used to physically identify the NIC on the system.
5091 * The Link LED will blink for a time specified by the user for
5092 * identification.
5093 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5094 * identification is possible only if it's link is up.
5095 * Return value:
5096 * int , returns 0 on success
5097 */
5098
5099 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5100 {
5101 u64 val64 = 0, last_gpio_ctrl_val;
5102 struct s2io_nic *sp = dev->priv;
5103 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5104 u16 subid;
5105
5106 subid = sp->pdev->subsystem_device;
5107 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5108 if ((sp->device_type == XFRAME_I_DEVICE) &&
5109 ((subid & 0xFF) < 0x07)) {
5110 val64 = readq(&bar0->adapter_control);
5111 if (!(val64 & ADAPTER_CNTL_EN)) {
5112 printk(KERN_ERR
5113 "Adapter Link down, cannot blink LED\n");
5114 return -EFAULT;
5115 }
5116 }
5117 if (sp->id_timer.function == NULL) {
5118 init_timer(&sp->id_timer);
5119 sp->id_timer.function = s2io_phy_id;
5120 sp->id_timer.data = (unsigned long) sp;
5121 }
5122 mod_timer(&sp->id_timer, jiffies);
5123 if (data)
5124 msleep_interruptible(data * HZ);
5125 else
5126 msleep_interruptible(MAX_FLICKER_TIME);
5127 del_timer_sync(&sp->id_timer);
5128
5129 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5130 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5131 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5132 }
5133
5134 return 0;
5135 }
5136
5137 static void s2io_ethtool_gringparam(struct net_device *dev,
5138 struct ethtool_ringparam *ering)
5139 {
5140 struct s2io_nic *sp = dev->priv;
5141 int i,tx_desc_count=0,rx_desc_count=0;
5142
5143 if (sp->rxd_mode == RXD_MODE_1)
5144 ering->rx_max_pending = MAX_RX_DESC_1;
5145 else if (sp->rxd_mode == RXD_MODE_3B)
5146 ering->rx_max_pending = MAX_RX_DESC_2;
5147
5148 ering->tx_max_pending = MAX_TX_DESC;
5149 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5150 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5151
5152 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5153 ering->tx_pending = tx_desc_count;
5154 rx_desc_count = 0;
5155 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5156 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5157
5158 ering->rx_pending = rx_desc_count;
5159
5160 ering->rx_mini_max_pending = 0;
5161 ering->rx_mini_pending = 0;
5162 if(sp->rxd_mode == RXD_MODE_1)
5163 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5164 else if (sp->rxd_mode == RXD_MODE_3B)
5165 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5166 ering->rx_jumbo_pending = rx_desc_count;
5167 }
5168
5169 /**
5170 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5171 * @sp : private member of the device structure, which is a pointer to the
5172 * s2io_nic structure.
5173 * @ep : pointer to the structure with pause parameters given by ethtool.
5174 * Description:
5175 * Returns the Pause frame generation and reception capability of the NIC.
5176 * Return value:
5177 * void
5178 */
5179 static void s2io_ethtool_getpause_data(struct net_device *dev,
5180 struct ethtool_pauseparam *ep)
5181 {
5182 u64 val64;
5183 struct s2io_nic *sp = dev->priv;
5184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5185
5186 val64 = readq(&bar0->rmac_pause_cfg);
5187 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5188 ep->tx_pause = TRUE;
5189 if (val64 & RMAC_PAUSE_RX_ENABLE)
5190 ep->rx_pause = TRUE;
5191 ep->autoneg = FALSE;
5192 }
5193
5194 /**
5195 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5196 * @sp : private member of the device structure, which is a pointer to the
5197 * s2io_nic structure.
5198 * @ep : pointer to the structure with pause parameters given by ethtool.
5199 * Description:
5200 * It can be used to set or reset Pause frame generation or reception
5201 * support of the NIC.
5202 * Return value:
5203 * int, returns 0 on Success
5204 */
5205
5206 static int s2io_ethtool_setpause_data(struct net_device *dev,
5207 struct ethtool_pauseparam *ep)
5208 {
5209 u64 val64;
5210 struct s2io_nic *sp = dev->priv;
5211 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5212
5213 val64 = readq(&bar0->rmac_pause_cfg);
5214 if (ep->tx_pause)
5215 val64 |= RMAC_PAUSE_GEN_ENABLE;
5216 else
5217 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5218 if (ep->rx_pause)
5219 val64 |= RMAC_PAUSE_RX_ENABLE;
5220 else
5221 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5222 writeq(val64, &bar0->rmac_pause_cfg);
5223 return 0;
5224 }
5225
5226 /**
5227 * read_eeprom - reads 4 bytes of data from user given offset.
5228 * @sp : private member of the device structure, which is a pointer to the
5229 * s2io_nic structure.
5230 * @off : offset at which the data must be written
5231 * @data : Its an output parameter where the data read at the given
5232 * offset is stored.
5233 * Description:
5234 * Will read 4 bytes of data from the user given offset and return the
5235 * read data.
5236 * NOTE: Will allow to read only part of the EEPROM visible through the
5237 * I2C bus.
5238 * Return value:
5239 * -1 on failure and 0 on success.
5240 */
5241
5242 #define S2IO_DEV_ID 5
5243 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5244 {
5245 int ret = -1;
5246 u32 exit_cnt = 0;
5247 u64 val64;
5248 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5249
5250 if (sp->device_type == XFRAME_I_DEVICE) {
5251 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5252 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5253 I2C_CONTROL_CNTL_START;
5254 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5255
5256 while (exit_cnt < 5) {
5257 val64 = readq(&bar0->i2c_control);
5258 if (I2C_CONTROL_CNTL_END(val64)) {
5259 *data = I2C_CONTROL_GET_DATA(val64);
5260 ret = 0;
5261 break;
5262 }
5263 msleep(50);
5264 exit_cnt++;
5265 }
5266 }
5267
5268 if (sp->device_type == XFRAME_II_DEVICE) {
5269 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5270 SPI_CONTROL_BYTECNT(0x3) |
5271 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5272 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5273 val64 |= SPI_CONTROL_REQ;
5274 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5275 while (exit_cnt < 5) {
5276 val64 = readq(&bar0->spi_control);
5277 if (val64 & SPI_CONTROL_NACK) {
5278 ret = 1;
5279 break;
5280 } else if (val64 & SPI_CONTROL_DONE) {
5281 *data = readq(&bar0->spi_data);
5282 *data &= 0xffffff;
5283 ret = 0;
5284 break;
5285 }
5286 msleep(50);
5287 exit_cnt++;
5288 }
5289 }
5290 return ret;
5291 }
5292
5293 /**
5294 * write_eeprom - actually writes the relevant part of the data value.
5295 * @sp : private member of the device structure, which is a pointer to the
5296 * s2io_nic structure.
5297 * @off : offset at which the data must be written
5298 * @data : The data that is to be written
5299 * @cnt : Number of bytes of the data that are actually to be written into
5300 * the Eeprom. (max of 3)
5301 * Description:
5302 * Actually writes the relevant part of the data value into the Eeprom
5303 * through the I2C bus.
5304 * Return value:
5305 * 0 on success, -1 on failure.
5306 */
5307
5308 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5309 {
5310 int exit_cnt = 0, ret = -1;
5311 u64 val64;
5312 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5313
5314 if (sp->device_type == XFRAME_I_DEVICE) {
5315 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5316 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5317 I2C_CONTROL_CNTL_START;
5318 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5319
5320 while (exit_cnt < 5) {
5321 val64 = readq(&bar0->i2c_control);
5322 if (I2C_CONTROL_CNTL_END(val64)) {
5323 if (!(val64 & I2C_CONTROL_NACK))
5324 ret = 0;
5325 break;
5326 }
5327 msleep(50);
5328 exit_cnt++;
5329 }
5330 }
5331
5332 if (sp->device_type == XFRAME_II_DEVICE) {
5333 int write_cnt = (cnt == 8) ? 0 : cnt;
5334 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5335
5336 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5337 SPI_CONTROL_BYTECNT(write_cnt) |
5338 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5339 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5340 val64 |= SPI_CONTROL_REQ;
5341 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5342 while (exit_cnt < 5) {
5343 val64 = readq(&bar0->spi_control);
5344 if (val64 & SPI_CONTROL_NACK) {
5345 ret = 1;
5346 break;
5347 } else if (val64 & SPI_CONTROL_DONE) {
5348 ret = 0;
5349 break;
5350 }
5351 msleep(50);
5352 exit_cnt++;
5353 }
5354 }
5355 return ret;
5356 }
5357 static void s2io_vpd_read(struct s2io_nic *nic)
5358 {
5359 u8 *vpd_data;
5360 u8 data;
5361 int i=0, cnt, fail = 0;
5362 int vpd_addr = 0x80;
5363
5364 if (nic->device_type == XFRAME_II_DEVICE) {
5365 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5366 vpd_addr = 0x80;
5367 }
5368 else {
5369 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5370 vpd_addr = 0x50;
5371 }
5372 strcpy(nic->serial_num, "NOT AVAILABLE");
5373
5374 vpd_data = kmalloc(256, GFP_KERNEL);
5375 if (!vpd_data) {
5376 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5377 return;
5378 }
5379 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5380
5381 for (i = 0; i < 256; i +=4 ) {
5382 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5383 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5384 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5385 for (cnt = 0; cnt <5; cnt++) {
5386 msleep(2);
5387 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5388 if (data == 0x80)
5389 break;
5390 }
5391 if (cnt >= 5) {
5392 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5393 fail = 1;
5394 break;
5395 }
5396 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5397 (u32 *)&vpd_data[i]);
5398 }
5399
5400 if(!fail) {
5401 /* read serial number of adapter */
5402 for (cnt = 0; cnt < 256; cnt++) {
5403 if ((vpd_data[cnt] == 'S') &&
5404 (vpd_data[cnt+1] == 'N') &&
5405 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5406 memset(nic->serial_num, 0, VPD_STRING_LEN);
5407 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5408 vpd_data[cnt+2]);
5409 break;
5410 }
5411 }
5412 }
5413
5414 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5415 memset(nic->product_name, 0, vpd_data[1]);
5416 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5417 }
5418 kfree(vpd_data);
5419 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5420 }
5421
5422 /**
5423 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5424 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5425 * @eeprom : pointer to the user level structure provided by ethtool,
5426 * containing all relevant information.
5427 * @data_buf : user defined value to be written into Eeprom.
5428 * Description: Reads the values stored in the Eeprom at given offset
5429 * for a given length. Stores these values int the input argument data
5430 * buffer 'data_buf' and returns these to the caller (ethtool.)
5431 * Return value:
5432 * int 0 on success
5433 */
5434
5435 static int s2io_ethtool_geeprom(struct net_device *dev,
5436 struct ethtool_eeprom *eeprom, u8 * data_buf)
5437 {
5438 u32 i, valid;
5439 u64 data;
5440 struct s2io_nic *sp = dev->priv;
5441
5442 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5443
5444 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5445 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5446
5447 for (i = 0; i < eeprom->len; i += 4) {
5448 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5449 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5450 return -EFAULT;
5451 }
5452 valid = INV(data);
5453 memcpy((data_buf + i), &valid, 4);
5454 }
5455 return 0;
5456 }
5457
5458 /**
5459 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5460 * @sp : private member of the device structure, which is a pointer to the
5461 * s2io_nic structure.
5462 * @eeprom : pointer to the user level structure provided by ethtool,
5463 * containing all relevant information.
5464 * @data_buf ; user defined value to be written into Eeprom.
5465 * Description:
5466 * Tries to write the user provided value in the Eeprom, at the offset
5467 * given by the user.
5468 * Return value:
5469 * 0 on success, -EFAULT on failure.
5470 */
5471
5472 static int s2io_ethtool_seeprom(struct net_device *dev,
5473 struct ethtool_eeprom *eeprom,
5474 u8 * data_buf)
5475 {
5476 int len = eeprom->len, cnt = 0;
5477 u64 valid = 0, data;
5478 struct s2io_nic *sp = dev->priv;
5479
5480 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5481 DBG_PRINT(ERR_DBG,
5482 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5483 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5484 eeprom->magic);
5485 return -EFAULT;
5486 }
5487
5488 while (len) {
5489 data = (u32) data_buf[cnt] & 0x000000FF;
5490 if (data) {
5491 valid = (u32) (data << 24);
5492 } else
5493 valid = data;
5494
5495 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5496 DBG_PRINT(ERR_DBG,
5497 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5498 DBG_PRINT(ERR_DBG,
5499 "write into the specified offset\n");
5500 return -EFAULT;
5501 }
5502 cnt++;
5503 len--;
5504 }
5505
5506 return 0;
5507 }
5508
5509 /**
5510 * s2io_register_test - reads and writes into all clock domains.
5511 * @sp : private member of the device structure, which is a pointer to the
5512 * s2io_nic structure.
5513 * @data : variable that returns the result of each of the test conducted b
5514 * by the driver.
5515 * Description:
5516 * Read and write into all clock domains. The NIC has 3 clock domains,
5517 * see that registers in all the three regions are accessible.
5518 * Return value:
5519 * 0 on success.
5520 */
5521
5522 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5523 {
5524 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5525 u64 val64 = 0, exp_val;
5526 int fail = 0;
5527
5528 val64 = readq(&bar0->pif_rd_swapper_fb);
5529 if (val64 != 0x123456789abcdefULL) {
5530 fail = 1;
5531 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5532 }
5533
5534 val64 = readq(&bar0->rmac_pause_cfg);
5535 if (val64 != 0xc000ffff00000000ULL) {
5536 fail = 1;
5537 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5538 }
5539
5540 val64 = readq(&bar0->rx_queue_cfg);
5541 if (sp->device_type == XFRAME_II_DEVICE)
5542 exp_val = 0x0404040404040404ULL;
5543 else
5544 exp_val = 0x0808080808080808ULL;
5545 if (val64 != exp_val) {
5546 fail = 1;
5547 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5548 }
5549
5550 val64 = readq(&bar0->xgxs_efifo_cfg);
5551 if (val64 != 0x000000001923141EULL) {
5552 fail = 1;
5553 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5554 }
5555
5556 val64 = 0x5A5A5A5A5A5A5A5AULL;
5557 writeq(val64, &bar0->xmsi_data);
5558 val64 = readq(&bar0->xmsi_data);
5559 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5560 fail = 1;
5561 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5562 }
5563
5564 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5565 writeq(val64, &bar0->xmsi_data);
5566 val64 = readq(&bar0->xmsi_data);
5567 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5568 fail = 1;
5569 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5570 }
5571
5572 *data = fail;
5573 return fail;
5574 }
5575
5576 /**
5577 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5578 * @sp : private member of the device structure, which is a pointer to the
5579 * s2io_nic structure.
5580 * @data:variable that returns the result of each of the test conducted by
5581 * the driver.
5582 * Description:
5583 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5584 * register.
5585 * Return value:
5586 * 0 on success.
5587 */
5588
5589 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5590 {
5591 int fail = 0;
5592 u64 ret_data, org_4F0, org_7F0;
5593 u8 saved_4F0 = 0, saved_7F0 = 0;
5594 struct net_device *dev = sp->dev;
5595
5596 /* Test Write Error at offset 0 */
5597 /* Note that SPI interface allows write access to all areas
5598 * of EEPROM. Hence doing all negative testing only for Xframe I.
5599 */
5600 if (sp->device_type == XFRAME_I_DEVICE)
5601 if (!write_eeprom(sp, 0, 0, 3))
5602 fail = 1;
5603
5604 /* Save current values at offsets 0x4F0 and 0x7F0 */
5605 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5606 saved_4F0 = 1;
5607 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5608 saved_7F0 = 1;
5609
5610 /* Test Write at offset 4f0 */
5611 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5612 fail = 1;
5613 if (read_eeprom(sp, 0x4F0, &ret_data))
5614 fail = 1;
5615
5616 if (ret_data != 0x012345) {
5617 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5618 "Data written %llx Data read %llx\n",
5619 dev->name, (unsigned long long)0x12345,
5620 (unsigned long long)ret_data);
5621 fail = 1;
5622 }
5623
5624 /* Reset the EEPROM data go FFFF */
5625 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5626
5627 /* Test Write Request Error at offset 0x7c */
5628 if (sp->device_type == XFRAME_I_DEVICE)
5629 if (!write_eeprom(sp, 0x07C, 0, 3))
5630 fail = 1;
5631
5632 /* Test Write Request at offset 0x7f0 */
5633 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5634 fail = 1;
5635 if (read_eeprom(sp, 0x7F0, &ret_data))
5636 fail = 1;
5637
5638 if (ret_data != 0x012345) {
5639 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5640 "Data written %llx Data read %llx\n",
5641 dev->name, (unsigned long long)0x12345,
5642 (unsigned long long)ret_data);
5643 fail = 1;
5644 }
5645
5646 /* Reset the EEPROM data go FFFF */
5647 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5648
5649 if (sp->device_type == XFRAME_I_DEVICE) {
5650 /* Test Write Error at offset 0x80 */
5651 if (!write_eeprom(sp, 0x080, 0, 3))
5652 fail = 1;
5653
5654 /* Test Write Error at offset 0xfc */
5655 if (!write_eeprom(sp, 0x0FC, 0, 3))
5656 fail = 1;
5657
5658 /* Test Write Error at offset 0x100 */
5659 if (!write_eeprom(sp, 0x100, 0, 3))
5660 fail = 1;
5661
5662 /* Test Write Error at offset 4ec */
5663 if (!write_eeprom(sp, 0x4EC, 0, 3))
5664 fail = 1;
5665 }
5666
5667 /* Restore values at offsets 0x4F0 and 0x7F0 */
5668 if (saved_4F0)
5669 write_eeprom(sp, 0x4F0, org_4F0, 3);
5670 if (saved_7F0)
5671 write_eeprom(sp, 0x7F0, org_7F0, 3);
5672
5673 *data = fail;
5674 return fail;
5675 }
5676
5677 /**
5678 * s2io_bist_test - invokes the MemBist test of the card .
5679 * @sp : private member of the device structure, which is a pointer to the
5680 * s2io_nic structure.
5681 * @data:variable that returns the result of each of the test conducted by
5682 * the driver.
5683 * Description:
5684 * This invokes the MemBist test of the card. We give around
5685 * 2 secs time for the Test to complete. If it's still not complete
5686 * within this peiod, we consider that the test failed.
5687 * Return value:
5688 * 0 on success and -1 on failure.
5689 */
5690
5691 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5692 {
5693 u8 bist = 0;
5694 int cnt = 0, ret = -1;
5695
5696 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5697 bist |= PCI_BIST_START;
5698 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5699
5700 while (cnt < 20) {
5701 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5702 if (!(bist & PCI_BIST_START)) {
5703 *data = (bist & PCI_BIST_CODE_MASK);
5704 ret = 0;
5705 break;
5706 }
5707 msleep(100);
5708 cnt++;
5709 }
5710
5711 return ret;
5712 }
5713
5714 /**
5715 * s2io-link_test - verifies the link state of the nic
5716 * @sp ; private member of the device structure, which is a pointer to the
5717 * s2io_nic structure.
5718 * @data: variable that returns the result of each of the test conducted by
5719 * the driver.
5720 * Description:
5721 * The function verifies the link state of the NIC and updates the input
5722 * argument 'data' appropriately.
5723 * Return value:
5724 * 0 on success.
5725 */
5726
5727 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5728 {
5729 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5730 u64 val64;
5731
5732 val64 = readq(&bar0->adapter_status);
5733 if(!(LINK_IS_UP(val64)))
5734 *data = 1;
5735 else
5736 *data = 0;
5737
5738 return *data;
5739 }
5740
5741 /**
5742 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5743 * @sp - private member of the device structure, which is a pointer to the
5744 * s2io_nic structure.
5745 * @data - variable that returns the result of each of the test
5746 * conducted by the driver.
5747 * Description:
5748 * This is one of the offline test that tests the read and write
5749 * access to the RldRam chip on the NIC.
5750 * Return value:
5751 * 0 on success.
5752 */
5753
5754 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5755 {
5756 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5757 u64 val64;
5758 int cnt, iteration = 0, test_fail = 0;
5759
5760 val64 = readq(&bar0->adapter_control);
5761 val64 &= ~ADAPTER_ECC_EN;
5762 writeq(val64, &bar0->adapter_control);
5763
5764 val64 = readq(&bar0->mc_rldram_test_ctrl);
5765 val64 |= MC_RLDRAM_TEST_MODE;
5766 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5767
5768 val64 = readq(&bar0->mc_rldram_mrs);
5769 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5770 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5771
5772 val64 |= MC_RLDRAM_MRS_ENABLE;
5773 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5774
5775 while (iteration < 2) {
5776 val64 = 0x55555555aaaa0000ULL;
5777 if (iteration == 1) {
5778 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5779 }
5780 writeq(val64, &bar0->mc_rldram_test_d0);
5781
5782 val64 = 0xaaaa5a5555550000ULL;
5783 if (iteration == 1) {
5784 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5785 }
5786 writeq(val64, &bar0->mc_rldram_test_d1);
5787
5788 val64 = 0x55aaaaaaaa5a0000ULL;
5789 if (iteration == 1) {
5790 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5791 }
5792 writeq(val64, &bar0->mc_rldram_test_d2);
5793
5794 val64 = (u64) (0x0000003ffffe0100ULL);
5795 writeq(val64, &bar0->mc_rldram_test_add);
5796
5797 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5798 MC_RLDRAM_TEST_GO;
5799 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5800
5801 for (cnt = 0; cnt < 5; cnt++) {
5802 val64 = readq(&bar0->mc_rldram_test_ctrl);
5803 if (val64 & MC_RLDRAM_TEST_DONE)
5804 break;
5805 msleep(200);
5806 }
5807
5808 if (cnt == 5)
5809 break;
5810
5811 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5812 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5813
5814 for (cnt = 0; cnt < 5; cnt++) {
5815 val64 = readq(&bar0->mc_rldram_test_ctrl);
5816 if (val64 & MC_RLDRAM_TEST_DONE)
5817 break;
5818 msleep(500);
5819 }
5820
5821 if (cnt == 5)
5822 break;
5823
5824 val64 = readq(&bar0->mc_rldram_test_ctrl);
5825 if (!(val64 & MC_RLDRAM_TEST_PASS))
5826 test_fail = 1;
5827
5828 iteration++;
5829 }
5830
5831 *data = test_fail;
5832
5833 /* Bring the adapter out of test mode */
5834 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5835
5836 return test_fail;
5837 }
5838
5839 /**
5840 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5841 * @sp : private member of the device structure, which is a pointer to the
5842 * s2io_nic structure.
5843 * @ethtest : pointer to a ethtool command specific structure that will be
5844 * returned to the user.
5845 * @data : variable that returns the result of each of the test
5846 * conducted by the driver.
5847 * Description:
5848 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5849 * the health of the card.
5850 * Return value:
5851 * void
5852 */
5853
5854 static void s2io_ethtool_test(struct net_device *dev,
5855 struct ethtool_test *ethtest,
5856 uint64_t * data)
5857 {
5858 struct s2io_nic *sp = dev->priv;
5859 int orig_state = netif_running(sp->dev);
5860
5861 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5862 /* Offline Tests. */
5863 if (orig_state)
5864 s2io_close(sp->dev);
5865
5866 if (s2io_register_test(sp, &data[0]))
5867 ethtest->flags |= ETH_TEST_FL_FAILED;
5868
5869 s2io_reset(sp);
5870
5871 if (s2io_rldram_test(sp, &data[3]))
5872 ethtest->flags |= ETH_TEST_FL_FAILED;
5873
5874 s2io_reset(sp);
5875
5876 if (s2io_eeprom_test(sp, &data[1]))
5877 ethtest->flags |= ETH_TEST_FL_FAILED;
5878
5879 if (s2io_bist_test(sp, &data[4]))
5880 ethtest->flags |= ETH_TEST_FL_FAILED;
5881
5882 if (orig_state)
5883 s2io_open(sp->dev);
5884
5885 data[2] = 0;
5886 } else {
5887 /* Online Tests. */
5888 if (!orig_state) {
5889 DBG_PRINT(ERR_DBG,
5890 "%s: is not up, cannot run test\n",
5891 dev->name);
5892 data[0] = -1;
5893 data[1] = -1;
5894 data[2] = -1;
5895 data[3] = -1;
5896 data[4] = -1;
5897 }
5898
5899 if (s2io_link_test(sp, &data[2]))
5900 ethtest->flags |= ETH_TEST_FL_FAILED;
5901
5902 data[0] = 0;
5903 data[1] = 0;
5904 data[3] = 0;
5905 data[4] = 0;
5906 }
5907 }
5908
5909 static void s2io_get_ethtool_stats(struct net_device *dev,
5910 struct ethtool_stats *estats,
5911 u64 * tmp_stats)
5912 {
5913 int i = 0, k;
5914 struct s2io_nic *sp = dev->priv;
5915 struct stat_block *stat_info = sp->mac_control.stats_info;
5916
5917 s2io_updt_stats(sp);
5918 tmp_stats[i++] =
5919 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5920 le32_to_cpu(stat_info->tmac_frms);
5921 tmp_stats[i++] =
5922 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5923 le32_to_cpu(stat_info->tmac_data_octets);
5924 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5925 tmp_stats[i++] =
5926 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5927 le32_to_cpu(stat_info->tmac_mcst_frms);
5928 tmp_stats[i++] =
5929 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5930 le32_to_cpu(stat_info->tmac_bcst_frms);
5931 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5932 tmp_stats[i++] =
5933 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5934 le32_to_cpu(stat_info->tmac_ttl_octets);
5935 tmp_stats[i++] =
5936 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5937 le32_to_cpu(stat_info->tmac_ucst_frms);
5938 tmp_stats[i++] =
5939 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5940 le32_to_cpu(stat_info->tmac_nucst_frms);
5941 tmp_stats[i++] =
5942 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5943 le32_to_cpu(stat_info->tmac_any_err_frms);
5944 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5945 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5946 tmp_stats[i++] =
5947 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5948 le32_to_cpu(stat_info->tmac_vld_ip);
5949 tmp_stats[i++] =
5950 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5951 le32_to_cpu(stat_info->tmac_drop_ip);
5952 tmp_stats[i++] =
5953 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5954 le32_to_cpu(stat_info->tmac_icmp);
5955 tmp_stats[i++] =
5956 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5957 le32_to_cpu(stat_info->tmac_rst_tcp);
5958 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5959 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5960 le32_to_cpu(stat_info->tmac_udp);
5961 tmp_stats[i++] =
5962 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5963 le32_to_cpu(stat_info->rmac_vld_frms);
5964 tmp_stats[i++] =
5965 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5966 le32_to_cpu(stat_info->rmac_data_octets);
5967 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5968 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5969 tmp_stats[i++] =
5970 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5971 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5972 tmp_stats[i++] =
5973 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5974 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5975 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5976 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5977 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5978 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5979 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5980 tmp_stats[i++] =
5981 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5982 le32_to_cpu(stat_info->rmac_ttl_octets);
5983 tmp_stats[i++] =
5984 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5985 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5986 tmp_stats[i++] =
5987 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5988 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5989 tmp_stats[i++] =
5990 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5991 le32_to_cpu(stat_info->rmac_discarded_frms);
5992 tmp_stats[i++] =
5993 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5994 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5995 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5996 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5997 tmp_stats[i++] =
5998 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5999 le32_to_cpu(stat_info->rmac_usized_frms);
6000 tmp_stats[i++] =
6001 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6002 le32_to_cpu(stat_info->rmac_osized_frms);
6003 tmp_stats[i++] =
6004 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6005 le32_to_cpu(stat_info->rmac_frag_frms);
6006 tmp_stats[i++] =
6007 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6008 le32_to_cpu(stat_info->rmac_jabber_frms);
6009 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6010 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6011 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6012 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6013 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6014 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6015 tmp_stats[i++] =
6016 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6017 le32_to_cpu(stat_info->rmac_ip);
6018 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6019 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6020 tmp_stats[i++] =
6021 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6022 le32_to_cpu(stat_info->rmac_drop_ip);
6023 tmp_stats[i++] =
6024 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6025 le32_to_cpu(stat_info->rmac_icmp);
6026 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6027 tmp_stats[i++] =
6028 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6029 le32_to_cpu(stat_info->rmac_udp);
6030 tmp_stats[i++] =
6031 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6032 le32_to_cpu(stat_info->rmac_err_drp_udp);
6033 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6034 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6035 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6036 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6037 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6038 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6039 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6040 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6041 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6042 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6043 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6044 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6045 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6046 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6047 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6048 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6049 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6050 tmp_stats[i++] =
6051 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6052 le32_to_cpu(stat_info->rmac_pause_cnt);
6053 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6054 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6055 tmp_stats[i++] =
6056 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6057 le32_to_cpu(stat_info->rmac_accepted_ip);
6058 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6059 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6060 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6061 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6062 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6063 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6064 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6065 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6066 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6067 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6068 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6069 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6070 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6071 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6072 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6073 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6074 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6075 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6076 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6077
6078 /* Enhanced statistics exist only for Hercules */
6079 if(sp->device_type == XFRAME_II_DEVICE) {
6080 tmp_stats[i++] =
6081 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6082 tmp_stats[i++] =
6083 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6084 tmp_stats[i++] =
6085 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6086 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6087 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6088 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6089 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6090 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6091 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6092 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6093 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6094 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6095 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6096 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6097 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6098 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6099 }
6100
6101 tmp_stats[i++] = 0;
6102 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6103 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6104 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6105 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6106 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6107 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6108 for (k = 0; k < MAX_RX_RINGS; k++)
6109 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6110 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6111 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6112 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6113 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6114 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6115 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6116 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6117 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6118 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6119 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6120 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6121 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6122 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6123 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6124 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6125 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6126 if (stat_info->sw_stat.num_aggregations) {
6127 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6128 int count = 0;
6129 /*
6130 * Since 64-bit divide does not work on all platforms,
6131 * do repeated subtraction.
6132 */
6133 while (tmp >= stat_info->sw_stat.num_aggregations) {
6134 tmp -= stat_info->sw_stat.num_aggregations;
6135 count++;
6136 }
6137 tmp_stats[i++] = count;
6138 }
6139 else
6140 tmp_stats[i++] = 0;
6141 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6142 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6143 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6144 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6145 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6146 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6147 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6148 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6149 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6150
6151 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6152 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6153 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6154 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6155 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6156
6157 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6158 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6159 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6160 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6161 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6162 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6163 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6164 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6165 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6166 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6167 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6168 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6169 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6170 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6171 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6172 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6173 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6174 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6175 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6176 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6177 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6178 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6179 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6180 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6181 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6182 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6183 }
6184
6185 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6186 {
6187 return (XENA_REG_SPACE);
6188 }
6189
6190
6191 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6192 {
6193 struct s2io_nic *sp = dev->priv;
6194
6195 return (sp->rx_csum);
6196 }
6197
6198 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6199 {
6200 struct s2io_nic *sp = dev->priv;
6201
6202 if (data)
6203 sp->rx_csum = 1;
6204 else
6205 sp->rx_csum = 0;
6206
6207 return 0;
6208 }
6209
6210 static int s2io_get_eeprom_len(struct net_device *dev)
6211 {
6212 return (XENA_EEPROM_SPACE);
6213 }
6214
6215 static int s2io_get_sset_count(struct net_device *dev, int sset)
6216 {
6217 struct s2io_nic *sp = dev->priv;
6218
6219 switch (sset) {
6220 case ETH_SS_TEST:
6221 return S2IO_TEST_LEN;
6222 case ETH_SS_STATS:
6223 switch(sp->device_type) {
6224 case XFRAME_I_DEVICE:
6225 return XFRAME_I_STAT_LEN;
6226 case XFRAME_II_DEVICE:
6227 return XFRAME_II_STAT_LEN;
6228 default:
6229 return 0;
6230 }
6231 default:
6232 return -EOPNOTSUPP;
6233 }
6234 }
6235
6236 static void s2io_ethtool_get_strings(struct net_device *dev,
6237 u32 stringset, u8 * data)
6238 {
6239 int stat_size = 0;
6240 struct s2io_nic *sp = dev->priv;
6241
6242 switch (stringset) {
6243 case ETH_SS_TEST:
6244 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6245 break;
6246 case ETH_SS_STATS:
6247 stat_size = sizeof(ethtool_xena_stats_keys);
6248 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6249 if(sp->device_type == XFRAME_II_DEVICE) {
6250 memcpy(data + stat_size,
6251 &ethtool_enhanced_stats_keys,
6252 sizeof(ethtool_enhanced_stats_keys));
6253 stat_size += sizeof(ethtool_enhanced_stats_keys);
6254 }
6255
6256 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6257 sizeof(ethtool_driver_stats_keys));
6258 }
6259 }
6260
6261 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6262 {
6263 if (data)
6264 dev->features |= NETIF_F_IP_CSUM;
6265 else
6266 dev->features &= ~NETIF_F_IP_CSUM;
6267
6268 return 0;
6269 }
6270
6271 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6272 {
6273 return (dev->features & NETIF_F_TSO) != 0;
6274 }
6275 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6276 {
6277 if (data)
6278 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6279 else
6280 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6281
6282 return 0;
6283 }
6284
6285 static const struct ethtool_ops netdev_ethtool_ops = {
6286 .get_settings = s2io_ethtool_gset,
6287 .set_settings = s2io_ethtool_sset,
6288 .get_drvinfo = s2io_ethtool_gdrvinfo,
6289 .get_regs_len = s2io_ethtool_get_regs_len,
6290 .get_regs = s2io_ethtool_gregs,
6291 .get_link = ethtool_op_get_link,
6292 .get_eeprom_len = s2io_get_eeprom_len,
6293 .get_eeprom = s2io_ethtool_geeprom,
6294 .set_eeprom = s2io_ethtool_seeprom,
6295 .get_ringparam = s2io_ethtool_gringparam,
6296 .get_pauseparam = s2io_ethtool_getpause_data,
6297 .set_pauseparam = s2io_ethtool_setpause_data,
6298 .get_rx_csum = s2io_ethtool_get_rx_csum,
6299 .set_rx_csum = s2io_ethtool_set_rx_csum,
6300 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6301 .set_sg = ethtool_op_set_sg,
6302 .get_tso = s2io_ethtool_op_get_tso,
6303 .set_tso = s2io_ethtool_op_set_tso,
6304 .set_ufo = ethtool_op_set_ufo,
6305 .self_test = s2io_ethtool_test,
6306 .get_strings = s2io_ethtool_get_strings,
6307 .phys_id = s2io_ethtool_idnic,
6308 .get_ethtool_stats = s2io_get_ethtool_stats,
6309 .get_sset_count = s2io_get_sset_count,
6310 };
6311
6312 /**
6313 * s2io_ioctl - Entry point for the Ioctl
6314 * @dev : Device pointer.
6315 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6316 * a proprietary structure used to pass information to the driver.
6317 * @cmd : This is used to distinguish between the different commands that
6318 * can be passed to the IOCTL functions.
6319 * Description:
6320 * Currently there are no special functionality supported in IOCTL, hence
6321 * function always return EOPNOTSUPPORTED
6322 */
6323
6324 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6325 {
6326 return -EOPNOTSUPP;
6327 }
6328
6329 /**
6330 * s2io_change_mtu - entry point to change MTU size for the device.
6331 * @dev : device pointer.
6332 * @new_mtu : the new MTU size for the device.
6333 * Description: A driver entry point to change MTU size for the device.
6334 * Before changing the MTU the device must be stopped.
6335 * Return value:
6336 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6337 * file on failure.
6338 */
6339
6340 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6341 {
6342 struct s2io_nic *sp = dev->priv;
6343
6344 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6345 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6346 dev->name);
6347 return -EPERM;
6348 }
6349
6350 dev->mtu = new_mtu;
6351 if (netif_running(dev)) {
6352 s2io_card_down(sp);
6353 netif_stop_queue(dev);
6354 if (s2io_card_up(sp)) {
6355 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6356 __FUNCTION__);
6357 }
6358 if (netif_queue_stopped(dev))
6359 netif_wake_queue(dev);
6360 } else { /* Device is down */
6361 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6362 u64 val64 = new_mtu;
6363
6364 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6365 }
6366
6367 return 0;
6368 }
6369
6370 /**
6371 * s2io_tasklet - Bottom half of the ISR.
6372 * @dev_adr : address of the device structure in dma_addr_t format.
6373 * Description:
6374 * This is the tasklet or the bottom half of the ISR. This is
6375 * an extension of the ISR which is scheduled by the scheduler to be run
6376 * when the load on the CPU is low. All low priority tasks of the ISR can
6377 * be pushed into the tasklet. For now the tasklet is used only to
6378 * replenish the Rx buffers in the Rx buffer descriptors.
6379 * Return value:
6380 * void.
6381 */
6382
6383 static void s2io_tasklet(unsigned long dev_addr)
6384 {
6385 struct net_device *dev = (struct net_device *) dev_addr;
6386 struct s2io_nic *sp = dev->priv;
6387 int i, ret;
6388 struct mac_info *mac_control;
6389 struct config_param *config;
6390
6391 mac_control = &sp->mac_control;
6392 config = &sp->config;
6393
6394 if (!TASKLET_IN_USE) {
6395 for (i = 0; i < config->rx_ring_num; i++) {
6396 ret = fill_rx_buffers(sp, i);
6397 if (ret == -ENOMEM) {
6398 DBG_PRINT(INFO_DBG, "%s: Out of ",
6399 dev->name);
6400 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
6401 break;
6402 } else if (ret == -EFILL) {
6403 DBG_PRINT(INFO_DBG,
6404 "%s: Rx Ring %d is full\n",
6405 dev->name, i);
6406 break;
6407 }
6408 }
6409 clear_bit(0, (&sp->tasklet_status));
6410 }
6411 }
6412
6413 /**
6414 * s2io_set_link - Set the LInk status
6415 * @data: long pointer to device private structue
6416 * Description: Sets the link status for the adapter
6417 */
6418
6419 static void s2io_set_link(struct work_struct *work)
6420 {
6421 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6422 struct net_device *dev = nic->dev;
6423 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6424 register u64 val64;
6425 u16 subid;
6426
6427 rtnl_lock();
6428
6429 if (!netif_running(dev))
6430 goto out_unlock;
6431
6432 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6433 /* The card is being reset, no point doing anything */
6434 goto out_unlock;
6435 }
6436
6437 subid = nic->pdev->subsystem_device;
6438 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6439 /*
6440 * Allow a small delay for the NICs self initiated
6441 * cleanup to complete.
6442 */
6443 msleep(100);
6444 }
6445
6446 val64 = readq(&bar0->adapter_status);
6447 if (LINK_IS_UP(val64)) {
6448 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6449 if (verify_xena_quiescence(nic)) {
6450 val64 = readq(&bar0->adapter_control);
6451 val64 |= ADAPTER_CNTL_EN;
6452 writeq(val64, &bar0->adapter_control);
6453 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6454 nic->device_type, subid)) {
6455 val64 = readq(&bar0->gpio_control);
6456 val64 |= GPIO_CTRL_GPIO_0;
6457 writeq(val64, &bar0->gpio_control);
6458 val64 = readq(&bar0->gpio_control);
6459 } else {
6460 val64 |= ADAPTER_LED_ON;
6461 writeq(val64, &bar0->adapter_control);
6462 }
6463 nic->device_enabled_once = TRUE;
6464 } else {
6465 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6466 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6467 netif_stop_queue(dev);
6468 }
6469 }
6470 val64 = readq(&bar0->adapter_control);
6471 val64 |= ADAPTER_LED_ON;
6472 writeq(val64, &bar0->adapter_control);
6473 s2io_link(nic, LINK_UP);
6474 } else {
6475 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6476 subid)) {
6477 val64 = readq(&bar0->gpio_control);
6478 val64 &= ~GPIO_CTRL_GPIO_0;
6479 writeq(val64, &bar0->gpio_control);
6480 val64 = readq(&bar0->gpio_control);
6481 }
6482 /* turn off LED */
6483 val64 = readq(&bar0->adapter_control);
6484 val64 = val64 &(~ADAPTER_LED_ON);
6485 writeq(val64, &bar0->adapter_control);
6486 s2io_link(nic, LINK_DOWN);
6487 }
6488 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6489
6490 out_unlock:
6491 rtnl_unlock();
6492 }
6493
6494 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6495 struct buffAdd *ba,
6496 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6497 u64 *temp2, int size)
6498 {
6499 struct net_device *dev = sp->dev;
6500 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6501
6502 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6503 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6504 /* allocate skb */
6505 if (*skb) {
6506 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6507 /*
6508 * As Rx frame are not going to be processed,
6509 * using same mapped address for the Rxd
6510 * buffer pointer
6511 */
6512 rxdp1->Buffer0_ptr = *temp0;
6513 } else {
6514 *skb = dev_alloc_skb(size);
6515 if (!(*skb)) {
6516 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6517 DBG_PRINT(INFO_DBG, "memory to allocate ");
6518 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6519 sp->mac_control.stats_info->sw_stat. \
6520 mem_alloc_fail_cnt++;
6521 return -ENOMEM ;
6522 }
6523 sp->mac_control.stats_info->sw_stat.mem_allocated
6524 += (*skb)->truesize;
6525 /* storing the mapped addr in a temp variable
6526 * such it will be used for next rxd whose
6527 * Host Control is NULL
6528 */
6529 rxdp1->Buffer0_ptr = *temp0 =
6530 pci_map_single( sp->pdev, (*skb)->data,
6531 size - NET_IP_ALIGN,
6532 PCI_DMA_FROMDEVICE);
6533 if( (rxdp1->Buffer0_ptr == 0) ||
6534 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6535 goto memalloc_failed;
6536 }
6537 rxdp->Host_Control = (unsigned long) (*skb);
6538 }
6539 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6540 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6541 /* Two buffer Mode */
6542 if (*skb) {
6543 rxdp3->Buffer2_ptr = *temp2;
6544 rxdp3->Buffer0_ptr = *temp0;
6545 rxdp3->Buffer1_ptr = *temp1;
6546 } else {
6547 *skb = dev_alloc_skb(size);
6548 if (!(*skb)) {
6549 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6550 DBG_PRINT(INFO_DBG, "memory to allocate ");
6551 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6552 sp->mac_control.stats_info->sw_stat. \
6553 mem_alloc_fail_cnt++;
6554 return -ENOMEM;
6555 }
6556 sp->mac_control.stats_info->sw_stat.mem_allocated
6557 += (*skb)->truesize;
6558 rxdp3->Buffer2_ptr = *temp2 =
6559 pci_map_single(sp->pdev, (*skb)->data,
6560 dev->mtu + 4,
6561 PCI_DMA_FROMDEVICE);
6562 if( (rxdp3->Buffer2_ptr == 0) ||
6563 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6564 goto memalloc_failed;
6565 }
6566 rxdp3->Buffer0_ptr = *temp0 =
6567 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6568 PCI_DMA_FROMDEVICE);
6569 if( (rxdp3->Buffer0_ptr == 0) ||
6570 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6571 pci_unmap_single (sp->pdev,
6572 (dma_addr_t)rxdp3->Buffer2_ptr,
6573 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6574 goto memalloc_failed;
6575 }
6576 rxdp->Host_Control = (unsigned long) (*skb);
6577
6578 /* Buffer-1 will be dummy buffer not used */
6579 rxdp3->Buffer1_ptr = *temp1 =
6580 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6581 PCI_DMA_FROMDEVICE);
6582 if( (rxdp3->Buffer1_ptr == 0) ||
6583 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6584 pci_unmap_single (sp->pdev,
6585 (dma_addr_t)rxdp3->Buffer0_ptr,
6586 BUF0_LEN, PCI_DMA_FROMDEVICE);
6587 pci_unmap_single (sp->pdev,
6588 (dma_addr_t)rxdp3->Buffer2_ptr,
6589 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6590 goto memalloc_failed;
6591 }
6592 }
6593 }
6594 return 0;
6595 memalloc_failed:
6596 stats->pci_map_fail_cnt++;
6597 stats->mem_freed += (*skb)->truesize;
6598 dev_kfree_skb(*skb);
6599 return -ENOMEM;
6600 }
6601
6602 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6603 int size)
6604 {
6605 struct net_device *dev = sp->dev;
6606 if (sp->rxd_mode == RXD_MODE_1) {
6607 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6608 } else if (sp->rxd_mode == RXD_MODE_3B) {
6609 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6610 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6611 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6612 }
6613 }
6614
6615 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6616 {
6617 int i, j, k, blk_cnt = 0, size;
6618 struct mac_info * mac_control = &sp->mac_control;
6619 struct config_param *config = &sp->config;
6620 struct net_device *dev = sp->dev;
6621 struct RxD_t *rxdp = NULL;
6622 struct sk_buff *skb = NULL;
6623 struct buffAdd *ba = NULL;
6624 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6625
6626 /* Calculate the size based on ring mode */
6627 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6628 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6629 if (sp->rxd_mode == RXD_MODE_1)
6630 size += NET_IP_ALIGN;
6631 else if (sp->rxd_mode == RXD_MODE_3B)
6632 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6633
6634 for (i = 0; i < config->rx_ring_num; i++) {
6635 blk_cnt = config->rx_cfg[i].num_rxd /
6636 (rxd_count[sp->rxd_mode] +1);
6637
6638 for (j = 0; j < blk_cnt; j++) {
6639 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6640 rxdp = mac_control->rings[i].
6641 rx_blocks[j].rxds[k].virt_addr;
6642 if(sp->rxd_mode == RXD_MODE_3B)
6643 ba = &mac_control->rings[i].ba[j][k];
6644 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6645 &skb,(u64 *)&temp0_64,
6646 (u64 *)&temp1_64,
6647 (u64 *)&temp2_64,
6648 size) == ENOMEM) {
6649 return 0;
6650 }
6651
6652 set_rxd_buffer_size(sp, rxdp, size);
6653 wmb();
6654 /* flip the Ownership bit to Hardware */
6655 rxdp->Control_1 |= RXD_OWN_XENA;
6656 }
6657 }
6658 }
6659 return 0;
6660
6661 }
6662
6663 static int s2io_add_isr(struct s2io_nic * sp)
6664 {
6665 int ret = 0;
6666 struct net_device *dev = sp->dev;
6667 int err = 0;
6668
6669 if (sp->config.intr_type == MSI_X)
6670 ret = s2io_enable_msi_x(sp);
6671 if (ret) {
6672 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6673 sp->config.intr_type = INTA;
6674 }
6675
6676 /* Store the values of the MSIX table in the struct s2io_nic structure */
6677 store_xmsi_data(sp);
6678
6679 /* After proper initialization of H/W, register ISR */
6680 if (sp->config.intr_type == MSI_X) {
6681 int i, msix_tx_cnt=0,msix_rx_cnt=0;
6682
6683 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6684 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6685 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6686 dev->name, i);
6687 err = request_irq(sp->entries[i].vector,
6688 s2io_msix_fifo_handle, 0, sp->desc[i],
6689 sp->s2io_entries[i].arg);
6690 /* If either data or addr is zero print it */
6691 if(!(sp->msix_info[i].addr &&
6692 sp->msix_info[i].data)) {
6693 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6694 "Data:0x%lx\n",sp->desc[i],
6695 (unsigned long long)
6696 sp->msix_info[i].addr,
6697 (unsigned long)
6698 ntohl(sp->msix_info[i].data));
6699 } else {
6700 msix_tx_cnt++;
6701 }
6702 } else {
6703 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6704 dev->name, i);
6705 err = request_irq(sp->entries[i].vector,
6706 s2io_msix_ring_handle, 0, sp->desc[i],
6707 sp->s2io_entries[i].arg);
6708 /* If either data or addr is zero print it */
6709 if(!(sp->msix_info[i].addr &&
6710 sp->msix_info[i].data)) {
6711 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6712 "Data:0x%lx\n",sp->desc[i],
6713 (unsigned long long)
6714 sp->msix_info[i].addr,
6715 (unsigned long)
6716 ntohl(sp->msix_info[i].data));
6717 } else {
6718 msix_rx_cnt++;
6719 }
6720 }
6721 if (err) {
6722 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6723 "failed\n", dev->name, i);
6724 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6725 return -1;
6726 }
6727 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6728 }
6729 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6730 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
6731 }
6732 if (sp->config.intr_type == INTA) {
6733 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6734 sp->name, dev);
6735 if (err) {
6736 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6737 dev->name);
6738 return -1;
6739 }
6740 }
6741 return 0;
6742 }
6743 static void s2io_rem_isr(struct s2io_nic * sp)
6744 {
6745 struct net_device *dev = sp->dev;
6746 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6747
6748 if (sp->config.intr_type == MSI_X) {
6749 int i;
6750 u16 msi_control;
6751
6752 for (i=1; (sp->s2io_entries[i].in_use ==
6753 MSIX_REGISTERED_SUCCESS); i++) {
6754 int vector = sp->entries[i].vector;
6755 void *arg = sp->s2io_entries[i].arg;
6756
6757 synchronize_irq(vector);
6758 free_irq(vector, arg);
6759 }
6760
6761 kfree(sp->entries);
6762 stats->mem_freed +=
6763 (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
6764 kfree(sp->s2io_entries);
6765 stats->mem_freed +=
6766 (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
6767 sp->entries = NULL;
6768 sp->s2io_entries = NULL;
6769
6770 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6771 msi_control &= 0xFFFE; /* Disable MSI */
6772 pci_write_config_word(sp->pdev, 0x42, msi_control);
6773
6774 pci_disable_msix(sp->pdev);
6775 } else {
6776 synchronize_irq(sp->pdev->irq);
6777 free_irq(sp->pdev->irq, dev);
6778 }
6779 }
6780
6781 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
6782 {
6783 int cnt = 0;
6784 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6785 unsigned long flags;
6786 register u64 val64 = 0;
6787
6788 del_timer_sync(&sp->alarm_timer);
6789 /* If s2io_set_link task is executing, wait till it completes. */
6790 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
6791 msleep(50);
6792 }
6793 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
6794
6795 /* disable Tx and Rx traffic on the NIC */
6796 if (do_io)
6797 stop_nic(sp);
6798
6799 s2io_rem_isr(sp);
6800
6801 /* Kill tasklet. */
6802 tasklet_kill(&sp->task);
6803
6804 /* Check if the device is Quiescent and then Reset the NIC */
6805 while(do_io) {
6806 /* As per the HW requirement we need to replenish the
6807 * receive buffer to avoid the ring bump. Since there is
6808 * no intention of processing the Rx frame at this pointwe are
6809 * just settting the ownership bit of rxd in Each Rx
6810 * ring to HW and set the appropriate buffer size
6811 * based on the ring mode
6812 */
6813 rxd_owner_bit_reset(sp);
6814
6815 val64 = readq(&bar0->adapter_status);
6816 if (verify_xena_quiescence(sp)) {
6817 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6818 break;
6819 }
6820
6821 msleep(50);
6822 cnt++;
6823 if (cnt == 10) {
6824 DBG_PRINT(ERR_DBG,
6825 "s2io_close:Device not Quiescent ");
6826 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6827 (unsigned long long) val64);
6828 break;
6829 }
6830 }
6831 if (do_io)
6832 s2io_reset(sp);
6833
6834 spin_lock_irqsave(&sp->tx_lock, flags);
6835 /* Free all Tx buffers */
6836 free_tx_buffers(sp);
6837 spin_unlock_irqrestore(&sp->tx_lock, flags);
6838
6839 /* Free all Rx buffers */
6840 spin_lock_irqsave(&sp->rx_lock, flags);
6841 free_rx_buffers(sp);
6842 spin_unlock_irqrestore(&sp->rx_lock, flags);
6843
6844 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
6845 }
6846
6847 static void s2io_card_down(struct s2io_nic * sp)
6848 {
6849 do_s2io_card_down(sp, 1);
6850 }
6851
6852 static int s2io_card_up(struct s2io_nic * sp)
6853 {
6854 int i, ret = 0;
6855 struct mac_info *mac_control;
6856 struct config_param *config;
6857 struct net_device *dev = (struct net_device *) sp->dev;
6858 u16 interruptible;
6859
6860 /* Initialize the H/W I/O registers */
6861 if (init_nic(sp) != 0) {
6862 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6863 dev->name);
6864 s2io_reset(sp);
6865 return -ENODEV;
6866 }
6867
6868 /*
6869 * Initializing the Rx buffers. For now we are considering only 1
6870 * Rx ring and initializing buffers into 30 Rx blocks
6871 */
6872 mac_control = &sp->mac_control;
6873 config = &sp->config;
6874
6875 for (i = 0; i < config->rx_ring_num; i++) {
6876 if ((ret = fill_rx_buffers(sp, i))) {
6877 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6878 dev->name);
6879 s2io_reset(sp);
6880 free_rx_buffers(sp);
6881 return -ENOMEM;
6882 }
6883 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6884 atomic_read(&sp->rx_bufs_left[i]));
6885 }
6886 /* Maintain the state prior to the open */
6887 if (sp->promisc_flg)
6888 sp->promisc_flg = 0;
6889 if (sp->m_cast_flg) {
6890 sp->m_cast_flg = 0;
6891 sp->all_multi_pos= 0;
6892 }
6893
6894 /* Setting its receive mode */
6895 s2io_set_multicast(dev);
6896
6897 if (sp->lro) {
6898 /* Initialize max aggregatable pkts per session based on MTU */
6899 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6900 /* Check if we can use(if specified) user provided value */
6901 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6902 sp->lro_max_aggr_per_sess = lro_max_pkts;
6903 }
6904
6905 /* Enable Rx Traffic and interrupts on the NIC */
6906 if (start_nic(sp)) {
6907 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6908 s2io_reset(sp);
6909 free_rx_buffers(sp);
6910 return -ENODEV;
6911 }
6912
6913 /* Add interrupt service routine */
6914 if (s2io_add_isr(sp) != 0) {
6915 if (sp->config.intr_type == MSI_X)
6916 s2io_rem_isr(sp);
6917 s2io_reset(sp);
6918 free_rx_buffers(sp);
6919 return -ENODEV;
6920 }
6921
6922 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6923
6924 /* Enable tasklet for the device */
6925 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6926
6927 /* Enable select interrupts */
6928 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
6929 if (sp->config.intr_type != INTA)
6930 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6931 else {
6932 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6933 interruptible |= TX_PIC_INTR;
6934 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6935 }
6936
6937 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
6938 return 0;
6939 }
6940
6941 /**
6942 * s2io_restart_nic - Resets the NIC.
6943 * @data : long pointer to the device private structure
6944 * Description:
6945 * This function is scheduled to be run by the s2io_tx_watchdog
6946 * function after 0.5 secs to reset the NIC. The idea is to reduce
6947 * the run time of the watch dog routine which is run holding a
6948 * spin lock.
6949 */
6950
6951 static void s2io_restart_nic(struct work_struct *work)
6952 {
6953 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
6954 struct net_device *dev = sp->dev;
6955
6956 rtnl_lock();
6957
6958 if (!netif_running(dev))
6959 goto out_unlock;
6960
6961 s2io_card_down(sp);
6962 if (s2io_card_up(sp)) {
6963 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6964 dev->name);
6965 }
6966 netif_wake_queue(dev);
6967 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6968 dev->name);
6969 out_unlock:
6970 rtnl_unlock();
6971 }
6972
6973 /**
6974 * s2io_tx_watchdog - Watchdog for transmit side.
6975 * @dev : Pointer to net device structure
6976 * Description:
6977 * This function is triggered if the Tx Queue is stopped
6978 * for a pre-defined amount of time when the Interface is still up.
6979 * If the Interface is jammed in such a situation, the hardware is
6980 * reset (by s2io_close) and restarted again (by s2io_open) to
6981 * overcome any problem that might have been caused in the hardware.
6982 * Return value:
6983 * void
6984 */
6985
6986 static void s2io_tx_watchdog(struct net_device *dev)
6987 {
6988 struct s2io_nic *sp = dev->priv;
6989
6990 if (netif_carrier_ok(dev)) {
6991 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
6992 schedule_work(&sp->rst_timer_task);
6993 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6994 }
6995 }
6996
6997 /**
6998 * rx_osm_handler - To perform some OS related operations on SKB.
6999 * @sp: private member of the device structure,pointer to s2io_nic structure.
7000 * @skb : the socket buffer pointer.
7001 * @len : length of the packet
7002 * @cksum : FCS checksum of the frame.
7003 * @ring_no : the ring from which this RxD was extracted.
7004 * Description:
7005 * This function is called by the Rx interrupt serivce routine to perform
7006 * some OS related operations on the SKB before passing it to the upper
7007 * layers. It mainly checks if the checksum is OK, if so adds it to the
7008 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7009 * to the upper layer. If the checksum is wrong, it increments the Rx
7010 * packet error count, frees the SKB and returns error.
7011 * Return value:
7012 * SUCCESS on success and -1 on failure.
7013 */
7014 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7015 {
7016 struct s2io_nic *sp = ring_data->nic;
7017 struct net_device *dev = (struct net_device *) sp->dev;
7018 struct sk_buff *skb = (struct sk_buff *)
7019 ((unsigned long) rxdp->Host_Control);
7020 int ring_no = ring_data->ring_no;
7021 u16 l3_csum, l4_csum;
7022 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7023 struct lro *lro;
7024 u8 err_mask;
7025
7026 skb->dev = dev;
7027
7028 if (err) {
7029 /* Check for parity error */
7030 if (err & 0x1) {
7031 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7032 }
7033 err_mask = err >> 48;
7034 switch(err_mask) {
7035 case 1:
7036 sp->mac_control.stats_info->sw_stat.
7037 rx_parity_err_cnt++;
7038 break;
7039
7040 case 2:
7041 sp->mac_control.stats_info->sw_stat.
7042 rx_abort_cnt++;
7043 break;
7044
7045 case 3:
7046 sp->mac_control.stats_info->sw_stat.
7047 rx_parity_abort_cnt++;
7048 break;
7049
7050 case 4:
7051 sp->mac_control.stats_info->sw_stat.
7052 rx_rda_fail_cnt++;
7053 break;
7054
7055 case 5:
7056 sp->mac_control.stats_info->sw_stat.
7057 rx_unkn_prot_cnt++;
7058 break;
7059
7060 case 6:
7061 sp->mac_control.stats_info->sw_stat.
7062 rx_fcs_err_cnt++;
7063 break;
7064
7065 case 7:
7066 sp->mac_control.stats_info->sw_stat.
7067 rx_buf_size_err_cnt++;
7068 break;
7069
7070 case 8:
7071 sp->mac_control.stats_info->sw_stat.
7072 rx_rxd_corrupt_cnt++;
7073 break;
7074
7075 case 15:
7076 sp->mac_control.stats_info->sw_stat.
7077 rx_unkn_err_cnt++;
7078 break;
7079 }
7080 /*
7081 * Drop the packet if bad transfer code. Exception being
7082 * 0x5, which could be due to unsupported IPv6 extension header.
7083 * In this case, we let stack handle the packet.
7084 * Note that in this case, since checksum will be incorrect,
7085 * stack will validate the same.
7086 */
7087 if (err_mask != 0x5) {
7088 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7089 dev->name, err_mask);
7090 sp->stats.rx_crc_errors++;
7091 sp->mac_control.stats_info->sw_stat.mem_freed
7092 += skb->truesize;
7093 dev_kfree_skb(skb);
7094 atomic_dec(&sp->rx_bufs_left[ring_no]);
7095 rxdp->Host_Control = 0;
7096 return 0;
7097 }
7098 }
7099
7100 /* Updating statistics */
7101 sp->stats.rx_packets++;
7102 rxdp->Host_Control = 0;
7103 if (sp->rxd_mode == RXD_MODE_1) {
7104 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7105
7106 sp->stats.rx_bytes += len;
7107 skb_put(skb, len);
7108
7109 } else if (sp->rxd_mode == RXD_MODE_3B) {
7110 int get_block = ring_data->rx_curr_get_info.block_index;
7111 int get_off = ring_data->rx_curr_get_info.offset;
7112 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7113 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7114 unsigned char *buff = skb_push(skb, buf0_len);
7115
7116 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7117 sp->stats.rx_bytes += buf0_len + buf2_len;
7118 memcpy(buff, ba->ba_0, buf0_len);
7119 skb_put(skb, buf2_len);
7120 }
7121
7122 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7123 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7124 (sp->rx_csum)) {
7125 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7126 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7127 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7128 /*
7129 * NIC verifies if the Checksum of the received
7130 * frame is Ok or not and accordingly returns
7131 * a flag in the RxD.
7132 */
7133 skb->ip_summed = CHECKSUM_UNNECESSARY;
7134 if (sp->lro) {
7135 u32 tcp_len;
7136 u8 *tcp;
7137 int ret = 0;
7138
7139 ret = s2io_club_tcp_session(skb->data, &tcp,
7140 &tcp_len, &lro,
7141 rxdp, sp);
7142 switch (ret) {
7143 case 3: /* Begin anew */
7144 lro->parent = skb;
7145 goto aggregate;
7146 case 1: /* Aggregate */
7147 {
7148 lro_append_pkt(sp, lro,
7149 skb, tcp_len);
7150 goto aggregate;
7151 }
7152 case 4: /* Flush session */
7153 {
7154 lro_append_pkt(sp, lro,
7155 skb, tcp_len);
7156 queue_rx_frame(lro->parent);
7157 clear_lro_session(lro);
7158 sp->mac_control.stats_info->
7159 sw_stat.flush_max_pkts++;
7160 goto aggregate;
7161 }
7162 case 2: /* Flush both */
7163 lro->parent->data_len =
7164 lro->frags_len;
7165 sp->mac_control.stats_info->
7166 sw_stat.sending_both++;
7167 queue_rx_frame(lro->parent);
7168 clear_lro_session(lro);
7169 goto send_up;
7170 case 0: /* sessions exceeded */
7171 case -1: /* non-TCP or not
7172 * L2 aggregatable
7173 */
7174 case 5: /*
7175 * First pkt in session not
7176 * L3/L4 aggregatable
7177 */
7178 break;
7179 default:
7180 DBG_PRINT(ERR_DBG,
7181 "%s: Samadhana!!\n",
7182 __FUNCTION__);
7183 BUG();
7184 }
7185 }
7186 } else {
7187 /*
7188 * Packet with erroneous checksum, let the
7189 * upper layers deal with it.
7190 */
7191 skb->ip_summed = CHECKSUM_NONE;
7192 }
7193 } else {
7194 skb->ip_summed = CHECKSUM_NONE;
7195 }
7196 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7197 if (!sp->lro) {
7198 skb->protocol = eth_type_trans(skb, dev);
7199 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7200 vlan_strip_flag)) {
7201 /* Queueing the vlan frame to the upper layer */
7202 if (napi)
7203 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7204 RXD_GET_VLAN_TAG(rxdp->Control_2));
7205 else
7206 vlan_hwaccel_rx(skb, sp->vlgrp,
7207 RXD_GET_VLAN_TAG(rxdp->Control_2));
7208 } else {
7209 if (napi)
7210 netif_receive_skb(skb);
7211 else
7212 netif_rx(skb);
7213 }
7214 } else {
7215 send_up:
7216 queue_rx_frame(skb);
7217 }
7218 dev->last_rx = jiffies;
7219 aggregate:
7220 atomic_dec(&sp->rx_bufs_left[ring_no]);
7221 return SUCCESS;
7222 }
7223
7224 /**
7225 * s2io_link - stops/starts the Tx queue.
7226 * @sp : private member of the device structure, which is a pointer to the
7227 * s2io_nic structure.
7228 * @link : inidicates whether link is UP/DOWN.
7229 * Description:
7230 * This function stops/starts the Tx queue depending on whether the link
7231 * status of the NIC is is down or up. This is called by the Alarm
7232 * interrupt handler whenever a link change interrupt comes up.
7233 * Return value:
7234 * void.
7235 */
7236
7237 static void s2io_link(struct s2io_nic * sp, int link)
7238 {
7239 struct net_device *dev = (struct net_device *) sp->dev;
7240
7241 if (link != sp->last_link_state) {
7242 if (link == LINK_DOWN) {
7243 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7244 netif_carrier_off(dev);
7245 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7246 sp->mac_control.stats_info->sw_stat.link_up_time =
7247 jiffies - sp->start_time;
7248 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7249 } else {
7250 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7251 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7252 sp->mac_control.stats_info->sw_stat.link_down_time =
7253 jiffies - sp->start_time;
7254 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7255 netif_carrier_on(dev);
7256 }
7257 }
7258 sp->last_link_state = link;
7259 sp->start_time = jiffies;
7260 }
7261
7262 /**
7263 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7264 * @sp : private member of the device structure, which is a pointer to the
7265 * s2io_nic structure.
7266 * Description:
7267 * This function initializes a few of the PCI and PCI-X configuration registers
7268 * with recommended values.
7269 * Return value:
7270 * void
7271 */
7272
7273 static void s2io_init_pci(struct s2io_nic * sp)
7274 {
7275 u16 pci_cmd = 0, pcix_cmd = 0;
7276
7277 /* Enable Data Parity Error Recovery in PCI-X command register. */
7278 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7279 &(pcix_cmd));
7280 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7281 (pcix_cmd | 1));
7282 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7283 &(pcix_cmd));
7284
7285 /* Set the PErr Response bit in PCI command register. */
7286 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7287 pci_write_config_word(sp->pdev, PCI_COMMAND,
7288 (pci_cmd | PCI_COMMAND_PARITY));
7289 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7290 }
7291
7292 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7293 {
7294 if ( tx_fifo_num > 8) {
7295 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
7296 "supported\n");
7297 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
7298 tx_fifo_num = 8;
7299 }
7300 if ( rx_ring_num > 8) {
7301 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7302 "supported\n");
7303 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7304 rx_ring_num = 8;
7305 }
7306 if (*dev_intr_type != INTA)
7307 napi = 0;
7308
7309 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7310 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7311 "Defaulting to INTA\n");
7312 *dev_intr_type = INTA;
7313 }
7314
7315 if ((*dev_intr_type == MSI_X) &&
7316 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7317 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7318 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7319 "Defaulting to INTA\n");
7320 *dev_intr_type = INTA;
7321 }
7322
7323 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7324 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7325 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7326 rx_ring_mode = 1;
7327 }
7328 return SUCCESS;
7329 }
7330
7331 /**
7332 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7333 * or Traffic class respectively.
7334 * @nic: device peivate variable
7335 * Description: The function configures the receive steering to
7336 * desired receive ring.
7337 * Return Value: SUCCESS on success and
7338 * '-1' on failure (endian settings incorrect).
7339 */
7340 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7341 {
7342 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7343 register u64 val64 = 0;
7344
7345 if (ds_codepoint > 63)
7346 return FAILURE;
7347
7348 val64 = RTS_DS_MEM_DATA(ring);
7349 writeq(val64, &bar0->rts_ds_mem_data);
7350
7351 val64 = RTS_DS_MEM_CTRL_WE |
7352 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7353 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7354
7355 writeq(val64, &bar0->rts_ds_mem_ctrl);
7356
7357 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7358 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7359 S2IO_BIT_RESET);
7360 }
7361
7362 /**
7363 * s2io_init_nic - Initialization of the adapter .
7364 * @pdev : structure containing the PCI related information of the device.
7365 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7366 * Description:
7367 * The function initializes an adapter identified by the pci_dec structure.
7368 * All OS related initialization including memory and device structure and
7369 * initlaization of the device private variable is done. Also the swapper
7370 * control register is initialized to enable read and write into the I/O
7371 * registers of the device.
7372 * Return value:
7373 * returns 0 on success and negative on failure.
7374 */
7375
7376 static int __devinit
7377 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7378 {
7379 struct s2io_nic *sp;
7380 struct net_device *dev;
7381 int i, j, ret;
7382 int dma_flag = FALSE;
7383 u32 mac_up, mac_down;
7384 u64 val64 = 0, tmp64 = 0;
7385 struct XENA_dev_config __iomem *bar0 = NULL;
7386 u16 subid;
7387 struct mac_info *mac_control;
7388 struct config_param *config;
7389 int mode;
7390 u8 dev_intr_type = intr_type;
7391 DECLARE_MAC_BUF(mac);
7392
7393 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7394 return ret;
7395
7396 if ((ret = pci_enable_device(pdev))) {
7397 DBG_PRINT(ERR_DBG,
7398 "s2io_init_nic: pci_enable_device failed\n");
7399 return ret;
7400 }
7401
7402 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7403 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7404 dma_flag = TRUE;
7405 if (pci_set_consistent_dma_mask
7406 (pdev, DMA_64BIT_MASK)) {
7407 DBG_PRINT(ERR_DBG,
7408 "Unable to obtain 64bit DMA for \
7409 consistent allocations\n");
7410 pci_disable_device(pdev);
7411 return -ENOMEM;
7412 }
7413 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7414 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7415 } else {
7416 pci_disable_device(pdev);
7417 return -ENOMEM;
7418 }
7419 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7420 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7421 pci_disable_device(pdev);
7422 return -ENODEV;
7423 }
7424
7425 dev = alloc_etherdev(sizeof(struct s2io_nic));
7426 if (dev == NULL) {
7427 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7428 pci_disable_device(pdev);
7429 pci_release_regions(pdev);
7430 return -ENODEV;
7431 }
7432
7433 pci_set_master(pdev);
7434 pci_set_drvdata(pdev, dev);
7435 SET_NETDEV_DEV(dev, &pdev->dev);
7436
7437 /* Private member variable initialized to s2io NIC structure */
7438 sp = dev->priv;
7439 memset(sp, 0, sizeof(struct s2io_nic));
7440 sp->dev = dev;
7441 sp->pdev = pdev;
7442 sp->high_dma_flag = dma_flag;
7443 sp->device_enabled_once = FALSE;
7444 if (rx_ring_mode == 1)
7445 sp->rxd_mode = RXD_MODE_1;
7446 if (rx_ring_mode == 2)
7447 sp->rxd_mode = RXD_MODE_3B;
7448
7449 sp->config.intr_type = dev_intr_type;
7450
7451 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7452 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7453 sp->device_type = XFRAME_II_DEVICE;
7454 else
7455 sp->device_type = XFRAME_I_DEVICE;
7456
7457 sp->lro = lro_enable;
7458
7459 /* Initialize some PCI/PCI-X fields of the NIC. */
7460 s2io_init_pci(sp);
7461
7462 /*
7463 * Setting the device configuration parameters.
7464 * Most of these parameters can be specified by the user during
7465 * module insertion as they are module loadable parameters. If
7466 * these parameters are not not specified during load time, they
7467 * are initialized with default values.
7468 */
7469 mac_control = &sp->mac_control;
7470 config = &sp->config;
7471
7472 config->napi = napi;
7473
7474 /* Tx side parameters. */
7475 config->tx_fifo_num = tx_fifo_num;
7476 for (i = 0; i < MAX_TX_FIFOS; i++) {
7477 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7478 config->tx_cfg[i].fifo_priority = i;
7479 }
7480
7481 /* mapping the QoS priority to the configured fifos */
7482 for (i = 0; i < MAX_TX_FIFOS; i++)
7483 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7484
7485 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7486 for (i = 0; i < config->tx_fifo_num; i++) {
7487 config->tx_cfg[i].f_no_snoop =
7488 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7489 if (config->tx_cfg[i].fifo_len < 65) {
7490 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7491 break;
7492 }
7493 }
7494 /* + 2 because one Txd for skb->data and one Txd for UFO */
7495 config->max_txds = MAX_SKB_FRAGS + 2;
7496
7497 /* Rx side parameters. */
7498 config->rx_ring_num = rx_ring_num;
7499 for (i = 0; i < MAX_RX_RINGS; i++) {
7500 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7501 (rxd_count[sp->rxd_mode] + 1);
7502 config->rx_cfg[i].ring_priority = i;
7503 }
7504
7505 for (i = 0; i < rx_ring_num; i++) {
7506 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7507 config->rx_cfg[i].f_no_snoop =
7508 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7509 }
7510
7511 /* Setting Mac Control parameters */
7512 mac_control->rmac_pause_time = rmac_pause_time;
7513 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7514 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7515
7516
7517 /* Initialize Ring buffer parameters. */
7518 for (i = 0; i < config->rx_ring_num; i++)
7519 atomic_set(&sp->rx_bufs_left[i], 0);
7520
7521 /* initialize the shared memory used by the NIC and the host */
7522 if (init_shared_mem(sp)) {
7523 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7524 dev->name);
7525 ret = -ENOMEM;
7526 goto mem_alloc_failed;
7527 }
7528
7529 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7530 pci_resource_len(pdev, 0));
7531 if (!sp->bar0) {
7532 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7533 dev->name);
7534 ret = -ENOMEM;
7535 goto bar0_remap_failed;
7536 }
7537
7538 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7539 pci_resource_len(pdev, 2));
7540 if (!sp->bar1) {
7541 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7542 dev->name);
7543 ret = -ENOMEM;
7544 goto bar1_remap_failed;
7545 }
7546
7547 dev->irq = pdev->irq;
7548 dev->base_addr = (unsigned long) sp->bar0;
7549
7550 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7551 for (j = 0; j < MAX_TX_FIFOS; j++) {
7552 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7553 (sp->bar1 + (j * 0x00020000));
7554 }
7555
7556 /* Driver entry points */
7557 dev->open = &s2io_open;
7558 dev->stop = &s2io_close;
7559 dev->hard_start_xmit = &s2io_xmit;
7560 dev->get_stats = &s2io_get_stats;
7561 dev->set_multicast_list = &s2io_set_multicast;
7562 dev->do_ioctl = &s2io_ioctl;
7563 dev->set_mac_address = &s2io_set_mac_addr;
7564 dev->change_mtu = &s2io_change_mtu;
7565 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7566 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7567 dev->vlan_rx_register = s2io_vlan_rx_register;
7568
7569 /*
7570 * will use eth_mac_addr() for dev->set_mac_address
7571 * mac address will be set every time dev->open() is called
7572 */
7573 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
7574
7575 #ifdef CONFIG_NET_POLL_CONTROLLER
7576 dev->poll_controller = s2io_netpoll;
7577 #endif
7578
7579 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7580 if (sp->high_dma_flag == TRUE)
7581 dev->features |= NETIF_F_HIGHDMA;
7582 dev->features |= NETIF_F_TSO;
7583 dev->features |= NETIF_F_TSO6;
7584 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7585 dev->features |= NETIF_F_UFO;
7586 dev->features |= NETIF_F_HW_CSUM;
7587 }
7588
7589 dev->tx_timeout = &s2io_tx_watchdog;
7590 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7591 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7592 INIT_WORK(&sp->set_link_task, s2io_set_link);
7593
7594 pci_save_state(sp->pdev);
7595
7596 /* Setting swapper control on the NIC, for proper reset operation */
7597 if (s2io_set_swapper(sp)) {
7598 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7599 dev->name);
7600 ret = -EAGAIN;
7601 goto set_swap_failed;
7602 }
7603
7604 /* Verify if the Herc works on the slot its placed into */
7605 if (sp->device_type & XFRAME_II_DEVICE) {
7606 mode = s2io_verify_pci_mode(sp);
7607 if (mode < 0) {
7608 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7609 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7610 ret = -EBADSLT;
7611 goto set_swap_failed;
7612 }
7613 }
7614
7615 /* Not needed for Herc */
7616 if (sp->device_type & XFRAME_I_DEVICE) {
7617 /*
7618 * Fix for all "FFs" MAC address problems observed on
7619 * Alpha platforms
7620 */
7621 fix_mac_address(sp);
7622 s2io_reset(sp);
7623 }
7624
7625 /*
7626 * MAC address initialization.
7627 * For now only one mac address will be read and used.
7628 */
7629 bar0 = sp->bar0;
7630 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7631 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7632 writeq(val64, &bar0->rmac_addr_cmd_mem);
7633 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7634 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
7635 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7636 mac_down = (u32) tmp64;
7637 mac_up = (u32) (tmp64 >> 32);
7638
7639 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7640 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7641 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7642 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7643 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7644 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7645
7646 /* Set the factory defined MAC address initially */
7647 dev->addr_len = ETH_ALEN;
7648 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7649 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
7650
7651 /* Store the values of the MSIX table in the s2io_nic structure */
7652 store_xmsi_data(sp);
7653 /* reset Nic and bring it to known state */
7654 s2io_reset(sp);
7655
7656 /*
7657 * Initialize the tasklet status and link state flags
7658 * and the card state parameter
7659 */
7660 sp->tasklet_status = 0;
7661 sp->state = 0;
7662
7663 /* Initialize spinlocks */
7664 spin_lock_init(&sp->tx_lock);
7665
7666 if (!napi)
7667 spin_lock_init(&sp->put_lock);
7668 spin_lock_init(&sp->rx_lock);
7669
7670 /*
7671 * SXE-002: Configure link and activity LED to init state
7672 * on driver load.
7673 */
7674 subid = sp->pdev->subsystem_device;
7675 if ((subid & 0xFF) >= 0x07) {
7676 val64 = readq(&bar0->gpio_control);
7677 val64 |= 0x0000800000000000ULL;
7678 writeq(val64, &bar0->gpio_control);
7679 val64 = 0x0411040400000000ULL;
7680 writeq(val64, (void __iomem *) bar0 + 0x2700);
7681 val64 = readq(&bar0->gpio_control);
7682 }
7683
7684 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7685
7686 if (register_netdev(dev)) {
7687 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7688 ret = -ENODEV;
7689 goto register_failed;
7690 }
7691 s2io_vpd_read(sp);
7692 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
7693 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7694 sp->product_name, pdev->revision);
7695 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7696 s2io_driver_version);
7697 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
7698 dev->name, print_mac(mac, dev->dev_addr));
7699 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7700 if (sp->device_type & XFRAME_II_DEVICE) {
7701 mode = s2io_print_pci_mode(sp);
7702 if (mode < 0) {
7703 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7704 ret = -EBADSLT;
7705 unregister_netdev(dev);
7706 goto set_swap_failed;
7707 }
7708 }
7709 switch(sp->rxd_mode) {
7710 case RXD_MODE_1:
7711 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7712 dev->name);
7713 break;
7714 case RXD_MODE_3B:
7715 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7716 dev->name);
7717 break;
7718 }
7719
7720 if (napi)
7721 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7722 switch(sp->config.intr_type) {
7723 case INTA:
7724 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7725 break;
7726 case MSI_X:
7727 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7728 break;
7729 }
7730 if (sp->lro)
7731 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7732 dev->name);
7733 if (ufo)
7734 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7735 " enabled\n", dev->name);
7736 /* Initialize device name */
7737 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7738
7739 /*
7740 * Make Link state as off at this point, when the Link change
7741 * interrupt comes the state will be automatically changed to
7742 * the right state.
7743 */
7744 netif_carrier_off(dev);
7745
7746 return 0;
7747
7748 register_failed:
7749 set_swap_failed:
7750 iounmap(sp->bar1);
7751 bar1_remap_failed:
7752 iounmap(sp->bar0);
7753 bar0_remap_failed:
7754 mem_alloc_failed:
7755 free_shared_mem(sp);
7756 pci_disable_device(pdev);
7757 pci_release_regions(pdev);
7758 pci_set_drvdata(pdev, NULL);
7759 free_netdev(dev);
7760
7761 return ret;
7762 }
7763
7764 /**
7765 * s2io_rem_nic - Free the PCI device
7766 * @pdev: structure containing the PCI related information of the device.
7767 * Description: This function is called by the Pci subsystem to release a
7768 * PCI device and free up all resource held up by the device. This could
7769 * be in response to a Hot plug event or when the driver is to be removed
7770 * from memory.
7771 */
7772
7773 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7774 {
7775 struct net_device *dev =
7776 (struct net_device *) pci_get_drvdata(pdev);
7777 struct s2io_nic *sp;
7778
7779 if (dev == NULL) {
7780 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7781 return;
7782 }
7783
7784 flush_scheduled_work();
7785
7786 sp = dev->priv;
7787 unregister_netdev(dev);
7788
7789 free_shared_mem(sp);
7790 iounmap(sp->bar0);
7791 iounmap(sp->bar1);
7792 pci_release_regions(pdev);
7793 pci_set_drvdata(pdev, NULL);
7794 free_netdev(dev);
7795 pci_disable_device(pdev);
7796 }
7797
7798 /**
7799 * s2io_starter - Entry point for the driver
7800 * Description: This function is the entry point for the driver. It verifies
7801 * the module loadable parameters and initializes PCI configuration space.
7802 */
7803
7804 static int __init s2io_starter(void)
7805 {
7806 return pci_register_driver(&s2io_driver);
7807 }
7808
7809 /**
7810 * s2io_closer - Cleanup routine for the driver
7811 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7812 */
7813
7814 static __exit void s2io_closer(void)
7815 {
7816 pci_unregister_driver(&s2io_driver);
7817 DBG_PRINT(INIT_DBG, "cleanup done\n");
7818 }
7819
7820 module_init(s2io_starter);
7821 module_exit(s2io_closer);
7822
7823 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7824 struct tcphdr **tcp, struct RxD_t *rxdp)
7825 {
7826 int ip_off;
7827 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7828
7829 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7830 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7831 __FUNCTION__);
7832 return -1;
7833 }
7834
7835 /* TODO:
7836 * By default the VLAN field in the MAC is stripped by the card, if this
7837 * feature is turned off in rx_pa_cfg register, then the ip_off field
7838 * has to be shifted by a further 2 bytes
7839 */
7840 switch (l2_type) {
7841 case 0: /* DIX type */
7842 case 4: /* DIX type with VLAN */
7843 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7844 break;
7845 /* LLC, SNAP etc are considered non-mergeable */
7846 default:
7847 return -1;
7848 }
7849
7850 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7851 ip_len = (u8)((*ip)->ihl);
7852 ip_len <<= 2;
7853 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7854
7855 return 0;
7856 }
7857
7858 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7859 struct tcphdr *tcp)
7860 {
7861 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7862 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7863 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7864 return -1;
7865 return 0;
7866 }
7867
7868 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7869 {
7870 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7871 }
7872
7873 static void initiate_new_session(struct lro *lro, u8 *l2h,
7874 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7875 {
7876 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7877 lro->l2h = l2h;
7878 lro->iph = ip;
7879 lro->tcph = tcp;
7880 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7881 lro->tcp_ack = ntohl(tcp->ack_seq);
7882 lro->sg_num = 1;
7883 lro->total_len = ntohs(ip->tot_len);
7884 lro->frags_len = 0;
7885 /*
7886 * check if we saw TCP timestamp. Other consistency checks have
7887 * already been done.
7888 */
7889 if (tcp->doff == 8) {
7890 u32 *ptr;
7891 ptr = (u32 *)(tcp+1);
7892 lro->saw_ts = 1;
7893 lro->cur_tsval = *(ptr+1);
7894 lro->cur_tsecr = *(ptr+2);
7895 }
7896 lro->in_use = 1;
7897 }
7898
7899 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7900 {
7901 struct iphdr *ip = lro->iph;
7902 struct tcphdr *tcp = lro->tcph;
7903 __sum16 nchk;
7904 struct stat_block *statinfo = sp->mac_control.stats_info;
7905 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7906
7907 /* Update L3 header */
7908 ip->tot_len = htons(lro->total_len);
7909 ip->check = 0;
7910 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7911 ip->check = nchk;
7912
7913 /* Update L4 header */
7914 tcp->ack_seq = lro->tcp_ack;
7915 tcp->window = lro->window;
7916
7917 /* Update tsecr field if this session has timestamps enabled */
7918 if (lro->saw_ts) {
7919 u32 *ptr = (u32 *)(tcp + 1);
7920 *(ptr+2) = lro->cur_tsecr;
7921 }
7922
7923 /* Update counters required for calculation of
7924 * average no. of packets aggregated.
7925 */
7926 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7927 statinfo->sw_stat.num_aggregations++;
7928 }
7929
7930 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7931 struct tcphdr *tcp, u32 l4_pyld)
7932 {
7933 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7934 lro->total_len += l4_pyld;
7935 lro->frags_len += l4_pyld;
7936 lro->tcp_next_seq += l4_pyld;
7937 lro->sg_num++;
7938
7939 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7940 lro->tcp_ack = tcp->ack_seq;
7941 lro->window = tcp->window;
7942
7943 if (lro->saw_ts) {
7944 u32 *ptr;
7945 /* Update tsecr and tsval from this packet */
7946 ptr = (u32 *) (tcp + 1);
7947 lro->cur_tsval = *(ptr + 1);
7948 lro->cur_tsecr = *(ptr + 2);
7949 }
7950 }
7951
7952 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7953 struct tcphdr *tcp, u32 tcp_pyld_len)
7954 {
7955 u8 *ptr;
7956
7957 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7958
7959 if (!tcp_pyld_len) {
7960 /* Runt frame or a pure ack */
7961 return -1;
7962 }
7963
7964 if (ip->ihl != 5) /* IP has options */
7965 return -1;
7966
7967 /* If we see CE codepoint in IP header, packet is not mergeable */
7968 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7969 return -1;
7970
7971 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7972 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7973 tcp->ece || tcp->cwr || !tcp->ack) {
7974 /*
7975 * Currently recognize only the ack control word and
7976 * any other control field being set would result in
7977 * flushing the LRO session
7978 */
7979 return -1;
7980 }
7981
7982 /*
7983 * Allow only one TCP timestamp option. Don't aggregate if
7984 * any other options are detected.
7985 */
7986 if (tcp->doff != 5 && tcp->doff != 8)
7987 return -1;
7988
7989 if (tcp->doff == 8) {
7990 ptr = (u8 *)(tcp + 1);
7991 while (*ptr == TCPOPT_NOP)
7992 ptr++;
7993 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7994 return -1;
7995
7996 /* Ensure timestamp value increases monotonically */
7997 if (l_lro)
7998 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7999 return -1;
8000
8001 /* timestamp echo reply should be non-zero */
8002 if (*((u32 *)(ptr+6)) == 0)
8003 return -1;
8004 }
8005
8006 return 0;
8007 }
8008
8009 static int
8010 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8011 struct RxD_t *rxdp, struct s2io_nic *sp)
8012 {
8013 struct iphdr *ip;
8014 struct tcphdr *tcph;
8015 int ret = 0, i;
8016
8017 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8018 rxdp))) {
8019 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8020 ip->saddr, ip->daddr);
8021 } else {
8022 return ret;
8023 }
8024
8025 tcph = (struct tcphdr *)*tcp;
8026 *tcp_len = get_l4_pyld_length(ip, tcph);
8027 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8028 struct lro *l_lro = &sp->lro0_n[i];
8029 if (l_lro->in_use) {
8030 if (check_for_socket_match(l_lro, ip, tcph))
8031 continue;
8032 /* Sock pair matched */
8033 *lro = l_lro;
8034
8035 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8036 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8037 "0x%x, actual 0x%x\n", __FUNCTION__,
8038 (*lro)->tcp_next_seq,
8039 ntohl(tcph->seq));
8040
8041 sp->mac_control.stats_info->
8042 sw_stat.outof_sequence_pkts++;
8043 ret = 2;
8044 break;
8045 }
8046
8047 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8048 ret = 1; /* Aggregate */
8049 else
8050 ret = 2; /* Flush both */
8051 break;
8052 }
8053 }
8054
8055 if (ret == 0) {
8056 /* Before searching for available LRO objects,
8057 * check if the pkt is L3/L4 aggregatable. If not
8058 * don't create new LRO session. Just send this
8059 * packet up.
8060 */
8061 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8062 return 5;
8063 }
8064
8065 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8066 struct lro *l_lro = &sp->lro0_n[i];
8067 if (!(l_lro->in_use)) {
8068 *lro = l_lro;
8069 ret = 3; /* Begin anew */
8070 break;
8071 }
8072 }
8073 }
8074
8075 if (ret == 0) { /* sessions exceeded */
8076 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8077 __FUNCTION__);
8078 *lro = NULL;
8079 return ret;
8080 }
8081
8082 switch (ret) {
8083 case 3:
8084 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
8085 break;
8086 case 2:
8087 update_L3L4_header(sp, *lro);
8088 break;
8089 case 1:
8090 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8091 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8092 update_L3L4_header(sp, *lro);
8093 ret = 4; /* Flush the LRO */
8094 }
8095 break;
8096 default:
8097 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8098 __FUNCTION__);
8099 break;
8100 }
8101
8102 return ret;
8103 }
8104
8105 static void clear_lro_session(struct lro *lro)
8106 {
8107 static u16 lro_struct_size = sizeof(struct lro);
8108
8109 memset(lro, 0, lro_struct_size);
8110 }
8111
8112 static void queue_rx_frame(struct sk_buff *skb)
8113 {
8114 struct net_device *dev = skb->dev;
8115
8116 skb->protocol = eth_type_trans(skb, dev);
8117 if (napi)
8118 netif_receive_skb(skb);
8119 else
8120 netif_rx(skb);
8121 }
8122
8123 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8124 struct sk_buff *skb,
8125 u32 tcp_len)
8126 {
8127 struct sk_buff *first = lro->parent;
8128
8129 first->len += tcp_len;
8130 first->data_len = lro->frags_len;
8131 skb_pull(skb, (skb->len - tcp_len));
8132 if (skb_shinfo(first)->frag_list)
8133 lro->last_frag->next = skb;
8134 else
8135 skb_shinfo(first)->frag_list = skb;
8136 first->truesize += skb->truesize;
8137 lro->last_frag = skb;
8138 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8139 return;
8140 }
8141
8142 /**
8143 * s2io_io_error_detected - called when PCI error is detected
8144 * @pdev: Pointer to PCI device
8145 * @state: The current pci connection state
8146 *
8147 * This function is called after a PCI bus error affecting
8148 * this device has been detected.
8149 */
8150 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8151 pci_channel_state_t state)
8152 {
8153 struct net_device *netdev = pci_get_drvdata(pdev);
8154 struct s2io_nic *sp = netdev->priv;
8155
8156 netif_device_detach(netdev);
8157
8158 if (netif_running(netdev)) {
8159 /* Bring down the card, while avoiding PCI I/O */
8160 do_s2io_card_down(sp, 0);
8161 }
8162 pci_disable_device(pdev);
8163
8164 return PCI_ERS_RESULT_NEED_RESET;
8165 }
8166
8167 /**
8168 * s2io_io_slot_reset - called after the pci bus has been reset.
8169 * @pdev: Pointer to PCI device
8170 *
8171 * Restart the card from scratch, as if from a cold-boot.
8172 * At this point, the card has exprienced a hard reset,
8173 * followed by fixups by BIOS, and has its config space
8174 * set up identically to what it was at cold boot.
8175 */
8176 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8177 {
8178 struct net_device *netdev = pci_get_drvdata(pdev);
8179 struct s2io_nic *sp = netdev->priv;
8180
8181 if (pci_enable_device(pdev)) {
8182 printk(KERN_ERR "s2io: "
8183 "Cannot re-enable PCI device after reset.\n");
8184 return PCI_ERS_RESULT_DISCONNECT;
8185 }
8186
8187 pci_set_master(pdev);
8188 s2io_reset(sp);
8189
8190 return PCI_ERS_RESULT_RECOVERED;
8191 }
8192
8193 /**
8194 * s2io_io_resume - called when traffic can start flowing again.
8195 * @pdev: Pointer to PCI device
8196 *
8197 * This callback is called when the error recovery driver tells
8198 * us that its OK to resume normal operation.
8199 */
8200 static void s2io_io_resume(struct pci_dev *pdev)
8201 {
8202 struct net_device *netdev = pci_get_drvdata(pdev);
8203 struct s2io_nic *sp = netdev->priv;
8204
8205 if (netif_running(netdev)) {
8206 if (s2io_card_up(sp)) {
8207 printk(KERN_ERR "s2io: "
8208 "Can't bring device back up after reset.\n");
8209 return;
8210 }
8211
8212 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8213 s2io_card_down(sp);
8214 printk(KERN_ERR "s2io: "
8215 "Can't resetore mac addr after reset.\n");
8216 return;
8217 }
8218 }
8219
8220 netif_device_attach(netdev);
8221 netif_wake_queue(netdev);
8222 }
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