drivers/net/wireless/iwlwifi/iwl-4965-hw.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU Geeral Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63
  64 #ifndef __iwl_4965_hw_h__
  65 #define __iwl_4965_hw_h__
  66
  67 #define IWL_RX_BUF_SIZE (4 * 1024)
  68 #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
  69 #define KDR_RTC_INST_UPPER_BOUND                (0x018000)
  70 #define KDR_RTC_DATA_UPPER_BOUND                (0x80A000)
  71 #define KDR_RTC_INST_SIZE    (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
  72 #define KDR_RTC_DATA_SIZE    (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
  73
  74 #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE
  75 #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE
  76
  77 static inline int iwl_hw_valid_rtc_data_addr(u32 addr)
  78 {
  79         return (addr >= RTC_DATA_LOWER_BOUND) &&
  80                (addr < KDR_RTC_DATA_UPPER_BOUND);
  81 }
  82
  83 /********************* START TXPOWER *****************************************/
  84 enum {
  85         HT_IE_EXT_CHANNEL_NONE = 0,
  86         HT_IE_EXT_CHANNEL_ABOVE,
  87         HT_IE_EXT_CHANNEL_INVALID,
  88         HT_IE_EXT_CHANNEL_BELOW,
  89         HT_IE_EXT_CHANNEL_MAX
  90 };
  91
  92 enum {
  93         CALIB_CH_GROUP_1 = 0,
  94         CALIB_CH_GROUP_2 = 1,
  95         CALIB_CH_GROUP_3 = 2,
  96         CALIB_CH_GROUP_4 = 3,
  97         CALIB_CH_GROUP_5 = 4,
  98         CALIB_CH_GROUP_MAX
  99 };
 100
 101 /* Temperature calibration offset is 3% 0C in Kelvin */
 102 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
 103 #define TEMPERATURE_CALIB_A_VAL 259
 104
 105 #define IWL_TX_POWER_TEMPERATURE_MIN  (263)
 106 #define IWL_TX_POWER_TEMPERATURE_MAX  (410)
 107
 108 #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
 109         (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
 110          ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
 111
 112 #define IWL_TX_POWER_ILLEGAL_TEMPERATURE (300)
 113
 114 #define IWL_TX_POWER_TEMPERATURE_DIFFERENCE (2)
 115
 116 #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
 117
 118 #define IWL_TX_POWER_TARGET_POWER_MIN       (0) /* 0 dBm = 1 milliwatt */
 119 #define IWL_TX_POWER_TARGET_POWER_MAX      (16) /* 16 dBm */
 120
 121 /* timeout equivalent to 3 minutes */
 122 #define IWL_TX_POWER_TIMELIMIT_NOCALIB 1800000000
 123
 124 #define IWL_TX_POWER_CCK_COMPENSATION (9)
 125
 126 #define MIN_TX_GAIN_INDEX               (0)
 127 #define MIN_TX_GAIN_INDEX_52GHZ_EXT     (-9)
 128 #define MAX_TX_GAIN_INDEX_52GHZ         (98)
 129 #define MIN_TX_GAIN_52GHZ               (98)
 130 #define MAX_TX_GAIN_INDEX_24GHZ         (98)
 131 #define MIN_TX_GAIN_24GHZ               (98)
 132 #define MAX_TX_GAIN                     (0)
 133 #define MAX_TX_GAIN_52GHZ_EXT           (-9)
 134
 135 #define IWL_TX_POWER_DEFAULT_REGULATORY_24   (34)
 136 #define IWL_TX_POWER_DEFAULT_REGULATORY_52   (34)
 137 #define IWL_TX_POWER_REGULATORY_MIN          (0)
 138 #define IWL_TX_POWER_REGULATORY_MAX          (34)
 139 #define IWL_TX_POWER_DEFAULT_SATURATION_24   (38)
 140 #define IWL_TX_POWER_DEFAULT_SATURATION_52   (38)
 141 #define IWL_TX_POWER_SATURATION_MIN          (20)
 142 #define IWL_TX_POWER_SATURATION_MAX          (50)
 143
 144 /* dv *0.4 = dt; so that 5 degrees temperature diff equals
 145  * 12.5 in voltage diff */
 146 #define IWL_TX_TEMPERATURE_UPDATE_LIMIT 9
 147
 148 #define IWL_INVALID_CHANNEL                 (0xffffffff)
 149 #define IWL_TX_POWER_REGITRY_BIT            (2)
 150
 151 #define MIN_IWL_TX_POWER_CALIB_DUR          (100)
 152 #define IWL_CCK_FROM_OFDM_POWER_DIFF        (-5)
 153 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (9)
 154
 155 /* Number of entries in the gain table */
 156 #define POWER_GAIN_NUM_ENTRIES 78
 157 #define TX_POW_MAX_SESSION_NUM 5
 158 /*  timeout equivalent to 3 minutes */
 159 #define TX_IWL_TIMELIMIT_NOCALIB 1800000000
 160
 161 /* Kedron TX_CALIB_STATES */
 162 #define IWL_TX_CALIB_STATE_SEND_TX        0x00000001
 163 #define IWL_TX_CALIB_WAIT_TX_RESPONSE     0x00000002
 164 #define IWL_TX_CALIB_ENABLED              0x00000004
 165 #define IWL_TX_CALIB_XVT_ON               0x00000008
 166 #define IWL_TX_CALIB_TEMPERATURE_CORRECT  0x00000010
 167 #define IWL_TX_CALIB_WORKING_WITH_XVT     0x00000020
 168 #define IWL_TX_CALIB_XVT_PERIODICAL       0x00000040
 169
 170 #define NUM_IWL_TX_CALIB_SETTINS 5      /* Number of tx correction groups */
 171
 172 #define IWL_MIN_POWER_IN_VP_TABLE 1     /* 0.5dBm multiplied by 2 */
 173 #define IWL_MAX_POWER_IN_VP_TABLE 40    /* 20dBm - multiplied by 2 (because
 174                                          * entries are for each 0.5dBm) */
 175 #define IWL_STEP_IN_VP_TABLE 1  /* 0.5dB - multiplied by 2 */
 176 #define IWL_NUM_POINTS_IN_VPTABLE \
 177         (1 + IWL_MAX_POWER_IN_VP_TABLE - IWL_MIN_POWER_IN_VP_TABLE)
 178
 179 #define MIN_TX_GAIN_INDEX         (0)
 180 #define MAX_TX_GAIN_INDEX_52GHZ   (98)
 181 #define MIN_TX_GAIN_52GHZ         (98)
 182 #define MAX_TX_GAIN_INDEX_24GHZ   (98)
 183 #define MIN_TX_GAIN_24GHZ         (98)
 184 #define MAX_TX_GAIN               (0)
 185
 186 /* First and last channels of all groups */
 187 #define CALIB_IWL_TX_ATTEN_GR1_FCH 34
 188 #define CALIB_IWL_TX_ATTEN_GR1_LCH 43
 189 #define CALIB_IWL_TX_ATTEN_GR2_FCH 44
 190 #define CALIB_IWL_TX_ATTEN_GR2_LCH 70
 191 #define CALIB_IWL_TX_ATTEN_GR3_FCH 71
 192 #define CALIB_IWL_TX_ATTEN_GR3_LCH 124
 193 #define CALIB_IWL_TX_ATTEN_GR4_FCH 125
 194 #define CALIB_IWL_TX_ATTEN_GR4_LCH 200
 195 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
 196 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
 197
 198
 199 union iwl_tx_power_dual_stream {
 200         struct {
 201                 u8 radio_tx_gain[2];
 202                 u8 dsp_predis_atten[2];
 203         } s;
 204         u32 dw;
 205 };
 206
 207 /********************* END TXPOWER *****************************************/
 208
 209 /* HT flags */
 210 #define RXON_FLG_CTRL_CHANNEL_LOC_POS           (22)
 211 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK        __constant_cpu_to_le32(0x1<<22)
 212
 213 #define RXON_FLG_HT_OPERATING_MODE_POS          (23)
 214
 215 #define RXON_FLG_HT_PROT_MSK                    __constant_cpu_to_le32(0x1<<23)
 216 #define RXON_FLG_FAT_PROT_MSK                   __constant_cpu_to_le32(0x2<<23)
 217
 218 #define RXON_FLG_CHANNEL_MODE_POS               (25)
 219 #define RXON_FLG_CHANNEL_MODE_MSK               __constant_cpu_to_le32(0x3<<25)
 220 #define RXON_FLG_CHANNEL_MODE_PURE_40_MSK       __constant_cpu_to_le32(0x1<<25)
 221 #define RXON_FLG_CHANNEL_MODE_MIXED_MSK         __constant_cpu_to_le32(0x2<<25)
 222
 223 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK          __constant_cpu_to_le16(0x1<<0)
 224 #define RXON_RX_CHAIN_VALID_MSK                 __constant_cpu_to_le16(0x7<<1)
 225 #define RXON_RX_CHAIN_VALID_POS                 (1)
 226 #define RXON_RX_CHAIN_FORCE_SEL_MSK             __constant_cpu_to_le16(0x7<<4)
 227 #define RXON_RX_CHAIN_FORCE_SEL_POS             (4)
 228 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK        __constant_cpu_to_le16(0x7<<7)
 229 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS        (7)
 230 #define RXON_RX_CHAIN_CNT_MSK                   __constant_cpu_to_le16(0x3<<10)
 231 #define RXON_RX_CHAIN_CNT_POS                   (10)
 232 #define RXON_RX_CHAIN_MIMO_CNT_MSK              __constant_cpu_to_le16(0x3<<12)
 233 #define RXON_RX_CHAIN_MIMO_CNT_POS              (12)
 234 #define RXON_RX_CHAIN_MIMO_FORCE_MSK            __constant_cpu_to_le16(0x1<<14)
 235 #define RXON_RX_CHAIN_MIMO_FORCE_POS            (14)
 236
 237
 238 #define MCS_DUP_6M_PLCP 0x20
 239
 240 /* OFDM HT rate masks */
 241 /* ***************************************** */
 242 #define R_MCS_6M_MSK 0x1
 243 #define R_MCS_12M_MSK 0x2
 244 #define R_MCS_18M_MSK 0x4
 245 #define R_MCS_24M_MSK 0x8
 246 #define R_MCS_36M_MSK 0x10
 247 #define R_MCS_48M_MSK 0x20
 248 #define R_MCS_54M_MSK 0x40
 249 #define R_MCS_60M_MSK 0x80
 250 #define R_MCS_12M_DUAL_MSK 0x100
 251 #define R_MCS_24M_DUAL_MSK 0x200
 252 #define R_MCS_36M_DUAL_MSK 0x400
 253 #define R_MCS_48M_DUAL_MSK 0x800
 254
 255 #define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A))
 256 #define is_siso(tbl) (((tbl) == LQ_SISO))
 257 #define is_mimo(tbl) (((tbl) == LQ_MIMO))
 258 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
 259 #define is_a_band(tbl) (((tbl) == LQ_A))
 260 #define is_g_and(tbl) (((tbl) == LQ_G))
 261
 262 /* Flow Handler Definitions */
 263
 264 /**********************/
 265 /*     Addresses      */
 266 /**********************/
 267
 268 #define FH_MEM_LOWER_BOUND                   (0x1000)
 269 #define FH_MEM_UPPER_BOUND                   (0x1EF0)
 270
 271 #define IWL_FH_REGS_LOWER_BOUND              (0x1000)
 272 #define IWL_FH_REGS_UPPER_BOUND              (0x2000)
 273
 274 #define IWL_FH_KW_MEM_ADDR_REG               (FH_MEM_LOWER_BOUND + 0x97C)
 275
 276 /* CBBC Area - Circular buffers base address cache pointers table */
 277 #define FH_MEM_CBBC_LOWER_BOUND              (FH_MEM_LOWER_BOUND + 0x9D0)
 278 #define FH_MEM_CBBC_UPPER_BOUND              (FH_MEM_LOWER_BOUND + 0xA10)
 279 /* queues 0 - 15 */
 280 #define FH_MEM_CBBC_QUEUE(x)  (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
 281
 282 /* RSCSR Area */
 283 #define FH_MEM_RSCSR_LOWER_BOUND        (FH_MEM_LOWER_BOUND + 0xBC0)
 284 #define FH_MEM_RSCSR_UPPER_BOUND        (FH_MEM_LOWER_BOUND + 0xC00)
 285 #define FH_MEM_RSCSR_CHNL0              (FH_MEM_RSCSR_LOWER_BOUND)
 286
 287 #define FH_RSCSR_CHNL0_STTS_WPTR_REG            (FH_MEM_RSCSR_CHNL0)
 288 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG           (FH_MEM_RSCSR_CHNL0 + 0x004)
 289 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG           (FH_MEM_RSCSR_CHNL0 + 0x008)
 290
 291 /* RCSR Area - Registers address map */
 292 #define FH_MEM_RCSR_LOWER_BOUND      (FH_MEM_LOWER_BOUND + 0xC00)
 293 #define FH_MEM_RCSR_UPPER_BOUND      (FH_MEM_LOWER_BOUND + 0xCC0)
 294 #define FH_MEM_RCSR_CHNL0            (FH_MEM_RCSR_LOWER_BOUND)
 295
 296 #define FH_MEM_RCSR_CHNL0_CONFIG_REG    (FH_MEM_RCSR_CHNL0)
 297
 298 /* RSSR Area - Rx shared ctrl & status registers */
 299 #define FH_MEM_RSSR_LOWER_BOUND                 (FH_MEM_LOWER_BOUND + 0xC40)
 300 #define FH_MEM_RSSR_UPPER_BOUND                 (FH_MEM_LOWER_BOUND + 0xD00)
 301 #define FH_MEM_RSSR_SHARED_CTRL_REG             (FH_MEM_RSSR_LOWER_BOUND)
 302 #define FH_MEM_RSSR_RX_STATUS_REG       (FH_MEM_RSSR_LOWER_BOUND + 0x004)
 303 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV  (FH_MEM_RSSR_LOWER_BOUND + 0x008)
 304
 305 /* TCSR */
 306 #define IWL_FH_TCSR_LOWER_BOUND  (IWL_FH_REGS_LOWER_BOUND + 0xD00)
 307 #define IWL_FH_TCSR_UPPER_BOUND  (IWL_FH_REGS_LOWER_BOUND + 0xE60)
 308
 309 #define IWL_FH_TCSR_CHNL_NUM                            (7)
 310 #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
 311         (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
 312
 313 /* TSSR Area - Tx shared status registers */
 314 /* TSSR */
 315 #define IWL_FH_TSSR_LOWER_BOUND         (IWL_FH_REGS_LOWER_BOUND + 0xEA0)
 316 #define IWL_FH_TSSR_UPPER_BOUND         (IWL_FH_REGS_LOWER_BOUND + 0xEC0)
 317
 318 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG   (IWL_FH_TSSR_LOWER_BOUND + 0x008)
 319 #define IWL_FH_TSSR_TX_STATUS_REG       (IWL_FH_TSSR_LOWER_BOUND + 0x010)
 320
 321 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON      (0xFF000000)
 322 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON      (0x00FF0000)
 323
 324 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B     (0x00000000)
 325 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B    (0x00000400)
 326 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B    (0x00000800)
 327 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B    (0x00000C00)
 328
 329 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON       (0x00000100)
 330 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON       (0x00000080)
 331
 332 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH     (0x00000020)
 333 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH           (0x00000005)
 334
 335 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
 336         ((1 << (_chnl)) << 24)
 337 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
 338         ((1 << (_chnl)) << 16)
 339
 340 #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
 341         (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
 342         IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
 343
 344 /* TCSR: tx_config register values */
 345 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF              (0x00000000)
 346 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER           (0x00000001)
 347 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC              (0x00000002)
 348
 349 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL    (0x00000000)
 350 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL     (0x00000008)
 351
 352 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT           (0x00000000)
 353 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD          (0x00100000)
 354 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD           (0x00200000)
 355
 356 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT            (0x00000000)
 357 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD           (0x00400000)
 358 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD            (0x00800000)
 359
 360 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE            (0x00000000)
 361 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF        (0x40000000)
 362 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE           (0x80000000)
 363
 364 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY          (0x00000000)
 365 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT           (0x00002000)
 366 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID          (0x00000003)
 367
 368 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR           (0x00000001)
 369
 370 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM              (20)
 371 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX              (12)
 372
 373 /* RCSR:  channel 0 rx_config register defines */
 374 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK  (0xC0000000) /* bits 30-31 */
 375 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK   (0x00F00000) /* bits 20-23 */
 376 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK      (0x00030000) /* bits 16-17 */
 377 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
 378 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK     (0x00001000) /* bit 12 */
 379 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK   (0x00000FF0) /* bit 4-11 */
 380
 381 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT       (20)
 382 #define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT                      (16)
 383
 384 /* RCSR: rx_config register values */
 385 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL         (0x00000000)
 386 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL     (0x40000000)
 387 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL        (0x80000000)
 388
 389 #define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K    (0x00000000)
 390
 391 /* RCSR channel 0 config register values */
 392 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL       (0x00000000)
 393 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL     (0x00001000)
 394
 395 /* RSCSR: defs used in normal mode */
 396 #define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK          (0x00000FFF)    /* bits 0-11 */
 397
 398 #define SCD_WIN_SIZE                            64
 399 #define SCD_FRAME_LIMIT                         64
 400
 401 /* memory mapped registers */
 402 #define SCD_START_OFFSET                0xa02c00
 403
 404 #define SCD_SRAM_BASE_ADDR           (SCD_START_OFFSET + 0x0)
 405 #define SCD_EMPTY_BITS               (SCD_START_OFFSET + 0x4)
 406 #define SCD_DRAM_BASE_ADDR           (SCD_START_OFFSET + 0x10)
 407 #define SCD_AIT                      (SCD_START_OFFSET + 0x18)
 408 #define SCD_TXFACT                   (SCD_START_OFFSET + 0x1c)
 409 #define SCD_QUEUE_WRPTR(x)           (SCD_START_OFFSET + 0x24 + (x) * 4)
 410 #define SCD_QUEUE_RDPTR(x)           (SCD_START_OFFSET + 0x64 + (x) * 4)
 411 #define SCD_SETQUEUENUM              (SCD_START_OFFSET + 0xa4)
 412 #define SCD_SET_TXSTAT_TXED          (SCD_START_OFFSET + 0xa8)
 413 #define SCD_SET_TXSTAT_DONE          (SCD_START_OFFSET + 0xac)
 414 #define SCD_SET_TXSTAT_NOT_SCHD      (SCD_START_OFFSET + 0xb0)
 415 #define SCD_DECREASE_CREDIT          (SCD_START_OFFSET + 0xb4)
 416 #define SCD_DECREASE_SCREDIT         (SCD_START_OFFSET + 0xb8)
 417 #define SCD_LOAD_CREDIT              (SCD_START_OFFSET + 0xbc)
 418 #define SCD_LOAD_SCREDIT             (SCD_START_OFFSET + 0xc0)
 419 #define SCD_BAR                      (SCD_START_OFFSET + 0xc4)
 420 #define SCD_BAR_DW0                  (SCD_START_OFFSET + 0xc8)
 421 #define SCD_BAR_DW1                  (SCD_START_OFFSET + 0xcc)
 422 #define SCD_QUEUECHAIN_SEL           (SCD_START_OFFSET + 0xd0)
 423 #define SCD_QUERY_REQ                (SCD_START_OFFSET + 0xd8)
 424 #define SCD_QUERY_RES                (SCD_START_OFFSET + 0xdc)
 425 #define SCD_PENDING_FRAMES           (SCD_START_OFFSET + 0xe0)
 426 #define SCD_INTERRUPT_MASK           (SCD_START_OFFSET + 0xe4)
 427 #define SCD_INTERRUPT_THRESHOLD      (SCD_START_OFFSET + 0xe8)
 428 #define SCD_QUERY_MIN_FRAME_SIZE     (SCD_START_OFFSET + 0x100)
 429 #define SCD_QUEUE_STATUS_BITS(x)     (SCD_START_OFFSET + 0x104 + (x) * 4)
 430
 431 /* SRAM structures */
 432 #define SCD_CONTEXT_DATA_OFFSET                 0x380
 433 #define SCD_TX_STTS_BITMAP_OFFSET               0x400
 434 #define SCD_TRANSLATE_TBL_OFFSET                0x500
 435 #define SCD_CONTEXT_QUEUE_OFFSET(x)     (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
 436 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
 437         ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
 438
 439 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
 440        ((1<<(hi))|((1<<(hi))-(1<<(lo))))
 441
 442
 443 #define SCD_MODE_REG_BIT_SEARCH_MODE            (1<<0)
 444 #define SCD_MODE_REG_BIT_SBYP_MODE              (1<<1)
 445
 446 #define SCD_TXFIFO_POS_TID                      (0)
 447 #define SCD_TXFIFO_POS_RA                       (4)
 448 #define SCD_QUEUE_STTS_REG_POS_ACTIVE           (0)
 449 #define SCD_QUEUE_STTS_REG_POS_TXF              (1)
 450 #define SCD_QUEUE_STTS_REG_POS_WSL              (5)
 451 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK          (8)
 452 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN       (10)
 453 #define SCD_QUEUE_STTS_REG_MSK                  (0x0007FC00)
 454
 455 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK          (0x01FF)
 456
 457 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS         (0)
 458 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK         (0x0000007F)
 459 #define SCD_QUEUE_CTX_REG1_CREDIT_POS           (8)
 460 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK           (0x00FFFF00)
 461 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS     (24)
 462 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK     (0xFF000000)
 463 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS      (16)
 464 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK      (0x007F0000)
 465
 466 #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R       (0x00000010)
 467 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x00000C00)
 468 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 469 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 470
 471 static inline u8 iwl_hw_get_rate(__le32 rate_n_flags)
 472 {
 473         return le32_to_cpu(rate_n_flags) & 0xFF;
 474 }
 475 static inline u16 iwl_hw_get_rate_n_flags(__le32 rate_n_flags)
 476 {
 477         return le32_to_cpu(rate_n_flags) & 0xFFFF;
 478 }
 479 static inline __le32 iwl_hw_set_rate_n_flags(u8 rate, u16 flags)
 480 {
 481         return cpu_to_le32(flags|(u16)rate);
 482 }
 483
 484 struct iwl_tfd_frame_data {
 485         __le32 tb1_addr;
 486
 487         __le32 val1;
 488         /* __le32 ptb1_32_35:4; */
 489 #define IWL_tb1_addr_hi_POS 0
 490 #define IWL_tb1_addr_hi_LEN 4
 491 #define IWL_tb1_addr_hi_SYM val1
 492         /* __le32 tb_len1:12; */
 493 #define IWL_tb1_len_POS 4
 494 #define IWL_tb1_len_LEN 12
 495 #define IWL_tb1_len_SYM val1
 496         /* __le32 ptb2_0_15:16; */
 497 #define IWL_tb2_addr_lo16_POS 16
 498 #define IWL_tb2_addr_lo16_LEN 16
 499 #define IWL_tb2_addr_lo16_SYM val1
 500
 501         __le32 val2;
 502         /* __le32 ptb2_16_35:20; */
 503 #define IWL_tb2_addr_hi20_POS 0
 504 #define IWL_tb2_addr_hi20_LEN 20
 505 #define IWL_tb2_addr_hi20_SYM val2
 506         /* __le32 tb_len2:12; */
 507 #define IWL_tb2_len_POS 20
 508 #define IWL_tb2_len_LEN 12
 509 #define IWL_tb2_len_SYM val2
 510 } __attribute__ ((packed));
 511
 512 struct iwl_tfd_frame {
 513         __le32 val0;
 514         /* __le32 rsvd1:24; */
 515         /* __le32 num_tbs:5; */
 516 #define IWL_num_tbs_POS 24
 517 #define IWL_num_tbs_LEN 5
 518 #define IWL_num_tbs_SYM val0
 519         /* __le32 rsvd2:1; */
 520         /* __le32 padding:2; */
 521         struct iwl_tfd_frame_data pa[10];
 522         __le32 reserved;
 523 } __attribute__ ((packed));
 524
 525 #define IWL4965_MAX_WIN_SIZE              64
 526 #define IWL4965_QUEUE_SIZE               256
 527 #define IWL4965_NUM_FIFOS                  7
 528 #define IWL_MAX_NUM_QUEUES                16
 529
 530 struct iwl4965_queue_byte_cnt_entry {
 531         __le16 val;
 532         /* __le16 byte_cnt:12; */
 533 #define IWL_byte_cnt_POS 0
 534 #define IWL_byte_cnt_LEN 12
 535 #define IWL_byte_cnt_SYM val
 536         /* __le16 rsvd:4; */
 537 } __attribute__ ((packed));
 538
 539 struct iwl4965_sched_queue_byte_cnt_tbl {
 540         struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE +
 541                                                        IWL4965_MAX_WIN_SIZE];
 542         u8 dont_care[1024 -
 543                      (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) *
 544                      sizeof(__le16)];
 545 } __attribute__ ((packed));
 546
 547 /* Base physical address of iwl_shared is provided to SCD_DRAM_BASE_ADDR
 548  * and &iwl_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */
 549 struct iwl_shared {
 550         struct iwl4965_sched_queue_byte_cnt_tbl
 551          queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES];
 552         __le32 val0;
 553
 554         /* __le32 rb_closed_stts_rb_num:12; */
 555 #define IWL_rb_closed_stts_rb_num_POS 0
 556 #define IWL_rb_closed_stts_rb_num_LEN 12
 557 #define IWL_rb_closed_stts_rb_num_SYM val0
 558         /* __le32 rsrv1:4; */
 559         /* __le32 rb_closed_stts_rx_frame_num:12; */
 560 #define IWL_rb_closed_stts_rx_frame_num_POS 16
 561 #define IWL_rb_closed_stts_rx_frame_num_LEN 12
 562 #define IWL_rb_closed_stts_rx_frame_num_SYM val0
 563         /* __le32 rsrv2:4; */
 564
 565         __le32 val1;
 566         /* __le32 frame_finished_stts_rb_num:12; */
 567 #define IWL_frame_finished_stts_rb_num_POS 0
 568 #define IWL_frame_finished_stts_rb_num_LEN 12
 569 #define IWL_frame_finished_stts_rb_num_SYM val1
 570         /* __le32 rsrv3:4; */
 571         /* __le32 frame_finished_stts_rx_frame_num:12; */
 572 #define IWL_frame_finished_stts_rx_frame_num_POS 16
 573 #define IWL_frame_finished_stts_rx_frame_num_LEN 12
 574 #define IWL_frame_finished_stts_rx_frame_num_SYM val1
 575         /* __le32 rsrv4:4; */
 576
 577         __le32 padding1;  /* so that allocation will be aligned to 16B */
 578         __le32 padding2;
 579 } __attribute__ ((packed));
 580
 581 #endif /* __iwl_4965_hw_h__ */