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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
blob31c1dd271627191813d37278d23abc08bcb48455
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt2400pci"
31
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
39
40 #include "rt2x00.h"
41 #include "rt2x00pci.h"
42 #include "rt2400pci.h"
43
44 /*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
57 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
58 {
59 u32 reg;
60 unsigned int i;
61
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65 break;
66 udelay(REGISTER_BUSY_DELAY);
67 }
68
69 return reg;
70 }
71
72 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73 const unsigned int word, const u8 value)
74 {
75 u32 reg;
76
77 /*
78 * Wait until the BBP becomes ready.
79 */
80 reg = rt2400pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83 return;
84 }
85
86 /*
87 * Write the data into the BBP.
88 */
89 reg = 0;
90 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96 }
97
98 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99 const unsigned int word, u8 *value)
100 {
101 u32 reg;
102
103 /*
104 * Wait until the BBP becomes ready.
105 */
106 reg = rt2400pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109 return;
110 }
111
112 /*
113 * Write the request into the BBP.
114 */
115 reg = 0;
116 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122 /*
123 * Wait until the BBP becomes ready.
124 */
125 reg = rt2400pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128 *value = 0xff;
129 return;
130 }
131
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133 }
134
135 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u32 value)
137 {
138 u32 reg;
139 unsigned int i;
140
141 if (!word)
142 return;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152 return;
153
154 rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
163 }
164
165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166 {
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178 }
179
180 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181 {
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
183 u32 reg = 0;
184
185 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
191
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193 }
194
195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
196 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
198 static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, u32 *data)
200 {
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202 }
203
204 static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205 const unsigned int word, u32 data)
206 {
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208 }
209
210 static const struct rt2x00debug rt2400pci_rt2x00debug = {
211 .owner = THIS_MODULE,
212 .csr = {
213 .read = rt2400pci_read_csr,
214 .write = rt2400pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt2400pci_bbp_read,
226 .write = rt2400pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt2400pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236 };
237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239 #ifdef CONFIG_RT2400PCI_RFKILL
240 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241 {
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246 }
247 #else
248 #define rt2400pci_rfkill_poll NULL
249 #endif /* CONFIG_RT2400PCI_RFKILL */
250
251 /*
252 * Configuration handlers.
253 */
254 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
255 __le32 *mac)
256 {
257 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
258 (2 * sizeof(__le32)));
259 }
260
261 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
262 __le32 *bssid)
263 {
264 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
265 (2 * sizeof(__le32)));
266 }
267
268 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
269 const int tsf_sync)
270 {
271 u32 reg;
272
273 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
274
275 /*
276 * Enable beacon config
277 */
278 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
279 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
280 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
281 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
282
283 /*
284 * Enable synchronisation.
285 */
286 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
287 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
288 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
289 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
290 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
291 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
292 }
293
294 static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
295 const int short_preamble,
296 const int ack_timeout,
297 const int ack_consume_time)
298 {
299 int preamble_mask;
300 u32 reg;
301
302 /*
303 * When short preamble is enabled, we should set bit 0x08
304 */
305 preamble_mask = short_preamble << 3;
306
307 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
308 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
309 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
310 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
311
312 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
313 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
314 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
315 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
316 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
317
318 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
319 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
320 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
321 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
322 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
323
324 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
325 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
326 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
327 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
328 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
329
330 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
331 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
332 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
333 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
334 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
335 }
336
337 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
338 const int basic_rate_mask)
339 {
340 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
341 }
342
343 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
344 struct rf_channel *rf)
345 {
346 /*
347 * Switch on tuning bits.
348 */
349 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
350 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
351
352 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
353 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
354 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
355
356 /*
357 * RF2420 chipset don't need any additional actions.
358 */
359 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
360 return;
361
362 /*
363 * For the RT2421 chipsets we need to write an invalid
364 * reference clock rate to activate auto_tune.
365 * After that we set the value back to the correct channel.
366 */
367 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
368 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
369 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
370
371 msleep(1);
372
373 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
376
377 msleep(1);
378
379 /*
380 * Switch off tuning bits.
381 */
382 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
383 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
384
385 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
386 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
387
388 /*
389 * Clear false CRC during channel switch.
390 */
391 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
392 }
393
394 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
395 {
396 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
397 }
398
399 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
400 int antenna_tx, int antenna_rx)
401 {
402 u8 r1;
403 u8 r4;
404
405 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
406 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
407
408 /*
409 * Configure the TX antenna.
410 */
411 switch (antenna_tx) {
412 case ANTENNA_SW_DIVERSITY:
413 case ANTENNA_HW_DIVERSITY:
414 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
415 break;
416 case ANTENNA_A:
417 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
418 break;
419 case ANTENNA_B:
420 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
421 break;
422 }
423
424 /*
425 * Configure the RX antenna.
426 */
427 switch (antenna_rx) {
428 case ANTENNA_SW_DIVERSITY:
429 case ANTENNA_HW_DIVERSITY:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
431 break;
432 case ANTENNA_A:
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
434 break;
435 case ANTENNA_B:
436 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
437 break;
438 }
439
440 rt2400pci_bbp_write(rt2x00dev, 4, r4);
441 rt2400pci_bbp_write(rt2x00dev, 1, r1);
442 }
443
444 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
445 struct rt2x00lib_conf *libconf)
446 {
447 u32 reg;
448
449 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
450 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
451 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
452
453 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
454 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
455 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
456 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
457
458 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
459 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
460 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
461 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
462
463 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
464 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
465 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
466 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
467
468 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
469 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
470 libconf->conf->beacon_int * 16);
471 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
472 libconf->conf->beacon_int * 16);
473 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
474 }
475
476 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
477 const unsigned int flags,
478 struct rt2x00lib_conf *libconf)
479 {
480 if (flags & CONFIG_UPDATE_PHYMODE)
481 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
482 if (flags & CONFIG_UPDATE_CHANNEL)
483 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
484 if (flags & CONFIG_UPDATE_TXPOWER)
485 rt2400pci_config_txpower(rt2x00dev,
486 libconf->conf->power_level);
487 if (flags & CONFIG_UPDATE_ANTENNA)
488 rt2400pci_config_antenna(rt2x00dev,
489 libconf->conf->antenna_sel_tx,
490 libconf->conf->antenna_sel_rx);
491 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
492 rt2400pci_config_duration(rt2x00dev, libconf);
493 }
494
495 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
496 struct ieee80211_tx_queue_params *params)
497 {
498 u32 reg;
499
500 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
501 rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
502 rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
503 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
504 }
505
506 /*
507 * LED functions.
508 */
509 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
510 {
511 u32 reg;
512
513 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
514
515 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
516 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
517
518 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
519 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
520 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
521 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
522 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
523 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
524 } else {
525 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
526 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
527 }
528
529 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
530 }
531
532 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
533 {
534 u32 reg;
535
536 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
537 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
538 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
539 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
540 }
541
542 /*
543 * Link tuning
544 */
545 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
546 {
547 u32 reg;
548 u8 bbp;
549
550 /*
551 * Update FCS error count from register.
552 */
553 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
554 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
555
556 /*
557 * Update False CCA count from register.
558 */
559 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
560 rt2x00dev->link.false_cca = bbp;
561 }
562
563 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
564 {
565 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
566 rt2x00dev->link.vgc_level = 0x08;
567 }
568
569 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
570 {
571 u8 reg;
572
573 /*
574 * The link tuner should not run longer then 60 seconds,
575 * and should run once every 2 seconds.
576 */
577 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
578 return;
579
580 /*
581 * Base r13 link tuning on the false cca count.
582 */
583 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
584
585 if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
586 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
587 rt2x00dev->link.vgc_level = reg;
588 } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
589 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
590 rt2x00dev->link.vgc_level = reg;
591 }
592 }
593
594 /*
595 * Initialization functions.
596 */
597 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
598 {
599 struct data_ring *ring = rt2x00dev->rx;
600 struct data_desc *rxd;
601 unsigned int i;
602 u32 word;
603
604 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
605
606 for (i = 0; i < ring->stats.limit; i++) {
607 rxd = ring->entry[i].priv;
608
609 rt2x00_desc_read(rxd, 2, &word);
610 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
611 ring->data_size);
612 rt2x00_desc_write(rxd, 2, word);
613
614 rt2x00_desc_read(rxd, 1, &word);
615 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
616 ring->entry[i].data_dma);
617 rt2x00_desc_write(rxd, 1, word);
618
619 rt2x00_desc_read(rxd, 0, &word);
620 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
621 rt2x00_desc_write(rxd, 0, word);
622 }
623
624 rt2x00_ring_index_clear(rt2x00dev->rx);
625 }
626
627 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
628 {
629 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
630 struct data_desc *txd;
631 unsigned int i;
632 u32 word;
633
634 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
635
636 for (i = 0; i < ring->stats.limit; i++) {
637 txd = ring->entry[i].priv;
638
639 rt2x00_desc_read(txd, 1, &word);
640 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
641 ring->entry[i].data_dma);
642 rt2x00_desc_write(txd, 1, word);
643
644 rt2x00_desc_read(txd, 2, &word);
645 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
646 ring->data_size);
647 rt2x00_desc_write(txd, 2, word);
648
649 rt2x00_desc_read(txd, 0, &word);
650 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
651 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
652 rt2x00_desc_write(txd, 0, word);
653 }
654
655 rt2x00_ring_index_clear(ring);
656 }
657
658 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
659 {
660 u32 reg;
661
662 /*
663 * Initialize rings.
664 */
665 rt2400pci_init_rxring(rt2x00dev);
666 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
667 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
668 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
669 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
670
671 /*
672 * Initialize registers.
673 */
674 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
675 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
676 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
677 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
678 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
679 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
680 rt2x00dev->bcn[1].stats.limit);
681 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
682 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
683 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
684
685 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
686 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
687 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
688 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
689
690 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
691 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
692 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
693 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
694
695 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
696 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
697 rt2x00dev->bcn[1].data_dma);
698 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
699
700 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
701 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
702 rt2x00dev->bcn[0].data_dma);
703 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
704
705 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
706 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
707 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
708 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
709
710 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
711 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
712 rt2x00dev->rx->data_dma);
713 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
714
715 return 0;
716 }
717
718 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
719 {
720 u32 reg;
721
722 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
723 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
724 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
725 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
726
727 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
728 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
729 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
730 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
731 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
732
733 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
734 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
735 (rt2x00dev->rx->data_size / 128));
736 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
737
738 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
739
740 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
741 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
742 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
743 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
744 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
745 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
746
747 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
748 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
749 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
750 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
751 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
752 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
753 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
754 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
755
756 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
757
758 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
759 return -EBUSY;
760
761 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
762 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
763
764 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
765 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
766 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
767
768 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
769 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
770 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
771 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
772 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
773 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
774
775 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
776 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
777 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
778 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
779 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
780
781 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
782 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
783 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
784 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
785
786 /*
787 * We must clear the FCS and FIFO error count.
788 * These registers are cleared on read,
789 * so we may pass a useless variable to store the value.
790 */
791 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
792 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
793
794 return 0;
795 }
796
797 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
798 {
799 unsigned int i;
800 u16 eeprom;
801 u8 reg_id;
802 u8 value;
803
804 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
805 rt2400pci_bbp_read(rt2x00dev, 0, &value);
806 if ((value != 0xff) && (value != 0x00))
807 goto continue_csr_init;
808 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
809 udelay(REGISTER_BUSY_DELAY);
810 }
811
812 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
813 return -EACCES;
814
815 continue_csr_init:
816 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
817 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
818 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
819 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
820 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
821 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
822 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
823 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
824 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
825 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
826 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
827 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
828 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
829 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
830
831 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
832 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
833 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
834
835 if (eeprom != 0xffff && eeprom != 0x0000) {
836 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
837 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
838 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
839 reg_id, value);
840 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
841 }
842 }
843 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
844
845 return 0;
846 }
847
848 /*
849 * Device state switch handlers.
850 */
851 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
852 enum dev_state state)
853 {
854 u32 reg;
855
856 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
857 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
858 state == STATE_RADIO_RX_OFF);
859 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
860 }
861
862 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
863 enum dev_state state)
864 {
865 int mask = (state == STATE_RADIO_IRQ_OFF);
866 u32 reg;
867
868 /*
869 * When interrupts are being enabled, the interrupt registers
870 * should clear the register to assure a clean state.
871 */
872 if (state == STATE_RADIO_IRQ_ON) {
873 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
874 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
875 }
876
877 /*
878 * Only toggle the interrupts bits we are going to use.
879 * Non-checked interrupt bits are disabled by default.
880 */
881 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
882 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
883 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
884 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
885 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
886 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
887 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
888 }
889
890 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
891 {
892 /*
893 * Initialize all registers.
894 */
895 if (rt2400pci_init_rings(rt2x00dev) ||
896 rt2400pci_init_registers(rt2x00dev) ||
897 rt2400pci_init_bbp(rt2x00dev)) {
898 ERROR(rt2x00dev, "Register initialization failed.\n");
899 return -EIO;
900 }
901
902 /*
903 * Enable interrupts.
904 */
905 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
906
907 /*
908 * Enable LED
909 */
910 rt2400pci_enable_led(rt2x00dev);
911
912 return 0;
913 }
914
915 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
916 {
917 u32 reg;
918
919 /*
920 * Disable LED
921 */
922 rt2400pci_disable_led(rt2x00dev);
923
924 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
925
926 /*
927 * Disable synchronisation.
928 */
929 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
930
931 /*
932 * Cancel RX and TX.
933 */
934 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
935 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
936 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
937
938 /*
939 * Disable interrupts.
940 */
941 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
942 }
943
944 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
945 enum dev_state state)
946 {
947 u32 reg;
948 unsigned int i;
949 char put_to_sleep;
950 char bbp_state;
951 char rf_state;
952
953 put_to_sleep = (state != STATE_AWAKE);
954
955 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
956 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
957 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
958 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
959 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
960 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
961
962 /*
963 * Device is not guaranteed to be in the requested state yet.
964 * We must wait until the register indicates that the
965 * device has entered the correct state.
966 */
967 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
968 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
969 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
970 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
971 if (bbp_state == state && rf_state == state)
972 return 0;
973 msleep(10);
974 }
975
976 NOTICE(rt2x00dev, "Device failed to enter state %d, "
977 "current device state: bbp %d and rf %d.\n",
978 state, bbp_state, rf_state);
979
980 return -EBUSY;
981 }
982
983 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
984 enum dev_state state)
985 {
986 int retval = 0;
987
988 switch (state) {
989 case STATE_RADIO_ON:
990 retval = rt2400pci_enable_radio(rt2x00dev);
991 break;
992 case STATE_RADIO_OFF:
993 rt2400pci_disable_radio(rt2x00dev);
994 break;
995 case STATE_RADIO_RX_ON:
996 case STATE_RADIO_RX_OFF:
997 rt2400pci_toggle_rx(rt2x00dev, state);
998 break;
999 case STATE_DEEP_SLEEP:
1000 case STATE_SLEEP:
1001 case STATE_STANDBY:
1002 case STATE_AWAKE:
1003 retval = rt2400pci_set_state(rt2x00dev, state);
1004 break;
1005 default:
1006 retval = -ENOTSUPP;
1007 break;
1008 }
1009
1010 return retval;
1011 }
1012
1013 /*
1014 * TX descriptor initialization
1015 */
1016 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1017 struct data_desc *txd,
1018 struct txdata_entry_desc *desc,
1019 struct ieee80211_hdr *ieee80211hdr,
1020 unsigned int length,
1021 struct ieee80211_tx_control *control)
1022 {
1023 u32 word;
1024 u32 signal = 0;
1025 u32 service = 0;
1026 u32 length_high = 0;
1027 u32 length_low = 0;
1028
1029 /*
1030 * The PLCP values should be treated as if they
1031 * were BBP values.
1032 */
1033 rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1034 rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1035 rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1036
1037 rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1038 rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1039 rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1040
1041 rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1042 rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1043 rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1044
1045 rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1046 rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1047 rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1048
1049 /*
1050 * Start writing the descriptor words.
1051 */
1052 rt2x00_desc_read(txd, 2, &word);
1053 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1054 rt2x00_desc_write(txd, 2, word);
1055
1056 rt2x00_desc_read(txd, 3, &word);
1057 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1058 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1059 rt2x00_desc_write(txd, 3, word);
1060
1061 rt2x00_desc_read(txd, 4, &word);
1062 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1063 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1064 rt2x00_desc_write(txd, 4, word);
1065
1066 rt2x00_desc_read(txd, 0, &word);
1067 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1068 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1069 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1070 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1071 rt2x00_set_field32(&word, TXD_W0_ACK,
1072 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1073 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1074 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1075 rt2x00_set_field32(&word, TXD_W0_RTS,
1076 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1077 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1078 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1079 !!(control->flags &
1080 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1081 rt2x00_desc_write(txd, 0, word);
1082 }
1083
1084 /*
1085 * TX data initialization
1086 */
1087 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1088 unsigned int queue)
1089 {
1090 u32 reg;
1091
1092 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1093 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1094 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1095 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1096 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1097 }
1098 return;
1099 }
1100
1101 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1102 if (queue == IEEE80211_TX_QUEUE_DATA0)
1103 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1104 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1105 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1106 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1107 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1108 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1109 }
1110
1111 /*
1112 * RX control handlers
1113 */
1114 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1115 struct rxdata_entry_desc *desc)
1116 {
1117 struct data_desc *rxd = entry->priv;
1118 u32 word0;
1119 u32 word2;
1120
1121 rt2x00_desc_read(rxd, 0, &word0);
1122 rt2x00_desc_read(rxd, 2, &word2);
1123
1124 desc->flags = 0;
1125 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1126 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1127 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1128 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1129
1130 /*
1131 * Obtain the status about this packet.
1132 */
1133 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1134 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1135 entry->ring->rt2x00dev->rssi_offset;
1136 desc->ofdm = 0;
1137 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1138 }
1139
1140 /*
1141 * Interrupt functions.
1142 */
1143 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1144 {
1145 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1146 struct data_entry *entry;
1147 struct data_desc *txd;
1148 u32 word;
1149 int tx_status;
1150 int retry;
1151
1152 while (!rt2x00_ring_empty(ring)) {
1153 entry = rt2x00_get_data_entry_done(ring);
1154 txd = entry->priv;
1155 rt2x00_desc_read(txd, 0, &word);
1156
1157 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1158 !rt2x00_get_field32(word, TXD_W0_VALID))
1159 break;
1160
1161 /*
1162 * Obtain the status about this packet.
1163 */
1164 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1165 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1166
1167 rt2x00lib_txdone(entry, tx_status, retry);
1168
1169 /*
1170 * Make this entry available for reuse.
1171 */
1172 entry->flags = 0;
1173 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1174 rt2x00_desc_write(txd, 0, word);
1175 rt2x00_ring_index_done_inc(ring);
1176 }
1177
1178 /*
1179 * If the data ring was full before the txdone handler
1180 * we must make sure the packet queue in the mac80211 stack
1181 * is reenabled when the txdone handler has finished.
1182 */
1183 entry = ring->entry;
1184 if (!rt2x00_ring_full(ring))
1185 ieee80211_wake_queue(rt2x00dev->hw,
1186 entry->tx_status.control.queue);
1187 }
1188
1189 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1190 {
1191 struct rt2x00_dev *rt2x00dev = dev_instance;
1192 u32 reg;
1193
1194 /*
1195 * Get the interrupt sources & saved to local variable.
1196 * Write register value back to clear pending interrupts.
1197 */
1198 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1199 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1200
1201 if (!reg)
1202 return IRQ_NONE;
1203
1204 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1205 return IRQ_HANDLED;
1206
1207 /*
1208 * Handle interrupts, walk through all bits
1209 * and run the tasks, the bits are checked in order of
1210 * priority.
1211 */
1212
1213 /*
1214 * 1 - Beacon timer expired interrupt.
1215 */
1216 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1217 rt2x00lib_beacondone(rt2x00dev);
1218
1219 /*
1220 * 2 - Rx ring done interrupt.
1221 */
1222 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1223 rt2x00pci_rxdone(rt2x00dev);
1224
1225 /*
1226 * 3 - Atim ring transmit done interrupt.
1227 */
1228 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1229 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1230
1231 /*
1232 * 4 - Priority ring transmit done interrupt.
1233 */
1234 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1235 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1236
1237 /*
1238 * 5 - Tx ring transmit done interrupt.
1239 */
1240 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1241 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1242
1243 return IRQ_HANDLED;
1244 }
1245
1246 /*
1247 * Device probe functions.
1248 */
1249 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1250 {
1251 struct eeprom_93cx6 eeprom;
1252 u32 reg;
1253 u16 word;
1254 u8 *mac;
1255
1256 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1257
1258 eeprom.data = rt2x00dev;
1259 eeprom.register_read = rt2400pci_eepromregister_read;
1260 eeprom.register_write = rt2400pci_eepromregister_write;
1261 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1262 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1263 eeprom.reg_data_in = 0;
1264 eeprom.reg_data_out = 0;
1265 eeprom.reg_data_clock = 0;
1266 eeprom.reg_chip_select = 0;
1267
1268 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1269 EEPROM_SIZE / sizeof(u16));
1270
1271 /*
1272 * Start validation of the data that has been read.
1273 */
1274 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1275 if (!is_valid_ether_addr(mac)) {
1276 DECLARE_MAC_BUF(macbuf);
1277
1278 random_ether_addr(mac);
1279 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1280 }
1281
1282 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1283 if (word == 0xffff) {
1284 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1285 return -EINVAL;
1286 }
1287
1288 return 0;
1289 }
1290
1291 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1292 {
1293 u32 reg;
1294 u16 value;
1295 u16 eeprom;
1296
1297 /*
1298 * Read EEPROM word for configuration.
1299 */
1300 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1301
1302 /*
1303 * Identify RF chipset.
1304 */
1305 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1306 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1307 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1308
1309 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1310 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1311 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1312 return -ENODEV;
1313 }
1314
1315 /*
1316 * Identify default antenna configuration.
1317 */
1318 rt2x00dev->hw->conf.antenna_sel_tx =
1319 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1320 rt2x00dev->hw->conf.antenna_sel_rx =
1321 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1322
1323 /*
1324 * Store led mode, for correct led behaviour.
1325 */
1326 rt2x00dev->led_mode =
1327 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1328
1329 /*
1330 * Detect if this device has an hardware controlled radio.
1331 */
1332 #ifdef CONFIG_RT2400PCI_RFKILL
1333 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1334 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1335 #endif /* CONFIG_RT2400PCI_RFKILL */
1336
1337 /*
1338 * Check if the BBP tuning should be enabled.
1339 */
1340 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1341 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1342
1343 return 0;
1344 }
1345
1346 /*
1347 * RF value list for RF2420 & RF2421
1348 * Supports: 2.4 GHz
1349 */
1350 static const struct rf_channel rf_vals_bg[] = {
1351 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1352 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1353 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1354 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1355 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1356 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1357 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1358 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1359 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1360 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1361 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1362 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1363 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1364 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1365 };
1366
1367 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1368 {
1369 struct hw_mode_spec *spec = &rt2x00dev->spec;
1370 u8 *txpower;
1371 unsigned int i;
1372
1373 /*
1374 * Initialize all hw fields.
1375 */
1376 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1377 rt2x00dev->hw->extra_tx_headroom = 0;
1378 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1379 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1380 rt2x00dev->hw->queues = 2;
1381
1382 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1383 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1384 rt2x00_eeprom_addr(rt2x00dev,
1385 EEPROM_MAC_ADDR_0));
1386
1387 /*
1388 * Convert tx_power array in eeprom.
1389 */
1390 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1391 for (i = 0; i < 14; i++)
1392 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1393
1394 /*
1395 * Initialize hw_mode information.
1396 */
1397 spec->num_modes = 1;
1398 spec->num_rates = 4;
1399 spec->tx_power_a = NULL;
1400 spec->tx_power_bg = txpower;
1401 spec->tx_power_default = DEFAULT_TXPOWER;
1402
1403 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1404 spec->channels = rf_vals_bg;
1405 }
1406
1407 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1408 {
1409 int retval;
1410
1411 /*
1412 * Allocate eeprom data.
1413 */
1414 retval = rt2400pci_validate_eeprom(rt2x00dev);
1415 if (retval)
1416 return retval;
1417
1418 retval = rt2400pci_init_eeprom(rt2x00dev);
1419 if (retval)
1420 return retval;
1421
1422 /*
1423 * Initialize hw specifications.
1424 */
1425 rt2400pci_probe_hw_mode(rt2x00dev);
1426
1427 /*
1428 * This device requires the beacon ring
1429 */
1430 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1431
1432 /*
1433 * Set the rssi offset.
1434 */
1435 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1436
1437 return 0;
1438 }
1439
1440 /*
1441 * IEEE80211 stack callback functions.
1442 */
1443 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1444 unsigned int changed_flags,
1445 unsigned int *total_flags,
1446 int mc_count,
1447 struct dev_addr_list *mc_list)
1448 {
1449 struct rt2x00_dev *rt2x00dev = hw->priv;
1450 struct interface *intf = &rt2x00dev->interface;
1451 u32 reg;
1452
1453 /*
1454 * Mask off any flags we are going to ignore from
1455 * the total_flags field.
1456 */
1457 *total_flags &=
1458 FIF_ALLMULTI |
1459 FIF_FCSFAIL |
1460 FIF_PLCPFAIL |
1461 FIF_CONTROL |
1462 FIF_OTHER_BSS |
1463 FIF_PROMISC_IN_BSS;
1464
1465 /*
1466 * Apply some rules to the filters:
1467 * - Some filters imply different filters to be set.
1468 * - Some things we can't filter out at all.
1469 * - Some filters are set based on interface type.
1470 */
1471 *total_flags |= FIF_ALLMULTI;
1472 if (*total_flags & FIF_OTHER_BSS ||
1473 *total_flags & FIF_PROMISC_IN_BSS)
1474 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1475 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1476 *total_flags |= FIF_PROMISC_IN_BSS;
1477
1478 /*
1479 * Check if there is any work left for us.
1480 */
1481 if (intf->filter == *total_flags)
1482 return;
1483 intf->filter = *total_flags;
1484
1485 /*
1486 * Start configuration steps.
1487 * Note that the version error will always be dropped
1488 * since there is no filter for it at this time.
1489 */
1490 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1491 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1492 !(*total_flags & FIF_FCSFAIL));
1493 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1494 !(*total_flags & FIF_PLCPFAIL));
1495 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1496 !(*total_flags & FIF_CONTROL));
1497 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1498 !(*total_flags & FIF_PROMISC_IN_BSS));
1499 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1500 !(*total_flags & FIF_PROMISC_IN_BSS));
1501 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1502 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1503 }
1504
1505 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1506 u32 short_retry, u32 long_retry)
1507 {
1508 struct rt2x00_dev *rt2x00dev = hw->priv;
1509 u32 reg;
1510
1511 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1512 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1513 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1514 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1515
1516 return 0;
1517 }
1518
1519 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1520 int queue,
1521 const struct ieee80211_tx_queue_params *params)
1522 {
1523 struct rt2x00_dev *rt2x00dev = hw->priv;
1524
1525 /*
1526 * We don't support variating cw_min and cw_max variables
1527 * per queue. So by default we only configure the TX queue,
1528 * and ignore all other configurations.
1529 */
1530 if (queue != IEEE80211_TX_QUEUE_DATA0)
1531 return -EINVAL;
1532
1533 if (rt2x00mac_conf_tx(hw, queue, params))
1534 return -EINVAL;
1535
1536 /*
1537 * Write configuration to register.
1538 */
1539 rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1540
1541 return 0;
1542 }
1543
1544 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1545 {
1546 struct rt2x00_dev *rt2x00dev = hw->priv;
1547 u64 tsf;
1548 u32 reg;
1549
1550 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1551 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1552 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1553 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1554
1555 return tsf;
1556 }
1557
1558 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1559 {
1560 struct rt2x00_dev *rt2x00dev = hw->priv;
1561
1562 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1563 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1564 }
1565
1566 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1567 {
1568 struct rt2x00_dev *rt2x00dev = hw->priv;
1569 u32 reg;
1570
1571 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1572 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1573 }
1574
1575 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1576 .tx = rt2x00mac_tx,
1577 .start = rt2x00mac_start,
1578 .stop = rt2x00mac_stop,
1579 .add_interface = rt2x00mac_add_interface,
1580 .remove_interface = rt2x00mac_remove_interface,
1581 .config = rt2x00mac_config,
1582 .config_interface = rt2x00mac_config_interface,
1583 .configure_filter = rt2400pci_configure_filter,
1584 .get_stats = rt2x00mac_get_stats,
1585 .set_retry_limit = rt2400pci_set_retry_limit,
1586 .erp_ie_changed = rt2x00mac_erp_ie_changed,
1587 .conf_tx = rt2400pci_conf_tx,
1588 .get_tx_stats = rt2x00mac_get_tx_stats,
1589 .get_tsf = rt2400pci_get_tsf,
1590 .reset_tsf = rt2400pci_reset_tsf,
1591 .beacon_update = rt2x00pci_beacon_update,
1592 .tx_last_beacon = rt2400pci_tx_last_beacon,
1593 };
1594
1595 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1596 .irq_handler = rt2400pci_interrupt,
1597 .probe_hw = rt2400pci_probe_hw,
1598 .initialize = rt2x00pci_initialize,
1599 .uninitialize = rt2x00pci_uninitialize,
1600 .set_device_state = rt2400pci_set_device_state,
1601 .rfkill_poll = rt2400pci_rfkill_poll,
1602 .link_stats = rt2400pci_link_stats,
1603 .reset_tuner = rt2400pci_reset_tuner,
1604 .link_tuner = rt2400pci_link_tuner,
1605 .write_tx_desc = rt2400pci_write_tx_desc,
1606 .write_tx_data = rt2x00pci_write_tx_data,
1607 .kick_tx_queue = rt2400pci_kick_tx_queue,
1608 .fill_rxdone = rt2400pci_fill_rxdone,
1609 .config_mac_addr = rt2400pci_config_mac_addr,
1610 .config_bssid = rt2400pci_config_bssid,
1611 .config_type = rt2400pci_config_type,
1612 .config_preamble = rt2400pci_config_preamble,
1613 .config = rt2400pci_config,
1614 };
1615
1616 static const struct rt2x00_ops rt2400pci_ops = {
1617 .name = DRV_NAME,
1618 .rxd_size = RXD_DESC_SIZE,
1619 .txd_size = TXD_DESC_SIZE,
1620 .eeprom_size = EEPROM_SIZE,
1621 .rf_size = RF_SIZE,
1622 .lib = &rt2400pci_rt2x00_ops,
1623 .hw = &rt2400pci_mac80211_ops,
1624 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1625 .debugfs = &rt2400pci_rt2x00debug,
1626 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1627 };
1628
1629 /*
1630 * RT2400pci module information.
1631 */
1632 static struct pci_device_id rt2400pci_device_table[] = {
1633 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1634 { 0, }
1635 };
1636
1637 MODULE_AUTHOR(DRV_PROJECT);
1638 MODULE_VERSION(DRV_VERSION);
1639 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1640 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1641 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1642 MODULE_LICENSE("GPL");
1643
1644 static struct pci_driver rt2400pci_driver = {
1645 .name = DRV_NAME,
1646 .id_table = rt2400pci_device_table,
1647 .probe = rt2x00pci_probe,
1648 .remove = __devexit_p(rt2x00pci_remove),
1649 .suspend = rt2x00pci_suspend,
1650 .resume = rt2x00pci_resume,
1651 };
1652
1653 static int __init rt2400pci_init(void)
1654 {
1655 return pci_register_driver(&rt2400pci_driver);
1656 }
1657
1658 static void __exit rt2400pci_exit(void)
1659 {
1660 pci_unregister_driver(&rt2400pci_driver);
1661 }
1662
1663 module_init(rt2400pci_init);
1664 module_exit(rt2400pci_exit);
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