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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blobff2d63267b19e8acb41b356e8524e3451014f291
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt2500pci"
31
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
39
40 #include "rt2x00.h"
41 #include "rt2x00pci.h"
42 #include "rt2500pci.h"
43
44 /*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
57 static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
58 {
59 u32 reg;
60 unsigned int i;
61
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65 break;
66 udelay(REGISTER_BUSY_DELAY);
67 }
68
69 return reg;
70 }
71
72 static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73 const unsigned int word, const u8 value)
74 {
75 u32 reg;
76
77 /*
78 * Wait until the BBP becomes ready.
79 */
80 reg = rt2500pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83 return;
84 }
85
86 /*
87 * Write the data into the BBP.
88 */
89 reg = 0;
90 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96 }
97
98 static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99 const unsigned int word, u8 *value)
100 {
101 u32 reg;
102
103 /*
104 * Wait until the BBP becomes ready.
105 */
106 reg = rt2500pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109 return;
110 }
111
112 /*
113 * Write the request into the BBP.
114 */
115 reg = 0;
116 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122 /*
123 * Wait until the BBP becomes ready.
124 */
125 reg = rt2500pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128 *value = 0xff;
129 return;
130 }
131
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133 }
134
135 static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u32 value)
137 {
138 u32 reg;
139 unsigned int i;
140
141 if (!word)
142 return;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152 return;
153
154 rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
163 }
164
165 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166 {
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178 }
179
180 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181 {
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
183 u32 reg = 0;
184
185 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
191
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193 }
194
195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
196 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
198 static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, u32 *data)
200 {
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202 }
203
204 static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205 const unsigned int word, u32 data)
206 {
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208 }
209
210 static const struct rt2x00debug rt2500pci_rt2x00debug = {
211 .owner = THIS_MODULE,
212 .csr = {
213 .read = rt2500pci_read_csr,
214 .write = rt2500pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt2500pci_bbp_read,
226 .write = rt2500pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt2500pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236 };
237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239 #ifdef CONFIG_RT2500PCI_RFKILL
240 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241 {
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246 }
247 #else
248 #define rt2500pci_rfkill_poll NULL
249 #endif /* CONFIG_RT2500PCI_RFKILL */
250
251 /*
252 * Configuration handlers.
253 */
254 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
255 __le32 *mac)
256 {
257 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
258 (2 * sizeof(__le32)));
259 }
260
261 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
262 __le32 *bssid)
263 {
264 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
265 (2 * sizeof(__le32)));
266 }
267
268 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
269 const int tsf_sync)
270 {
271 u32 reg;
272
273 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
274
275 /*
276 * Enable beacon config
277 */
278 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
279 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
280 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
281 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
282 rt2x00lib_get_ring(rt2x00dev,
283 IEEE80211_TX_QUEUE_BEACON)
284 ->tx_params.cw_min);
285 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
286
287 /*
288 * Enable synchronisation.
289 */
290 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
291 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
292 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
293 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
294 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
295 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
296 }
297
298 static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
299 const int short_preamble,
300 const int ack_timeout,
301 const int ack_consume_time)
302 {
303 int preamble_mask;
304 u32 reg;
305
306 /*
307 * When short preamble is enabled, we should set bit 0x08
308 */
309 preamble_mask = short_preamble << 3;
310
311 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
312 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
313 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
314 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
315
316 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
317 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
318 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
319 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
320 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
321
322 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
323 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
324 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
325 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
326 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
327
328 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
329 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
330 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
331 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
332 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
333
334 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
335 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
336 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
337 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
338 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
339 }
340
341 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
342 const int basic_rate_mask)
343 {
344 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
345 }
346
347 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
348 struct rf_channel *rf, const int txpower)
349 {
350 u8 r70;
351
352 /*
353 * Set TXpower.
354 */
355 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
356
357 /*
358 * Switch on tuning bits.
359 * For RT2523 devices we do not need to update the R1 register.
360 */
361 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
362 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
363 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
364
365 /*
366 * For RT2525 we should first set the channel to half band higher.
367 */
368 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
369 static const u32 vals[] = {
370 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
371 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
372 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
373 0x00080d2e, 0x00080d3a
374 };
375
376 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
377 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
378 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
379 if (rf->rf4)
380 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
381 }
382
383 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
384 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
385 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
386 if (rf->rf4)
387 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
388
389 /*
390 * Channel 14 requires the Japan filter bit to be set.
391 */
392 r70 = 0x46;
393 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
394 rt2500pci_bbp_write(rt2x00dev, 70, r70);
395
396 msleep(1);
397
398 /*
399 * Switch off tuning bits.
400 * For RT2523 devices we do not need to update the R1 register.
401 */
402 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
403 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
404 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
405 }
406
407 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
408 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
409
410 /*
411 * Clear false CRC during channel switch.
412 */
413 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
414 }
415
416 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
417 const int txpower)
418 {
419 u32 rf3;
420
421 rt2x00_rf_read(rt2x00dev, 3, &rf3);
422 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
423 rt2500pci_rf_write(rt2x00dev, 3, rf3);
424 }
425
426 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
427 const int antenna_tx, const int antenna_rx)
428 {
429 u32 reg;
430 u8 r14;
431 u8 r2;
432
433 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
434 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
435 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
436
437 /*
438 * Configure the TX antenna.
439 */
440 switch (antenna_tx) {
441 case ANTENNA_SW_DIVERSITY:
442 case ANTENNA_HW_DIVERSITY:
443 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
444 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
445 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
446 break;
447 case ANTENNA_A:
448 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
449 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
450 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
451 break;
452 case ANTENNA_B:
453 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
454 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
455 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
456 break;
457 }
458
459 /*
460 * Configure the RX antenna.
461 */
462 switch (antenna_rx) {
463 case ANTENNA_SW_DIVERSITY:
464 case ANTENNA_HW_DIVERSITY:
465 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
466 break;
467 case ANTENNA_A:
468 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
469 break;
470 case ANTENNA_B:
471 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
472 break;
473 }
474
475 /*
476 * RT2525E and RT5222 need to flip TX I/Q
477 */
478 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
479 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
480 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
481 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
482 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
483
484 /*
485 * RT2525E does not need RX I/Q Flip.
486 */
487 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
488 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
489 } else {
490 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
491 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
492 }
493
494 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
495 rt2500pci_bbp_write(rt2x00dev, 14, r14);
496 rt2500pci_bbp_write(rt2x00dev, 2, r2);
497 }
498
499 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
500 struct rt2x00lib_conf *libconf)
501 {
502 u32 reg;
503
504 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
505 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
506 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
507
508 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
509 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
510 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
511 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
512
513 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
514 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
515 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
516 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
517
518 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
519 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
520 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
521 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
522
523 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
524 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
525 libconf->conf->beacon_int * 16);
526 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
527 libconf->conf->beacon_int * 16);
528 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
529 }
530
531 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
532 const unsigned int flags,
533 struct rt2x00lib_conf *libconf)
534 {
535 if (flags & CONFIG_UPDATE_PHYMODE)
536 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
537 if (flags & CONFIG_UPDATE_CHANNEL)
538 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
539 libconf->conf->power_level);
540 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
541 rt2500pci_config_txpower(rt2x00dev,
542 libconf->conf->power_level);
543 if (flags & CONFIG_UPDATE_ANTENNA)
544 rt2500pci_config_antenna(rt2x00dev,
545 libconf->conf->antenna_sel_tx,
546 libconf->conf->antenna_sel_rx);
547 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
548 rt2500pci_config_duration(rt2x00dev, libconf);
549 }
550
551 /*
552 * LED functions.
553 */
554 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
555 {
556 u32 reg;
557
558 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
559
560 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
561 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
562
563 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
564 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
565 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
566 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
567 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
568 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
569 } else {
570 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
571 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
572 }
573
574 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
575 }
576
577 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
578 {
579 u32 reg;
580
581 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
582 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
583 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
584 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
585 }
586
587 /*
588 * Link tuning
589 */
590 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
591 {
592 u32 reg;
593
594 /*
595 * Update FCS error count from register.
596 */
597 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
598 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
599
600 /*
601 * Update False CCA count from register.
602 */
603 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
604 rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
605 }
606
607 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
608 {
609 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
610 rt2x00dev->link.vgc_level = 0x48;
611 }
612
613 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
614 {
615 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
616 u8 r17;
617
618 /*
619 * To prevent collisions with MAC ASIC on chipsets
620 * up to version C the link tuning should halt after 20
621 * seconds.
622 */
623 if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
624 rt2x00dev->link.count > 20)
625 return;
626
627 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
628
629 /*
630 * Chipset versions C and lower should directly continue
631 * to the dynamic CCA tuning.
632 */
633 if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
634 goto dynamic_cca_tune;
635
636 /*
637 * A too low RSSI will cause too much false CCA which will
638 * then corrupt the R17 tuning. To remidy this the tuning should
639 * be stopped (While making sure the R17 value will not exceed limits)
640 */
641 if (rssi < -80 && rt2x00dev->link.count > 20) {
642 if (r17 >= 0x41) {
643 r17 = rt2x00dev->link.vgc_level;
644 rt2500pci_bbp_write(rt2x00dev, 17, r17);
645 }
646 return;
647 }
648
649 /*
650 * Special big-R17 for short distance
651 */
652 if (rssi >= -58) {
653 if (r17 != 0x50)
654 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
655 return;
656 }
657
658 /*
659 * Special mid-R17 for middle distance
660 */
661 if (rssi >= -74) {
662 if (r17 != 0x41)
663 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
664 return;
665 }
666
667 /*
668 * Leave short or middle distance condition, restore r17
669 * to the dynamic tuning range.
670 */
671 if (r17 >= 0x41) {
672 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
673 return;
674 }
675
676 dynamic_cca_tune:
677
678 /*
679 * R17 is inside the dynamic tuning range,
680 * start tuning the link based on the false cca counter.
681 */
682 if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
683 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
684 rt2x00dev->link.vgc_level = r17;
685 } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
686 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
687 rt2x00dev->link.vgc_level = r17;
688 }
689 }
690
691 /*
692 * Initialization functions.
693 */
694 static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
695 {
696 struct data_ring *ring = rt2x00dev->rx;
697 struct data_desc *rxd;
698 unsigned int i;
699 u32 word;
700
701 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
702
703 for (i = 0; i < ring->stats.limit; i++) {
704 rxd = ring->entry[i].priv;
705
706 rt2x00_desc_read(rxd, 1, &word);
707 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
708 ring->entry[i].data_dma);
709 rt2x00_desc_write(rxd, 1, word);
710
711 rt2x00_desc_read(rxd, 0, &word);
712 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
713 rt2x00_desc_write(rxd, 0, word);
714 }
715
716 rt2x00_ring_index_clear(rt2x00dev->rx);
717 }
718
719 static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
720 {
721 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
722 struct data_desc *txd;
723 unsigned int i;
724 u32 word;
725
726 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
727
728 for (i = 0; i < ring->stats.limit; i++) {
729 txd = ring->entry[i].priv;
730
731 rt2x00_desc_read(txd, 1, &word);
732 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
733 ring->entry[i].data_dma);
734 rt2x00_desc_write(txd, 1, word);
735
736 rt2x00_desc_read(txd, 0, &word);
737 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
738 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
739 rt2x00_desc_write(txd, 0, word);
740 }
741
742 rt2x00_ring_index_clear(ring);
743 }
744
745 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
746 {
747 u32 reg;
748
749 /*
750 * Initialize rings.
751 */
752 rt2500pci_init_rxring(rt2x00dev);
753 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
754 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
755 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
756 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
757
758 /*
759 * Initialize registers.
760 */
761 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
762 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
763 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
765 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
766 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
767 rt2x00dev->bcn[1].stats.limit);
768 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
769 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
770 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
771
772 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
773 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
774 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
775 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
776
777 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
778 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
779 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
780 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
781
782 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
783 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
784 rt2x00dev->bcn[1].data_dma);
785 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
786
787 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
788 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
789 rt2x00dev->bcn[0].data_dma);
790 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
791
792 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
793 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
794 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
795 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
796
797 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
798 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
799 rt2x00dev->rx->data_dma);
800 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
801
802 return 0;
803 }
804
805 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
806 {
807 u32 reg;
808
809 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
810 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
811 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
813
814 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
815 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
816 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
817 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
818 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
819
820 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
821 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
822 rt2x00dev->rx->data_size / 128);
823 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
824
825 /*
826 * Always use CWmin and CWmax set in descriptor.
827 */
828 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
829 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
830 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
831
832 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
833
834 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
835 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
836 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
837 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
838 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
839 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
840 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
841 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
842 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
843 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
844
845 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
846 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
847 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
848 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
849 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
850 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
851
852 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
853 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
854 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
855 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
856 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
857 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
858
859 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
860 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
861 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
862 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
863 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
864 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
865
866 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
867 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
868 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
869 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
870 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
871 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
872 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
873 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
874 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
875 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
876
877 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
878 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
879 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
880 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
881 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
882 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
883 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
884 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
885 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
886
887 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
888
889 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
890 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
891
892 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
893 return -EBUSY;
894
895 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
896 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
897
898 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
899 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
900 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
901
902 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
903 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
904 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
905 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
906 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
907 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
908 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
909 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
910
911 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
912
913 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
914
915 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
916 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
917 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
918 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
919 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
920
921 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
922 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
923 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
924 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
925
926 /*
927 * We must clear the FCS and FIFO error count.
928 * These registers are cleared on read,
929 * so we may pass a useless variable to store the value.
930 */
931 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
932 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
933
934 return 0;
935 }
936
937 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
938 {
939 unsigned int i;
940 u16 eeprom;
941 u8 reg_id;
942 u8 value;
943
944 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
945 rt2500pci_bbp_read(rt2x00dev, 0, &value);
946 if ((value != 0xff) && (value != 0x00))
947 goto continue_csr_init;
948 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
949 udelay(REGISTER_BUSY_DELAY);
950 }
951
952 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
953 return -EACCES;
954
955 continue_csr_init:
956 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
957 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
958 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
959 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
960 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
961 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
962 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
963 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
964 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
965 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
966 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
967 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
968 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
969 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
970 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
971 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
972 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
973 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
974 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
975 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
976 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
977 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
978 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
979 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
980 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
981 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
982 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
983 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
984 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
985 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
986
987 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
988 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
989 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
990
991 if (eeprom != 0xffff && eeprom != 0x0000) {
992 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
993 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
994 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
995 reg_id, value);
996 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
997 }
998 }
999 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1000
1001 return 0;
1002 }
1003
1004 /*
1005 * Device state switch handlers.
1006 */
1007 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1008 enum dev_state state)
1009 {
1010 u32 reg;
1011
1012 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1013 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1014 state == STATE_RADIO_RX_OFF);
1015 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1016 }
1017
1018 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1019 enum dev_state state)
1020 {
1021 int mask = (state == STATE_RADIO_IRQ_OFF);
1022 u32 reg;
1023
1024 /*
1025 * When interrupts are being enabled, the interrupt registers
1026 * should clear the register to assure a clean state.
1027 */
1028 if (state == STATE_RADIO_IRQ_ON) {
1029 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1030 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1031 }
1032
1033 /*
1034 * Only toggle the interrupts bits we are going to use.
1035 * Non-checked interrupt bits are disabled by default.
1036 */
1037 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1038 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1039 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1040 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1041 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1042 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1043 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1044 }
1045
1046 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1047 {
1048 /*
1049 * Initialize all registers.
1050 */
1051 if (rt2500pci_init_rings(rt2x00dev) ||
1052 rt2500pci_init_registers(rt2x00dev) ||
1053 rt2500pci_init_bbp(rt2x00dev)) {
1054 ERROR(rt2x00dev, "Register initialization failed.\n");
1055 return -EIO;
1056 }
1057
1058 /*
1059 * Enable interrupts.
1060 */
1061 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1062
1063 /*
1064 * Enable LED
1065 */
1066 rt2500pci_enable_led(rt2x00dev);
1067
1068 return 0;
1069 }
1070
1071 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1072 {
1073 u32 reg;
1074
1075 /*
1076 * Disable LED
1077 */
1078 rt2500pci_disable_led(rt2x00dev);
1079
1080 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1081
1082 /*
1083 * Disable synchronisation.
1084 */
1085 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1086
1087 /*
1088 * Cancel RX and TX.
1089 */
1090 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1091 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1092 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1093
1094 /*
1095 * Disable interrupts.
1096 */
1097 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1098 }
1099
1100 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1101 enum dev_state state)
1102 {
1103 u32 reg;
1104 unsigned int i;
1105 char put_to_sleep;
1106 char bbp_state;
1107 char rf_state;
1108
1109 put_to_sleep = (state != STATE_AWAKE);
1110
1111 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1112 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1113 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1114 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1115 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1116 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1117
1118 /*
1119 * Device is not guaranteed to be in the requested state yet.
1120 * We must wait until the register indicates that the
1121 * device has entered the correct state.
1122 */
1123 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1124 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1125 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1126 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1127 if (bbp_state == state && rf_state == state)
1128 return 0;
1129 msleep(10);
1130 }
1131
1132 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1133 "current device state: bbp %d and rf %d.\n",
1134 state, bbp_state, rf_state);
1135
1136 return -EBUSY;
1137 }
1138
1139 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1140 enum dev_state state)
1141 {
1142 int retval = 0;
1143
1144 switch (state) {
1145 case STATE_RADIO_ON:
1146 retval = rt2500pci_enable_radio(rt2x00dev);
1147 break;
1148 case STATE_RADIO_OFF:
1149 rt2500pci_disable_radio(rt2x00dev);
1150 break;
1151 case STATE_RADIO_RX_ON:
1152 case STATE_RADIO_RX_OFF:
1153 rt2500pci_toggle_rx(rt2x00dev, state);
1154 break;
1155 case STATE_DEEP_SLEEP:
1156 case STATE_SLEEP:
1157 case STATE_STANDBY:
1158 case STATE_AWAKE:
1159 retval = rt2500pci_set_state(rt2x00dev, state);
1160 break;
1161 default:
1162 retval = -ENOTSUPP;
1163 break;
1164 }
1165
1166 return retval;
1167 }
1168
1169 /*
1170 * TX descriptor initialization
1171 */
1172 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1173 struct data_desc *txd,
1174 struct txdata_entry_desc *desc,
1175 struct ieee80211_hdr *ieee80211hdr,
1176 unsigned int length,
1177 struct ieee80211_tx_control *control)
1178 {
1179 u32 word;
1180
1181 /*
1182 * Start writing the descriptor words.
1183 */
1184 rt2x00_desc_read(txd, 2, &word);
1185 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1186 rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1187 rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1188 rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1189 rt2x00_desc_write(txd, 2, word);
1190
1191 rt2x00_desc_read(txd, 3, &word);
1192 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1193 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1194 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1195 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1196 rt2x00_desc_write(txd, 3, word);
1197
1198 rt2x00_desc_read(txd, 10, &word);
1199 rt2x00_set_field32(&word, TXD_W10_RTS,
1200 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1201 rt2x00_desc_write(txd, 10, word);
1202
1203 rt2x00_desc_read(txd, 0, &word);
1204 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1205 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1206 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1207 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1208 rt2x00_set_field32(&word, TXD_W0_ACK,
1209 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1210 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1211 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1212 rt2x00_set_field32(&word, TXD_W0_OFDM,
1213 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1214 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1215 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1216 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1217 !!(control->flags &
1218 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1219 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1220 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1221 rt2x00_desc_write(txd, 0, word);
1222 }
1223
1224 /*
1225 * TX data initialization
1226 */
1227 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1228 unsigned int queue)
1229 {
1230 u32 reg;
1231
1232 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1233 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1234 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1235 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1236 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1237 }
1238 return;
1239 }
1240
1241 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1242 if (queue == IEEE80211_TX_QUEUE_DATA0)
1243 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1244 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1245 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1246 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1247 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1248 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1249 }
1250
1251 /*
1252 * RX control handlers
1253 */
1254 static void rt2500pci_fill_rxdone(struct data_entry *entry,
1255 struct rxdata_entry_desc *desc)
1256 {
1257 struct data_desc *rxd = entry->priv;
1258 u32 word0;
1259 u32 word2;
1260
1261 rt2x00_desc_read(rxd, 0, &word0);
1262 rt2x00_desc_read(rxd, 2, &word2);
1263
1264 desc->flags = 0;
1265 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1266 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1267 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1268 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1269
1270 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1271 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1272 entry->ring->rt2x00dev->rssi_offset;
1273 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1274 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1275 }
1276
1277 /*
1278 * Interrupt functions.
1279 */
1280 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1281 {
1282 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1283 struct data_entry *entry;
1284 struct data_desc *txd;
1285 u32 word;
1286 int tx_status;
1287 int retry;
1288
1289 while (!rt2x00_ring_empty(ring)) {
1290 entry = rt2x00_get_data_entry_done(ring);
1291 txd = entry->priv;
1292 rt2x00_desc_read(txd, 0, &word);
1293
1294 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1295 !rt2x00_get_field32(word, TXD_W0_VALID))
1296 break;
1297
1298 /*
1299 * Obtain the status about this packet.
1300 */
1301 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1302 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1303
1304 rt2x00lib_txdone(entry, tx_status, retry);
1305
1306 /*
1307 * Make this entry available for reuse.
1308 */
1309 entry->flags = 0;
1310 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1311 rt2x00_desc_write(txd, 0, word);
1312 rt2x00_ring_index_done_inc(ring);
1313 }
1314
1315 /*
1316 * If the data ring was full before the txdone handler
1317 * we must make sure the packet queue in the mac80211 stack
1318 * is reenabled when the txdone handler has finished.
1319 */
1320 entry = ring->entry;
1321 if (!rt2x00_ring_full(ring))
1322 ieee80211_wake_queue(rt2x00dev->hw,
1323 entry->tx_status.control.queue);
1324 }
1325
1326 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1327 {
1328 struct rt2x00_dev *rt2x00dev = dev_instance;
1329 u32 reg;
1330
1331 /*
1332 * Get the interrupt sources & saved to local variable.
1333 * Write register value back to clear pending interrupts.
1334 */
1335 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1336 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1337
1338 if (!reg)
1339 return IRQ_NONE;
1340
1341 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1342 return IRQ_HANDLED;
1343
1344 /*
1345 * Handle interrupts, walk through all bits
1346 * and run the tasks, the bits are checked in order of
1347 * priority.
1348 */
1349
1350 /*
1351 * 1 - Beacon timer expired interrupt.
1352 */
1353 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1354 rt2x00lib_beacondone(rt2x00dev);
1355
1356 /*
1357 * 2 - Rx ring done interrupt.
1358 */
1359 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1360 rt2x00pci_rxdone(rt2x00dev);
1361
1362 /*
1363 * 3 - Atim ring transmit done interrupt.
1364 */
1365 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1366 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1367
1368 /*
1369 * 4 - Priority ring transmit done interrupt.
1370 */
1371 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1372 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1373
1374 /*
1375 * 5 - Tx ring transmit done interrupt.
1376 */
1377 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1378 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1379
1380 return IRQ_HANDLED;
1381 }
1382
1383 /*
1384 * Device probe functions.
1385 */
1386 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1387 {
1388 struct eeprom_93cx6 eeprom;
1389 u32 reg;
1390 u16 word;
1391 u8 *mac;
1392
1393 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1394
1395 eeprom.data = rt2x00dev;
1396 eeprom.register_read = rt2500pci_eepromregister_read;
1397 eeprom.register_write = rt2500pci_eepromregister_write;
1398 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1399 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1400 eeprom.reg_data_in = 0;
1401 eeprom.reg_data_out = 0;
1402 eeprom.reg_data_clock = 0;
1403 eeprom.reg_chip_select = 0;
1404
1405 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1406 EEPROM_SIZE / sizeof(u16));
1407
1408 /*
1409 * Start validation of the data that has been read.
1410 */
1411 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1412 if (!is_valid_ether_addr(mac)) {
1413 DECLARE_MAC_BUF(macbuf);
1414
1415 random_ether_addr(mac);
1416 EEPROM(rt2x00dev, "MAC: %s\n",
1417 print_mac(macbuf, mac));
1418 }
1419
1420 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1421 if (word == 0xffff) {
1422 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1423 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
1424 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
1425 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
1426 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1427 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1428 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1429 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1430 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1431 }
1432
1433 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1434 if (word == 0xffff) {
1435 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1436 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1437 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1438 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1439 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1440 }
1441
1442 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1443 if (word == 0xffff) {
1444 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1445 DEFAULT_RSSI_OFFSET);
1446 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1447 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1448 }
1449
1450 return 0;
1451 }
1452
1453 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1454 {
1455 u32 reg;
1456 u16 value;
1457 u16 eeprom;
1458
1459 /*
1460 * Read EEPROM word for configuration.
1461 */
1462 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1463
1464 /*
1465 * Identify RF chipset.
1466 */
1467 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1468 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1469 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1470
1471 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1472 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1473 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1474 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1475 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1476 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1477 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1478 return -ENODEV;
1479 }
1480
1481 /*
1482 * Identify default antenna configuration.
1483 */
1484 rt2x00dev->hw->conf.antenna_sel_tx =
1485 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1486 rt2x00dev->hw->conf.antenna_sel_rx =
1487 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1488
1489 /*
1490 * Store led mode, for correct led behaviour.
1491 */
1492 rt2x00dev->led_mode =
1493 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1494
1495 /*
1496 * Detect if this device has an hardware controlled radio.
1497 */
1498 #ifdef CONFIG_RT2500PCI_RFKILL
1499 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1500 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1501 #endif /* CONFIG_RT2500PCI_RFKILL */
1502
1503 /*
1504 * Check if the BBP tuning should be enabled.
1505 */
1506 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1507
1508 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1509 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1510
1511 /*
1512 * Read the RSSI <-> dBm offset information.
1513 */
1514 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1515 rt2x00dev->rssi_offset =
1516 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1517
1518 return 0;
1519 }
1520
1521 /*
1522 * RF value list for RF2522
1523 * Supports: 2.4 GHz
1524 */
1525 static const struct rf_channel rf_vals_bg_2522[] = {
1526 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1527 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1528 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1529 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1530 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1531 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1532 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1533 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1534 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1535 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1536 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1537 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1538 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1539 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1540 };
1541
1542 /*
1543 * RF value list for RF2523
1544 * Supports: 2.4 GHz
1545 */
1546 static const struct rf_channel rf_vals_bg_2523[] = {
1547 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1548 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1549 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1550 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1551 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1552 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1553 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1554 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1555 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1556 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1557 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1558 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1559 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1560 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1561 };
1562
1563 /*
1564 * RF value list for RF2524
1565 * Supports: 2.4 GHz
1566 */
1567 static const struct rf_channel rf_vals_bg_2524[] = {
1568 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1569 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1570 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1571 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1572 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1573 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1574 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1575 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1576 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1577 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1578 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1579 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1580 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1581 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1582 };
1583
1584 /*
1585 * RF value list for RF2525
1586 * Supports: 2.4 GHz
1587 */
1588 static const struct rf_channel rf_vals_bg_2525[] = {
1589 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1590 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1591 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1592 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1593 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1594 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1595 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1596 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1597 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1598 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1599 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1600 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1601 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1602 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1603 };
1604
1605 /*
1606 * RF value list for RF2525e
1607 * Supports: 2.4 GHz
1608 */
1609 static const struct rf_channel rf_vals_bg_2525e[] = {
1610 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1611 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1612 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1613 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1614 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1615 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1616 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1617 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1618 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1619 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1620 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1621 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1622 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1623 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1624 };
1625
1626 /*
1627 * RF value list for RF5222
1628 * Supports: 2.4 GHz & 5.2 GHz
1629 */
1630 static const struct rf_channel rf_vals_5222[] = {
1631 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1632 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1633 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1634 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1635 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1636 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1637 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1638 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1639 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1640 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1641 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1642 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1643 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1644 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1645
1646 /* 802.11 UNI / HyperLan 2 */
1647 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1648 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1649 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1650 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1651 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1652 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1653 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1654 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1655
1656 /* 802.11 HyperLan 2 */
1657 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1658 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1659 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1660 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1661 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1662 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1663 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1664 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1665 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1666 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1667
1668 /* 802.11 UNII */
1669 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1670 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1671 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1672 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1673 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1674 };
1675
1676 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1677 {
1678 struct hw_mode_spec *spec = &rt2x00dev->spec;
1679 u8 *txpower;
1680 unsigned int i;
1681
1682 /*
1683 * Initialize all hw fields.
1684 */
1685 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1686 rt2x00dev->hw->extra_tx_headroom = 0;
1687 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1688 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1689 rt2x00dev->hw->queues = 2;
1690
1691 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1692 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1693 rt2x00_eeprom_addr(rt2x00dev,
1694 EEPROM_MAC_ADDR_0));
1695
1696 /*
1697 * Convert tx_power array in eeprom.
1698 */
1699 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1700 for (i = 0; i < 14; i++)
1701 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1702
1703 /*
1704 * Initialize hw_mode information.
1705 */
1706 spec->num_modes = 2;
1707 spec->num_rates = 12;
1708 spec->tx_power_a = NULL;
1709 spec->tx_power_bg = txpower;
1710 spec->tx_power_default = DEFAULT_TXPOWER;
1711
1712 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1713 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1714 spec->channels = rf_vals_bg_2522;
1715 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1716 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1717 spec->channels = rf_vals_bg_2523;
1718 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1719 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1720 spec->channels = rf_vals_bg_2524;
1721 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1722 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1723 spec->channels = rf_vals_bg_2525;
1724 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1725 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1726 spec->channels = rf_vals_bg_2525e;
1727 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1728 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1729 spec->channels = rf_vals_5222;
1730 spec->num_modes = 3;
1731 }
1732 }
1733
1734 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1735 {
1736 int retval;
1737
1738 /*
1739 * Allocate eeprom data.
1740 */
1741 retval = rt2500pci_validate_eeprom(rt2x00dev);
1742 if (retval)
1743 return retval;
1744
1745 retval = rt2500pci_init_eeprom(rt2x00dev);
1746 if (retval)
1747 return retval;
1748
1749 /*
1750 * Initialize hw specifications.
1751 */
1752 rt2500pci_probe_hw_mode(rt2x00dev);
1753
1754 /*
1755 * This device requires the beacon ring
1756 */
1757 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1758
1759 /*
1760 * Set the rssi offset.
1761 */
1762 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1763
1764 return 0;
1765 }
1766
1767 /*
1768 * IEEE80211 stack callback functions.
1769 */
1770 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1771 unsigned int changed_flags,
1772 unsigned int *total_flags,
1773 int mc_count,
1774 struct dev_addr_list *mc_list)
1775 {
1776 struct rt2x00_dev *rt2x00dev = hw->priv;
1777 struct interface *intf = &rt2x00dev->interface;
1778 u32 reg;
1779
1780 /*
1781 * Mask off any flags we are going to ignore from
1782 * the total_flags field.
1783 */
1784 *total_flags &=
1785 FIF_ALLMULTI |
1786 FIF_FCSFAIL |
1787 FIF_PLCPFAIL |
1788 FIF_CONTROL |
1789 FIF_OTHER_BSS |
1790 FIF_PROMISC_IN_BSS;
1791
1792 /*
1793 * Apply some rules to the filters:
1794 * - Some filters imply different filters to be set.
1795 * - Some things we can't filter out at all.
1796 * - Some filters are set based on interface type.
1797 */
1798 if (mc_count)
1799 *total_flags |= FIF_ALLMULTI;
1800 if (*total_flags & FIF_OTHER_BSS ||
1801 *total_flags & FIF_PROMISC_IN_BSS)
1802 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1803 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1804 *total_flags |= FIF_PROMISC_IN_BSS;
1805
1806 /*
1807 * Check if there is any work left for us.
1808 */
1809 if (intf->filter == *total_flags)
1810 return;
1811 intf->filter = *total_flags;
1812
1813 /*
1814 * Start configuration steps.
1815 * Note that the version error will always be dropped
1816 * and broadcast frames will always be accepted since
1817 * there is no filter for it at this time.
1818 */
1819 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1820 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1821 !(*total_flags & FIF_FCSFAIL));
1822 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1823 !(*total_flags & FIF_PLCPFAIL));
1824 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1825 !(*total_flags & FIF_CONTROL));
1826 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1827 !(*total_flags & FIF_PROMISC_IN_BSS));
1828 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1829 !(*total_flags & FIF_PROMISC_IN_BSS));
1830 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1831 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1832 !(*total_flags & FIF_ALLMULTI));
1833 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1834 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1835 }
1836
1837 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1838 u32 short_retry, u32 long_retry)
1839 {
1840 struct rt2x00_dev *rt2x00dev = hw->priv;
1841 u32 reg;
1842
1843 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1844 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1845 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1846 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1847
1848 return 0;
1849 }
1850
1851 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1852 {
1853 struct rt2x00_dev *rt2x00dev = hw->priv;
1854 u64 tsf;
1855 u32 reg;
1856
1857 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1858 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1859 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1860 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1861
1862 return tsf;
1863 }
1864
1865 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1866 {
1867 struct rt2x00_dev *rt2x00dev = hw->priv;
1868
1869 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1870 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1871 }
1872
1873 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1874 {
1875 struct rt2x00_dev *rt2x00dev = hw->priv;
1876 u32 reg;
1877
1878 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1879 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1880 }
1881
1882 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1883 .tx = rt2x00mac_tx,
1884 .start = rt2x00mac_start,
1885 .stop = rt2x00mac_stop,
1886 .add_interface = rt2x00mac_add_interface,
1887 .remove_interface = rt2x00mac_remove_interface,
1888 .config = rt2x00mac_config,
1889 .config_interface = rt2x00mac_config_interface,
1890 .configure_filter = rt2500pci_configure_filter,
1891 .get_stats = rt2x00mac_get_stats,
1892 .set_retry_limit = rt2500pci_set_retry_limit,
1893 .erp_ie_changed = rt2x00mac_erp_ie_changed,
1894 .conf_tx = rt2x00mac_conf_tx,
1895 .get_tx_stats = rt2x00mac_get_tx_stats,
1896 .get_tsf = rt2500pci_get_tsf,
1897 .reset_tsf = rt2500pci_reset_tsf,
1898 .beacon_update = rt2x00pci_beacon_update,
1899 .tx_last_beacon = rt2500pci_tx_last_beacon,
1900 };
1901
1902 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1903 .irq_handler = rt2500pci_interrupt,
1904 .probe_hw = rt2500pci_probe_hw,
1905 .initialize = rt2x00pci_initialize,
1906 .uninitialize = rt2x00pci_uninitialize,
1907 .set_device_state = rt2500pci_set_device_state,
1908 .rfkill_poll = rt2500pci_rfkill_poll,
1909 .link_stats = rt2500pci_link_stats,
1910 .reset_tuner = rt2500pci_reset_tuner,
1911 .link_tuner = rt2500pci_link_tuner,
1912 .write_tx_desc = rt2500pci_write_tx_desc,
1913 .write_tx_data = rt2x00pci_write_tx_data,
1914 .kick_tx_queue = rt2500pci_kick_tx_queue,
1915 .fill_rxdone = rt2500pci_fill_rxdone,
1916 .config_mac_addr = rt2500pci_config_mac_addr,
1917 .config_bssid = rt2500pci_config_bssid,
1918 .config_type = rt2500pci_config_type,
1919 .config_preamble = rt2500pci_config_preamble,
1920 .config = rt2500pci_config,
1921 };
1922
1923 static const struct rt2x00_ops rt2500pci_ops = {
1924 .name = DRV_NAME,
1925 .rxd_size = RXD_DESC_SIZE,
1926 .txd_size = TXD_DESC_SIZE,
1927 .eeprom_size = EEPROM_SIZE,
1928 .rf_size = RF_SIZE,
1929 .lib = &rt2500pci_rt2x00_ops,
1930 .hw = &rt2500pci_mac80211_ops,
1931 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1932 .debugfs = &rt2500pci_rt2x00debug,
1933 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1934 };
1935
1936 /*
1937 * RT2500pci module information.
1938 */
1939 static struct pci_device_id rt2500pci_device_table[] = {
1940 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1941 { 0, }
1942 };
1943
1944 MODULE_AUTHOR(DRV_PROJECT);
1945 MODULE_VERSION(DRV_VERSION);
1946 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1947 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1948 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1949 MODULE_LICENSE("GPL");
1950
1951 static struct pci_driver rt2500pci_driver = {
1952 .name = DRV_NAME,
1953 .id_table = rt2500pci_device_table,
1954 .probe = rt2x00pci_probe,
1955 .remove = __devexit_p(rt2x00pci_remove),
1956 .suspend = rt2x00pci_suspend,
1957 .resume = rt2x00pci_resume,
1958 };
1959
1960 static int __init rt2500pci_init(void)
1961 {
1962 return pci_register_driver(&rt2500pci_driver);
1963 }
1964
1965 static void __exit rt2500pci_exit(void)
1966 {
1967 pci_unregister_driver(&rt2500pci_driver);
1968 }
1969
1970 module_init(rt2500pci_init);
1971 module_exit(rt2500pci_exit);
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