| blob | b18d56e73cf1cf8c5a5ed7d2316bf9f67e8802d1 |
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt2500usb
23 Abstract: Data structures and registers for the rt2500usb module.
24 Supported chipsets: RT2570.
25 */
27 #ifndef RT2500USB_H
28 #define RT2500USB_H
30 /*
31 * RF chip defines.
32 */
33 #define RF2522 0x0000
34 #define RF2523 0x0001
35 #define RF2524 0x0002
36 #define RF2525 0x0003
37 #define RF2525E 0x0005
38 #define RF5222 0x0010
40 /*
41 * RT2570 version
42 */
43 #define RT2570_VERSION_B 2
44 #define RT2570_VERSION_C 3
45 #define RT2570_VERSION_D 4
47 /*
48 * Signal information.
49 * Defaul offset is required for RSSI <-> dBm conversion.
50 */
51 #define MAX_SIGNAL 100
52 #define MAX_RX_SSI -1
53 #define DEFAULT_RSSI_OFFSET 120
55 /*
56 * Register layout information.
57 */
58 #define CSR_REG_BASE 0x0400
59 #define CSR_REG_SIZE 0x0100
60 #define EEPROM_BASE 0x0000
61 #define EEPROM_SIZE 0x006a
62 #define BBP_SIZE 0x0060
63 #define RF_SIZE 0x0014
65 /*
66 * Control/Status Registers(CSR).
67 * Some values are set in TU, whereas 1 TU == 1024 us.
68 */
70 /*
71 * MAC_CSR0: ASIC revision number.
72 */
73 #define MAC_CSR0 0x0400
75 /*
76 * MAC_CSR1: System control.
77 * SOFT_RESET: Software reset, 1: reset, 0: normal.
78 * BBP_RESET: Hardware reset, 1: reset, 0, release.
79 * HOST_READY: Host ready after initialization.
80 */
81 #define MAC_CSR1 0x0402
82 #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
83 #define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
84 #define MAC_CSR1_HOST_READY FIELD16(0x00000004)
86 /*
87 * MAC_CSR2: STA MAC register 0.
88 */
89 #define MAC_CSR2 0x0404
90 #define MAC_CSR2_BYTE0 FIELD16(0x00ff)
91 #define MAC_CSR2_BYTE1 FIELD16(0xff00)
93 /*
94 * MAC_CSR3: STA MAC register 1.
95 */
96 #define MAC_CSR3 0x0406
97 #define MAC_CSR3_BYTE2 FIELD16(0x00ff)
98 #define MAC_CSR3_BYTE3 FIELD16(0xff00)
100 /*
101 * MAC_CSR4: STA MAC register 2.
102 */
103 #define MAC_CSR4 0X0408
104 #define MAC_CSR4_BYTE4 FIELD16(0x00ff)
105 #define MAC_CSR4_BYTE5 FIELD16(0xff00)
107 /*
108 * MAC_CSR5: BSSID register 0.
109 */
110 #define MAC_CSR5 0x040a
111 #define MAC_CSR5_BYTE0 FIELD16(0x00ff)
112 #define MAC_CSR5_BYTE1 FIELD16(0xff00)
114 /*
115 * MAC_CSR6: BSSID register 1.
116 */
117 #define MAC_CSR6 0x040c
118 #define MAC_CSR6_BYTE2 FIELD16(0x00ff)
119 #define MAC_CSR6_BYTE3 FIELD16(0xff00)
121 /*
122 * MAC_CSR7: BSSID register 2.
123 */
124 #define MAC_CSR7 0x040e
125 #define MAC_CSR7_BYTE4 FIELD16(0x00ff)
126 #define MAC_CSR7_BYTE5 FIELD16(0xff00)
128 /*
129 * MAC_CSR8: Max frame length.
130 */
131 #define MAC_CSR8 0x0410
132 #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
134 /*
135 * Misc MAC_CSR registers.
136 * MAC_CSR9: Timer control.
137 * MAC_CSR10: Slot time.
138 * MAC_CSR11: IFS.
139 * MAC_CSR12: EIFS.
140 * MAC_CSR13: Power mode0.
141 * MAC_CSR14: Power mode1.
142 * MAC_CSR15: Power saving transition0
143 * MAC_CSR16: Power saving transition1
144 */
145 #define MAC_CSR9 0x0412
146 #define MAC_CSR10 0x0414
147 #define MAC_CSR11 0x0416
148 #define MAC_CSR12 0x0418
149 #define MAC_CSR13 0x041a
150 #define MAC_CSR14 0x041c
151 #define MAC_CSR15 0x041e
152 #define MAC_CSR16 0x0420
154 /*
155 * MAC_CSR17: Manual power control / status register.
156 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
157 * SET_STATE: Set state. Write 1 to trigger, self cleared.
158 * BBP_DESIRE_STATE: BBP desired state.
159 * RF_DESIRE_STATE: RF desired state.
160 * BBP_CURRENT_STATE: BBP current state.
161 * RF_CURRENT_STATE: RF current state.
162 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
163 */
164 #define MAC_CSR17 0x0422
165 #define MAC_CSR17_SET_STATE FIELD16(0x0001)
166 #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
167 #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
168 #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
169 #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
170 #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
172 /*
173 * MAC_CSR18: Wakeup timer register.
174 * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
175 * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
176 * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
177 */
178 #define MAC_CSR18 0x0424
179 #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
180 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
181 #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
183 /*
184 * MAC_CSR19: GPIO control register.
185 */
186 #define MAC_CSR19 0x0426
188 /*
189 * MAC_CSR20: LED control register.
190 * ACTIVITY: 0: idle, 1: active.
191 * LINK: 0: linkoff, 1: linkup.
192 * ACTIVITY_POLARITY: 0: active low, 1: active high.
193 */
194 #define MAC_CSR20 0x0428
195 #define MAC_CSR20_ACTIVITY FIELD16(0x0001)
196 #define MAC_CSR20_LINK FIELD16(0x0002)
197 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
199 /*
200 * MAC_CSR21: LED control register.
201 * ON_PERIOD: On period, default 70ms.
202 * OFF_PERIOD: Off period, default 30ms.
203 */
204 #define MAC_CSR21 0x042a
205 #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
206 #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
208 /*
209 * Collision window control register.
210 */
211 #define MAC_CSR22 0x042c
213 /*
214 * Transmit related CSRs.
215 * Some values are set in TU, whereas 1 TU == 1024 us.
216 */
218 /*
219 * TXRX_CSR0: Security control register.
220 */
221 #define TXRX_CSR0 0x0440
222 #define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
223 #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
224 #define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
226 /*
227 * TXRX_CSR1: TX configuration.
228 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
229 * TSF_OFFSET: TSF offset in MAC header.
230 * AUTO_SEQUENCE: Let ASIC control frame sequence number.
231 */
232 #define TXRX_CSR1 0x0442
233 #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
234 #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
235 #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
237 /*
238 * TXRX_CSR2: RX control.
239 * DISABLE_RX: Disable rx engine.
240 * DROP_CRC: Drop crc error.
241 * DROP_PHYSICAL: Drop physical error.
242 * DROP_CONTROL: Drop control frame.
243 * DROP_NOT_TO_ME: Drop not to me unicast frame.
244 * DROP_TODS: Drop frame tods bit is true.
245 * DROP_VERSION_ERROR: Drop version error frame.
246 * DROP_MCAST: Drop multicast frames.
247 * DROP_BCAST: Drop broadcast frames.
248 */
249 #define TXRX_CSR2 0x0444
250 #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
251 #define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
252 #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
253 #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
254 #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
255 #define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
256 #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
257 #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
258 #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
260 /*
261 * RX BBP ID registers
262 * TXRX_CSR3: CCK RX BBP ID.
263 * TXRX_CSR4: OFDM RX BBP ID.
264 */
265 #define TXRX_CSR3 0x0446
266 #define TXRX_CSR4 0x0448
268 /*
269 * TXRX_CSR5: CCK TX BBP ID0.
270 */
271 #define TXRX_CSR5 0x044a
272 #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
273 #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
274 #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
275 #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
277 /*
278 * TXRX_CSR6: CCK TX BBP ID1.
279 */
280 #define TXRX_CSR6 0x044c
281 #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
282 #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
283 #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
284 #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
286 /*
287 * TXRX_CSR7: OFDM TX BBP ID0.
288 */
289 #define TXRX_CSR7 0x044e
290 #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
291 #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
292 #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
293 #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
295 /*
296 * TXRX_CSR5: OFDM TX BBP ID1.
297 */
298 #define TXRX_CSR8 0x0450
299 #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
300 #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
301 #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
302 #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
304 /*
305 * TXRX_CSR9: TX ACK time-out.
306 */
307 #define TXRX_CSR9 0x0452
309 /*
310 * TXRX_CSR10: Auto responder control.
311 */
312 #define TXRX_CSR10 0x0454
313 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
315 /*
316 * TXRX_CSR11: Auto responder basic rate.
317 */
318 #define TXRX_CSR11 0x0456
320 /*
321 * ACK/CTS time registers.
322 */
323 #define TXRX_CSR12 0x0458
324 #define TXRX_CSR13 0x045a
325 #define TXRX_CSR14 0x045c
326 #define TXRX_CSR15 0x045e
327 #define TXRX_CSR16 0x0460
328 #define TXRX_CSR17 0x0462
330 /*
331 * TXRX_CSR18: Synchronization control register.
332 */
333 #define TXRX_CSR18 0x0464
334 #define TXRX_CSR18_OFFSET FIELD16(0x000f)
335 #define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
337 /*
338 * TXRX_CSR19: Synchronization control register.
339 * TSF_COUNT: Enable TSF auto counting.
340 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
341 * TBCN: Enable Tbcn with reload value.
342 * BEACON_GEN: Enable beacon generator.
343 */
344 #define TXRX_CSR19 0x0466
345 #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
346 #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
347 #define TXRX_CSR19_TBCN FIELD16(0x0008)
348 #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
350 /*
351 * TXRX_CSR20: Tx BEACON offset time control register.
352 * OFFSET: In units of usec.
353 * BCN_EXPECT_WINDOW: Default: 2^CWmin
354 */
355 #define TXRX_CSR20 0x0468
356 #define TXRX_CSR20_OFFSET FIELD16(0x1fff)
357 #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
359 /*
360 * TXRX_CSR21
361 */
362 #define TXRX_CSR21 0x046a
364 /*
365 * Encryption related CSRs.
366 *
367 */
369 /*
370 * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
371 */
372 #define SEC_CSR0 0x0480
373 #define SEC_CSR1 0x0482
374 #define SEC_CSR2 0x0484
375 #define SEC_CSR3 0x0486
376 #define SEC_CSR4 0x0488
377 #define SEC_CSR5 0x048a
378 #define SEC_CSR6 0x048c
379 #define SEC_CSR7 0x048e
381 /*
382 * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
383 */
384 #define SEC_CSR8 0x0490
385 #define SEC_CSR9 0x0492
386 #define SEC_CSR10 0x0494
387 #define SEC_CSR11 0x0496
388 #define SEC_CSR12 0x0498
389 #define SEC_CSR13 0x049a
390 #define SEC_CSR14 0x049c
391 #define SEC_CSR15 0x049e
393 /*
394 * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
395 */
396 #define SEC_CSR16 0x04a0
397 #define SEC_CSR17 0x04a2
398 #define SEC_CSR18 0X04A4
399 #define SEC_CSR19 0x04a6
400 #define SEC_CSR20 0x04a8
401 #define SEC_CSR21 0x04aa
402 #define SEC_CSR22 0x04ac
403 #define SEC_CSR23 0x04ae
405 /*
406 * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
407 */
408 #define SEC_CSR24 0x04b0
409 #define SEC_CSR25 0x04b2
410 #define SEC_CSR26 0x04b4
411 #define SEC_CSR27 0x04b6
412 #define SEC_CSR28 0x04b8
413 #define SEC_CSR29 0x04ba
414 #define SEC_CSR30 0x04bc
415 #define SEC_CSR31 0x04be
417 /*
418 * PHY control registers.
419 */
421 /*
422 * PHY_CSR0: RF switching timing control.
423 */
424 #define PHY_CSR0 0x04c0
426 /*
427 * PHY_CSR1: TX PA configuration.
428 */
429 #define PHY_CSR1 0x04c2
431 /*
432 * MAC configuration registers.
433 * PHY_CSR2: TX MAC configuration.
434 * PHY_CSR3: RX MAC configuration.
435 */
436 #define PHY_CSR2 0x04c4
437 #define PHY_CSR3 0x04c6
439 /*
440 * PHY_CSR4: Interface configuration.
441 */
442 #define PHY_CSR4 0x04c8
443 #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
445 /*
446 * BBP pre-TX registers.
447 * PHY_CSR5: BBP pre-TX CCK.
448 */
449 #define PHY_CSR5 0x04ca
450 #define PHY_CSR5_CCK FIELD16(0x0003)
451 #define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
453 /*
454 * BBP pre-TX registers.
455 * PHY_CSR6: BBP pre-TX OFDM.
456 */
457 #define PHY_CSR6 0x04cc
458 #define PHY_CSR6_OFDM FIELD16(0x0003)
459 #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
461 /*
462 * PHY_CSR7: BBP access register 0.
463 * BBP_DATA: BBP data.
464 * BBP_REG_ID: BBP register ID.
465 * BBP_READ_CONTROL: 0: write, 1: read.
466 */
467 #define PHY_CSR7 0x04ce
468 #define PHY_CSR7_DATA FIELD16(0x00ff)
469 #define PHY_CSR7_REG_ID FIELD16(0x7f00)
470 #define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
472 /*
473 * PHY_CSR8: BBP access register 1.
474 * BBP_BUSY: ASIC is busy execute BBP programming.
475 */
476 #define PHY_CSR8 0x04d0
477 #define PHY_CSR8_BUSY FIELD16(0x0001)
479 /*
480 * PHY_CSR9: RF access register.
481 * RF_VALUE: Register value + id to program into rf/if.
482 */
483 #define PHY_CSR9 0x04d2
484 #define PHY_CSR9_RF_VALUE FIELD16(0xffff)
486 /*
487 * PHY_CSR10: RF access register.
488 * RF_VALUE: Register value + id to program into rf/if.
489 * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
490 * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
491 * RF_PLL_LD: Rf pll_ld status.
492 * RF_BUSY: 1: asic is busy execute rf programming.
493 */
494 #define PHY_CSR10 0x04d4
495 #define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
496 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
497 #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
498 #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
499 #define PHY_CSR10_RF_BUSY FIELD16(0x8000)
501 /*
502 * STA_CSR0: FCS error count.
503 * FCS_ERROR: FCS error count, cleared when read.
504 */
505 #define STA_CSR0 0x04e0
506 #define STA_CSR0_FCS_ERROR FIELD16(0xffff)
508 /*
509 * STA_CSR1: PLCP error count.
510 */
511 #define STA_CSR1 0x04e2
513 /*
514 * STA_CSR2: LONG error count.
515 */
516 #define STA_CSR2 0x04e4
518 /*
519 * STA_CSR3: CCA false alarm.
520 * FALSE_CCA_ERROR: False CCA error count, cleared when read.
521 */
522 #define STA_CSR3 0x04e6
523 #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
525 /*
526 * STA_CSR4: RX FIFO overflow.
527 */
528 #define STA_CSR4 0x04e8
530 /*
531 * STA_CSR5: Beacon sent counter.
532 */
533 #define STA_CSR5 0x04ea
535 /*
536 * Statistics registers
537 */
538 #define STA_CSR6 0x04ec
539 #define STA_CSR7 0x04ee
540 #define STA_CSR8 0x04f0
541 #define STA_CSR9 0x04f2
542 #define STA_CSR10 0x04f4
544 /*
545 * BBP registers.
546 * The wordsize of the BBP is 8 bits.
547 */
549 /*
550 * R2: TX antenna control
551 */
552 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
553 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
555 /*
556 * R14: RX antenna control
557 */
558 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
559 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
561 /*
562 * RF registers.
563 */
565 /*
566 * RF 1
567 */
568 #define RF1_TUNER FIELD32(0x00020000)
570 /*
571 * RF 3
572 */
573 #define RF3_TUNER FIELD32(0x00000100)
574 #define RF3_TXPOWER FIELD32(0x00003e00)
576 /*
577 * EEPROM contents.
578 */
580 /*
581 * HW MAC address.
582 */
583 #define EEPROM_MAC_ADDR_0 0x0002
584 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
585 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
586 #define EEPROM_MAC_ADDR1 0x0003
587 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
588 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
589 #define EEPROM_MAC_ADDR_2 0x0004
590 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
591 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
593 /*
594 * EEPROM antenna.
595 * ANTENNA_NUM: Number of antenna's.
596 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
597 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
598 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
599 * DYN_TXAGC: Dynamic TX AGC control.
600 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
601 * RF_TYPE: Rf_type of this adapter.
602 */
603 #define EEPROM_ANTENNA 0x000b
604 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
605 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
606 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
607 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
608 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
609 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
610 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
612 /*
613 * EEPROM NIC config.
614 * CARDBUS_ACCEL: 0: enable, 1: disable.
615 * DYN_BBP_TUNE: 0: enable, 1: disable.
616 * CCK_TX_POWER: CCK TX power compensation.
617 */
618 #define EEPROM_NIC 0x000c
619 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
620 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
621 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
623 /*
624 * EEPROM geography.
625 * GEO: Default geography setting for device.
626 */
627 #define EEPROM_GEOGRAPHY 0x000d
628 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
630 /*
631 * EEPROM BBP.
632 */
633 #define EEPROM_BBP_START 0x000e
634 #define EEPROM_BBP_SIZE 16
635 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
636 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
638 /*
639 * EEPROM TXPOWER
640 */
641 #define EEPROM_TXPOWER_START 0x001e
642 #define EEPROM_TXPOWER_SIZE 7
643 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
644 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
646 /*
647 * EEPROM Tuning threshold
648 */
649 #define EEPROM_BBPTUNE 0x0030
650 #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
652 /*
653 * EEPROM BBP R24 Tuning.
654 */
655 #define EEPROM_BBPTUNE_R24 0x0031
656 #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
657 #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
659 /*
660 * EEPROM BBP R25 Tuning.
661 */
662 #define EEPROM_BBPTUNE_R25 0x0032
663 #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
664 #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
666 /*
667 * EEPROM BBP R24 Tuning.
668 */
669 #define EEPROM_BBPTUNE_R61 0x0033
670 #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
671 #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
673 /*
674 * EEPROM BBP VGC Tuning.
675 */
676 #define EEPROM_BBPTUNE_VGC 0x0034
677 #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
679 /*
680 * EEPROM BBP R17 Tuning.
681 */
682 #define EEPROM_BBPTUNE_R17 0x0035
683 #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
684 #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
686 /*
687 * RSSI <-> dBm offset calibration
688 */
689 #define EEPROM_CALIBRATE_OFFSET 0x0036
690 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
692 /*
693 * DMA descriptor defines.
694 */
695 #define TXD_DESC_SIZE ( 5 * sizeof(struct data_desc) )
696 #define RXD_DESC_SIZE ( 4 * sizeof(struct data_desc) )
698 /*
699 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
700 */
702 /*
703 * Word0
704 */
705 #define TXD_W0_PACKET_ID FIELD32(0x0000000f)
706 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
707 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
708 #define TXD_W0_ACK FIELD32(0x00000200)
709 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
710 #define TXD_W0_OFDM FIELD32(0x00000800)
711 #define TXD_W0_NEW_SEQ FIELD32(0x00001000)
712 #define TXD_W0_IFS FIELD32(0x00006000)
713 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
714 #define TXD_W0_CIPHER FIELD32(0x20000000)
715 #define TXD_W0_KEY_ID FIELD32(0xc0000000)
717 /*
718 * Word1
719 */
720 #define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
721 #define TXD_W1_AIFS FIELD32(0x000000c0)
722 #define TXD_W1_CWMIN FIELD32(0x00000f00)
723 #define TXD_W1_CWMAX FIELD32(0x0000f000)
725 /*
726 * Word2: PLCP information
727 */
728 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
729 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
730 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
731 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
733 /*
734 * Word3
735 */
736 #define TXD_W3_IV FIELD32(0xffffffff)
738 /*
739 * Word4
740 */
741 #define TXD_W4_EIV FIELD32(0xffffffff)
743 /*
744 * RX descriptor format for RX Ring.
745 */
747 /*
748 * Word0
749 */
750 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
751 #define RXD_W0_MULTICAST FIELD32(0x00000004)
752 #define RXD_W0_BROADCAST FIELD32(0x00000008)
753 #define RXD_W0_MY_BSS FIELD32(0x00000010)
754 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
755 #define RXD_W0_OFDM FIELD32(0x00000040)
756 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
757 #define RXD_W0_CIPHER FIELD32(0x00000100)
758 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
759 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
761 /*
762 * Word1
763 */
764 #define RXD_W1_RSSI FIELD32(0x000000ff)
765 #define RXD_W1_SIGNAL FIELD32(0x0000ff00)
767 /*
768 * Word2
769 */
770 #define RXD_W2_IV FIELD32(0xffffffff)
772 /*
773 * Word3
774 */
775 #define RXD_W3_EIV FIELD32(0xffffffff)
777 /*
778 * Macro's for converting txpower from EEPROM to dscape value
779 * and from dscape value to register value.
780 */
781 #define MIN_TXPOWER 0
782 #define MAX_TXPOWER 31
783 #define DEFAULT_TXPOWER 24
785 #define TXPOWER_FROM_DEV(__txpower) \
786 ({ \
787 ((__txpower) > MAX_TXPOWER) ? \
788 DEFAULT_TXPOWER : (__txpower); \
789 })
791 #define TXPOWER_TO_DEV(__txpower) \
792 ({ \
793 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
794 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
795 (__txpower)); \
796 })