drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           reclaim;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 struct ehci_hcd {                       /* one per controller */
  66         /* glue to PCI and HCD framework */
  67         struct ehci_caps __iomem *caps;
  68         struct ehci_regs __iomem *regs;
  69         struct ehci_dbg_port __iomem *debug;
  70
  71         __u32                   hcs_params;     /* cached register copy */
  72         spinlock_t              lock;
  73
  74         /* async schedule support */
  75         struct ehci_qh          *async;
  76         struct ehci_qh          *reclaim;
  77         unsigned                reclaim_ready : 1;
  78         unsigned                scanning : 1;
  79
  80         /* periodic schedule support */
  81 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  82         unsigned                periodic_size;
  83         __hc32                  *periodic;      /* hw periodic table */
  84         dma_addr_t              periodic_dma;
  85         unsigned                i_thresh;       /* uframes HC might cache */
  86
  87         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  88         int                     next_uframe;    /* scan periodic, start here */
  89         unsigned                periodic_sched; /* periodic activity count */
  90
  91         /* per root hub port */
  92         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  93
  94         /* bit vectors (one bit per port) */
  95         unsigned long           bus_suspended;          /* which ports were
  96                         already suspended at the start of a bus suspend */
  97         unsigned long           companion_ports;        /* which ports are
  98                         dedicated to the companion controller */
  99         unsigned long           owned_ports;            /* which ports are
 100                         owned by the companion during a bus suspend */
 101
 102         /* per-HC memory pools (could be per-bus, but ...) */
 103         struct dma_pool         *qh_pool;       /* qh per active urb */
 104         struct dma_pool         *qtd_pool;      /* one or more per qh */
 105         struct dma_pool         *itd_pool;      /* itd per iso urb */
 106         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 107
 108         struct timer_list       watchdog;
 109         unsigned long           actions;
 110         unsigned                stamp;
 111         unsigned long           next_statechange;
 112         u32                     command;
 113
 114         /* SILICON QUIRKS */
 115         unsigned                is_tdi_rh_tt:1; /* TDI roothub with TT */
 116         unsigned                no_selective_suspend:1;
 117         unsigned                has_fsl_port_bug:1; /* FreeScale */
 118         unsigned                big_endian_mmio:1;
 119         unsigned                big_endian_desc:1;
 120
 121         u8                      sbrn;           /* packed release number */
 122
 123         /* irq statistics */
 124 #ifdef EHCI_STATS
 125         struct ehci_stats       stats;
 126 #       define COUNT(x) do { (x)++; } while (0)
 127 #else
 128 #       define COUNT(x) do {} while (0)
 129 #endif
 130 };
 131
 132 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 133 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 134 {
 135         return (struct ehci_hcd *) (hcd->hcd_priv);
 136 }
 137 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 138 {
 139         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 140 }
 141
 142
 143 enum ehci_timer_action {
 144         TIMER_IO_WATCHDOG,
 145         TIMER_IAA_WATCHDOG,
 146         TIMER_ASYNC_SHRINK,
 147         TIMER_ASYNC_OFF,
 148 };
 149
 150 static inline void
 151 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 152 {
 153         clear_bit (action, &ehci->actions);
 154 }
 155
 156 static inline void
 157 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 158 {
 159         if (!test_and_set_bit (action, &ehci->actions)) {
 160                 unsigned long t;
 161
 162                 switch (action) {
 163                 case TIMER_IAA_WATCHDOG:
 164                         t = EHCI_IAA_JIFFIES;
 165                         break;
 166                 case TIMER_IO_WATCHDOG:
 167                         t = EHCI_IO_JIFFIES;
 168                         break;
 169                 case TIMER_ASYNC_OFF:
 170                         t = EHCI_ASYNC_JIFFIES;
 171                         break;
 172                 // case TIMER_ASYNC_SHRINK:
 173                 default:
 174                         t = EHCI_SHRINK_JIFFIES;
 175                         break;
 176                 }
 177                 t += jiffies;
 178                 // all timings except IAA watchdog can be overridden.
 179                 // async queue SHRINK often precedes IAA.  while it's ready
 180                 // to go OFF neither can matter, and afterwards the IO
 181                 // watchdog stops unless there's still periodic traffic.
 182                 if (action != TIMER_IAA_WATCHDOG
 183                                 && t > ehci->watchdog.expires
 184                                 && timer_pending (&ehci->watchdog))
 185                         return;
 186                 mod_timer (&ehci->watchdog, t);
 187         }
 188 }
 189
 190 /*-------------------------------------------------------------------------*/
 191
 192 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 193
 194 /* Section 2.2 Host Controller Capability Registers */
 195 struct ehci_caps {
 196         /* these fields are specified as 8 and 16 bit registers,
 197          * but some hosts can't perform 8 or 16 bit PCI accesses.
 198          */
 199         u32             hc_capbase;
 200 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 201 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 202         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 203 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 204 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 205 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 206 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 207 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 208 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 209 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 210
 211         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 212 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 213 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 214 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 215 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 216 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 217 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 218         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 219 } __attribute__ ((packed));
 220
 221
 222 /* Section 2.3 Host Controller Operational Registers */
 223 struct ehci_regs {
 224
 225         /* USBCMD: offset 0x00 */
 226         u32             command;
 227 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 228 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 229 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 230 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 231 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 232 #define CMD_ASE         (1<<5)          /* async schedule enable */
 233 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 234 /* 3:2 is periodic frame list size */
 235 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 236 #define CMD_RUN         (1<<0)          /* start/stop HC */
 237
 238         /* USBSTS: offset 0x04 */
 239         u32             status;
 240 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 241 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 242 #define STS_RECL        (1<<13)         /* Reclamation */
 243 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 244 /* some bits reserved */
 245         /* these STS_* flags are also intr_enable bits (USBINTR) */
 246 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 247 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 248 #define STS_FLR         (1<<3)          /* frame list rolled over */
 249 #define STS_PCD         (1<<2)          /* port change detect */
 250 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 251 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 252
 253         /* USBINTR: offset 0x08 */
 254         u32             intr_enable;
 255
 256         /* FRINDEX: offset 0x0C */
 257         u32             frame_index;    /* current microframe number */
 258         /* CTRLDSSEGMENT: offset 0x10 */
 259         u32             segment;        /* address bits 63:32 if needed */
 260         /* PERIODICLISTBASE: offset 0x14 */
 261         u32             frame_list;     /* points to periodic list */
 262         /* ASYNCLISTADDR: offset 0x18 */
 263         u32             async_next;     /* address of next async queue head */
 264
 265         u32             reserved [9];
 266
 267         /* CONFIGFLAG: offset 0x40 */
 268         u32             configured_flag;
 269 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 270
 271         /* PORTSC: offset 0x44 */
 272         u32             port_status [0];        /* up to N_PORTS */
 273 /* 31:23 reserved */
 274 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 275 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 276 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 277 /* 19:16 for port testing */
 278 #define PORT_LED_OFF    (0<<14)
 279 #define PORT_LED_AMBER  (1<<14)
 280 #define PORT_LED_GREEN  (2<<14)
 281 #define PORT_LED_MASK   (3<<14)
 282 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 283 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 284 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 285 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 286 /* 9 reserved */
 287 #define PORT_RESET      (1<<8)          /* reset port */
 288 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 289 #define PORT_RESUME     (1<<6)          /* resume it */
 290 #define PORT_OCC        (1<<5)          /* over current change */
 291 #define PORT_OC         (1<<4)          /* over current active */
 292 #define PORT_PEC        (1<<3)          /* port enable change */
 293 #define PORT_PE         (1<<2)          /* port enable */
 294 #define PORT_CSC        (1<<1)          /* connect status change */
 295 #define PORT_CONNECT    (1<<0)          /* device connected */
 296 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 297 } __attribute__ ((packed));
 298
 299 #define USBMODE         0x68            /* USB Device mode */
 300 #define USBMODE_SDIS    (1<<3)          /* Stream disable */
 301 #define USBMODE_BE      (1<<2)          /* BE/LE endianness select */
 302 #define USBMODE_CM_HC   (3<<0)          /* host controller mode */
 303 #define USBMODE_CM_IDLE (0<<0)          /* idle state */
 304
 305 /* Appendix C, Debug port ... intended for use with special "debug devices"
 306  * that can help if there's no serial console.  (nonstandard enumeration.)
 307  */
 308 struct ehci_dbg_port {
 309         u32     control;
 310 #define DBGP_OWNER      (1<<30)
 311 #define DBGP_ENABLED    (1<<28)
 312 #define DBGP_DONE       (1<<16)
 313 #define DBGP_INUSE      (1<<10)
 314 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 315 #       define DBGP_ERR_BAD     1
 316 #       define DBGP_ERR_SIGNAL  2
 317 #define DBGP_ERROR      (1<<6)
 318 #define DBGP_GO         (1<<5)
 319 #define DBGP_OUT        (1<<4)
 320 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 321         u32     pids;
 322 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 323 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 324         u32     data03;
 325         u32     data47;
 326         u32     address;
 327 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 328 } __attribute__ ((packed));
 329
 330 /*-------------------------------------------------------------------------*/
 331
 332 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 333
 334 /*
 335  * EHCI Specification 0.95 Section 3.5
 336  * QTD: describe data transfer components (buffer, direction, ...)
 337  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 338  *
 339  * These are associated only with "QH" (Queue Head) structures,
 340  * used with control, bulk, and interrupt transfers.
 341  */
 342 struct ehci_qtd {
 343         /* first part defined by EHCI spec */
 344         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 345         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 346         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 347 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 348 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 349 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 350 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 351 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 352 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 353 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 354 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 355 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 356 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 357 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 358 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 359 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 360
 361 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 362 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 363 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 364
 365         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 366         __hc32                  hw_buf_hi [5];        /* Appendix B */
 367
 368         /* the rest is HCD-private */
 369         dma_addr_t              qtd_dma;                /* qtd address */
 370         struct list_head        qtd_list;               /* sw qtd list */
 371         struct urb              *urb;                   /* qtd's urb */
 372         size_t                  length;                 /* length of buffer */
 373 } __attribute__ ((aligned (32)));
 374
 375 /* mask NakCnt+T in qh->hw_alt_next */
 376 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 377
 378 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 379
 380 /*-------------------------------------------------------------------------*/
 381
 382 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 383 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 384
 385 /*
 386  * Now the following defines are not converted using the
 387  * __constant_cpu_to_le32() macro anymore, since we have to support
 388  * "dynamic" switching between be and le support, so that the driver
 389  * can be used on one system with SoC EHCI controller using big-endian
 390  * descriptors as well as a normal little-endian PCI EHCI controller.
 391  */
 392 /* values for that type tag */
 393 #define Q_TYPE_ITD      (0 << 1)
 394 #define Q_TYPE_QH       (1 << 1)
 395 #define Q_TYPE_SITD     (2 << 1)
 396 #define Q_TYPE_FSTN     (3 << 1)
 397
 398 /* next async queue entry, or pointer to interrupt/periodic QH */
 399 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 400
 401 /* for periodic/async schedules and qtd lists, mark end of list */
 402 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 403
 404 /*
 405  * Entries in periodic shadow table are pointers to one of four kinds
 406  * of data structure.  That's dictated by the hardware; a type tag is
 407  * encoded in the low bits of the hardware's periodic schedule.  Use
 408  * Q_NEXT_TYPE to get the tag.
 409  *
 410  * For entries in the async schedule, the type tag always says "qh".
 411  */
 412 union ehci_shadow {
 413         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 414         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 415         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 416         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 417         __hc32                  *hw_next;       /* (all types) */
 418         void                    *ptr;
 419 };
 420
 421 /*-------------------------------------------------------------------------*/
 422
 423 /*
 424  * EHCI Specification 0.95 Section 3.6
 425  * QH: describes control/bulk/interrupt endpoints
 426  * See Fig 3-7 "Queue Head Structure Layout".
 427  *
 428  * These appear in both the async and (for interrupt) periodic schedules.
 429  */
 430
 431 struct ehci_qh {
 432         /* first part defined by EHCI spec */
 433         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 434         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 435 #define QH_HEAD         0x00008000
 436         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 437 #define QH_SMASK        0x000000ff
 438 #define QH_CMASK        0x0000ff00
 439 #define QH_HUBADDR      0x007f0000
 440 #define QH_HUBPORT      0x3f800000
 441 #define QH_MULT         0xc0000000
 442         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 443
 444         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 445         __hc32                  hw_qtd_next;
 446         __hc32                  hw_alt_next;
 447         __hc32                  hw_token;
 448         __hc32                  hw_buf [5];
 449         __hc32                  hw_buf_hi [5];
 450
 451         /* the rest is HCD-private */
 452         dma_addr_t              qh_dma;         /* address of qh */
 453         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 454         struct list_head        qtd_list;       /* sw qtd list */
 455         struct ehci_qtd         *dummy;
 456         struct ehci_qh          *reclaim;       /* next to reclaim */
 457
 458         struct ehci_hcd         *ehci;
 459
 460         /*
 461          * Do NOT use atomic operations for QH refcounting. On some CPUs
 462          * (PPC7448 for example), atomic operations cannot be performed on
 463          * memory that is cache-inhibited (i.e. being used for DMA).
 464          * Spinlocks are used to protect all QH fields.
 465          */
 466         u32                     refcount;
 467         unsigned                stamp;
 468
 469         u8                      qh_state;
 470 #define QH_STATE_LINKED         1               /* HC sees this */
 471 #define QH_STATE_UNLINK         2               /* HC may still see this */
 472 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 473 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 474 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 475
 476         /* periodic schedule info */
 477         u8                      usecs;          /* intr bandwidth */
 478         u8                      gap_uf;         /* uframes split/csplit gap */
 479         u8                      c_usecs;        /* ... split completion bw */
 480         u16                     tt_usecs;       /* tt downstream bandwidth */
 481         unsigned short          period;         /* polling interval */
 482         unsigned short          start;          /* where polling starts */
 483 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 484         struct usb_device       *dev;           /* access to TT */
 485 } __attribute__ ((aligned (32)));
 486
 487 /*-------------------------------------------------------------------------*/
 488
 489 /* description of one iso transaction (up to 3 KB data if highspeed) */
 490 struct ehci_iso_packet {
 491         /* These will be copied to iTD when scheduling */
 492         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 493         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 494         u8                      cross;          /* buf crosses pages */
 495         /* for full speed OUT splits */
 496         u32                     buf1;
 497 };
 498
 499 /* temporary schedule data for packets from iso urbs (both speeds)
 500  * each packet is one logical usb transaction to the device (not TT),
 501  * beginning at stream->next_uframe
 502  */
 503 struct ehci_iso_sched {
 504         struct list_head        td_list;
 505         unsigned                span;
 506         struct ehci_iso_packet  packet [0];
 507 };
 508
 509 /*
 510  * ehci_iso_stream - groups all (s)itds for this endpoint.
 511  * acts like a qh would, if EHCI had them for ISO.
 512  */
 513 struct ehci_iso_stream {
 514         /* first two fields match QH, but info1 == 0 */
 515         __hc32                  hw_next;
 516         __hc32                  hw_info1;
 517
 518         u32                     refcount;
 519         u8                      bEndpointAddress;
 520         u8                      highspeed;
 521         u16                     depth;          /* depth in uframes */
 522         struct list_head        td_list;        /* queued itds/sitds */
 523         struct list_head        free_list;      /* list of unused itds/sitds */
 524         struct usb_device       *udev;
 525         struct usb_host_endpoint *ep;
 526
 527         /* output of (re)scheduling */
 528         unsigned long           start;          /* jiffies */
 529         unsigned long           rescheduled;
 530         int                     next_uframe;
 531         __hc32                  splits;
 532
 533         /* the rest is derived from the endpoint descriptor,
 534          * trusting urb->interval == f(epdesc->bInterval) and
 535          * including the extra info for hw_bufp[0..2]
 536          */
 537         u8                      interval;
 538         u8                      usecs, c_usecs;
 539         u16                     tt_usecs;
 540         u16                     maxp;
 541         u16                     raw_mask;
 542         unsigned                bandwidth;
 543
 544         /* This is used to initialize iTD's hw_bufp fields */
 545         __hc32                  buf0;
 546         __hc32                  buf1;
 547         __hc32                  buf2;
 548
 549         /* this is used to initialize sITD's tt info */
 550         __hc32                  address;
 551 };
 552
 553 /*-------------------------------------------------------------------------*/
 554
 555 /*
 556  * EHCI Specification 0.95 Section 3.3
 557  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 558  *
 559  * Schedule records for high speed iso xfers
 560  */
 561 struct ehci_itd {
 562         /* first part defined by EHCI spec */
 563         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 564         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 565 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 566 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 567 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 568 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 569 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 570 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 571
 572 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 573
 574         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 575         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 576
 577         /* the rest is HCD-private */
 578         dma_addr_t              itd_dma;        /* for this itd */
 579         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 580
 581         struct urb              *urb;
 582         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 583         struct list_head        itd_list;       /* list of stream's itds */
 584
 585         /* any/all hw_transactions here may be used by that urb */
 586         unsigned                frame;          /* where scheduled */
 587         unsigned                pg;
 588         unsigned                index[8];       /* in urb->iso_frame_desc */
 589         u8                      usecs[8];
 590 } __attribute__ ((aligned (32)));
 591
 592 /*-------------------------------------------------------------------------*/
 593
 594 /*
 595  * EHCI Specification 0.95 Section 3.4
 596  * siTD, aka split-transaction isochronous Transfer Descriptor
 597  *       ... describe full speed iso xfers through TT in hubs
 598  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 599  */
 600 struct ehci_sitd {
 601         /* first part defined by EHCI spec */
 602         __hc32                  hw_next;
 603 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 604         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 605         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 606         __hc32                  hw_results;             /* EHCI table 3-11 */
 607 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 608 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 609 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 610 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 611 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 612 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 613 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 614 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 615 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 616 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 617
 618 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 619
 620         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 621         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 622         __hc32                  hw_buf_hi [2];          /* Appendix B */
 623
 624         /* the rest is HCD-private */
 625         dma_addr_t              sitd_dma;
 626         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 627
 628         struct urb              *urb;
 629         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 630         struct list_head        sitd_list;      /* list of stream's sitds */
 631         unsigned                frame;
 632         unsigned                index;
 633 } __attribute__ ((aligned (32)));
 634
 635 /*-------------------------------------------------------------------------*/
 636
 637 /*
 638  * EHCI Specification 0.96 Section 3.7
 639  * Periodic Frame Span Traversal Node (FSTN)
 640  *
 641  * Manages split interrupt transactions (using TT) that span frame boundaries
 642  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 643  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 644  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 645  */
 646 struct ehci_fstn {
 647         __hc32                  hw_next;        /* any periodic q entry */
 648         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 649
 650         /* the rest is HCD-private */
 651         dma_addr_t              fstn_dma;
 652         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 653 } __attribute__ ((aligned (32)));
 654
 655 /*-------------------------------------------------------------------------*/
 656
 657 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 658
 659 /*
 660  * Some EHCI controllers have a Transaction Translator built into the
 661  * root hub. This is a non-standard feature.  Each controller will need
 662  * to add code to the following inline functions, and call them as
 663  * needed (mostly in root hub code).
 664  */
 665
 666 #define ehci_is_TDI(e)                  ((e)->is_tdi_rh_tt)
 667
 668 /* Returns the speed of a device attached to a port on the root hub. */
 669 static inline unsigned int
 670 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 671 {
 672         if (ehci_is_TDI(ehci)) {
 673                 switch ((portsc>>26)&3) {
 674                 case 0:
 675                         return 0;
 676                 case 1:
 677                         return (1<<USB_PORT_FEAT_LOWSPEED);
 678                 case 2:
 679                 default:
 680                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 681                 }
 682         }
 683         return (1<<USB_PORT_FEAT_HIGHSPEED);
 684 }
 685
 686 #else
 687
 688 #define ehci_is_TDI(e)                  (0)
 689
 690 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 691 #endif
 692
 693 /*-------------------------------------------------------------------------*/
 694
 695 #ifdef CONFIG_PPC_83xx
 696 /* Some Freescale processors have an erratum in which the TT
 697  * port number in the queue head was 0..N-1 instead of 1..N.
 698  */
 699 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 700 #else
 701 #define ehci_has_fsl_portno_bug(e)              (0)
 702 #endif
 703
 704 /*
 705  * While most USB host controllers implement their registers in
 706  * little-endian format, a minority (celleb companion chip) implement
 707  * them in big endian format.
 708  *
 709  * This attempts to support either format at compile time without a
 710  * runtime penalty, or both formats with the additional overhead
 711  * of checking a flag bit.
 712  */
 713
 714 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 715 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 716 #else
 717 #define ehci_big_endian_mmio(e)         0
 718 #endif
 719
 720 /*
 721  * Big-endian read/write functions are arch-specific.
 722  * Other arches can be added if/when they're needed.
 723  *
 724  * REVISIT: arch/powerpc now has readl/writel_be, so the
 725  * definition below can die once the 4xx support is
 726  * finally ported over.
 727  */
 728 #if defined(CONFIG_PPC)
 729 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 730 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 731 #endif
 732
 733 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 734                 __u32 __iomem * regs)
 735 {
 736 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 737         return ehci_big_endian_mmio(ehci) ?
 738                 readl_be(regs) :
 739                 readl(regs);
 740 #else
 741         return readl(regs);
 742 #endif
 743 }
 744
 745 static inline void ehci_writel(const struct ehci_hcd *ehci,
 746                 const unsigned int val, __u32 __iomem *regs)
 747 {
 748 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 749         ehci_big_endian_mmio(ehci) ?
 750                 writel_be(val, regs) :
 751                 writel(val, regs);
 752 #else
 753         writel(val, regs);
 754 #endif
 755 }
 756
 757 /*-------------------------------------------------------------------------*/
 758
 759 /*
 760  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 761  * format, but also its DMA data structures (descriptors).
 762  *
 763  * EHCI controllers accessed through PCI work normally (little-endian
 764  * everywhere), so we won't bother supporting a BE-only mode for now.
 765  */
 766 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 767 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 768
 769 /* cpu to ehci */
 770 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 771 {
 772         return ehci_big_endian_desc(ehci)
 773                 ? (__force __hc32)cpu_to_be32(x)
 774                 : (__force __hc32)cpu_to_le32(x);
 775 }
 776
 777 /* ehci to cpu */
 778 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 779 {
 780         return ehci_big_endian_desc(ehci)
 781                 ? be32_to_cpu((__force __be32)x)
 782                 : le32_to_cpu((__force __le32)x);
 783 }
 784
 785 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 786 {
 787         return ehci_big_endian_desc(ehci)
 788                 ? be32_to_cpup((__force __be32 *)x)
 789                 : le32_to_cpup((__force __le32 *)x);
 790 }
 791
 792 #else
 793
 794 /* cpu to ehci */
 795 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 796 {
 797         return cpu_to_le32(x);
 798 }
 799
 800 /* ehci to cpu */
 801 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 802 {
 803         return le32_to_cpu(x);
 804 }
 805
 806 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 807 {
 808         return le32_to_cpup(x);
 809 }
 810
 811 #endif
 812
 813 /*-------------------------------------------------------------------------*/
 814
 815 #ifndef DEBUG
 816 #define STUB_DEBUG_FILES
 817 #endif  /* DEBUG */
 818
 819 /*-------------------------------------------------------------------------*/
 820
 821 #endif /* __LINUX_EHCI_HCD_H */