include/asm-powerpc/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4
   5 #include <linux/pci.h>
   6 #include <linux/list.h>
   7 #include <linux/ioport.h>
   8
   9 #ifndef CONFIG_PPC64
  10
  11 struct device_node;
  12 struct pci_controller;
  13
  14 /*
  15  * Structure of a PCI controller (host bridge)
  16  */
  17 struct pci_controller {
  18         struct pci_bus *bus;
  19         char is_dynamic;
  20         void *arch_data;
  21         struct list_head list_node;
  22         struct device *parent;
  23
  24         int first_busno;
  25         int last_busno;
  26         int self_busno;
  27
  28         void __iomem *io_base_virt;
  29         resource_size_t io_base_phys;
  30
  31         /* Some machines (PReP) have a non 1:1 mapping of
  32          * the PCI memory space in the CPU bus space
  33          */
  34         resource_size_t pci_mem_offset;
  35
  36         struct pci_ops *ops;
  37         volatile unsigned int __iomem *cfg_addr;
  38         volatile void __iomem *cfg_data;
  39
  40         /*
  41          * Used for variants of PCI indirect handling and possible quirks:
  42          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  43          *  EXT_REG - provides access to PCI-e extended registers
  44          *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
  45          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  46          *   to determine which bus number to match on when generating type0
  47          *   config cycles
  48          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  49          *   hanging if we don't have link and try to do config cycles to
  50          *   anything but the PHB.  Only allow talking to the PHB if this is
  51          *   set.
  52          *  BIG_ENDIAN - cfg_addr is a big endian register
  53          */
  54 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          (0x00000001)
  55 #define PPC_INDIRECT_TYPE_EXT_REG               (0x00000002)
  56 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  (0x00000004)
  57 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          (0x00000008)
  58 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            (0x00000010)
  59         u32 indirect_type;
  60
  61         /* Currently, we limit ourselves to 1 IO range and 3 mem
  62          * ranges since the common pci_bus structure can't handle more
  63          */
  64         struct resource io_resource;
  65         struct resource mem_resources[3];
  66         int global_number;              /* PCI domain number */
  67 };
  68
  69 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
  70 {
  71         return bus->sysdata;
  72 }
  73
  74 static inline int isa_vaddr_is_ioport(void __iomem *address)
  75 {
  76         /* No specific ISA handling on ppc32 at this stage, it
  77          * all goes through PCI
  78          */
  79         return 0;
  80 }
  81
  82 /* These are used for config access before all the PCI probing
  83    has been done. */
  84 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  85                            int where, u8 *val);
  86 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
  87                            int where, u16 *val);
  88 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
  89                             int where, u32 *val);
  90 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  91                             int where, u8 val);
  92 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
  93                             int where, u16 val);
  94 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
  95                              int where, u32 val);
  96
  97 extern int early_find_capability(struct pci_controller *hose, int bus,
  98                                  int dev_fn, int cap);
  99
 100 extern void setup_indirect_pci(struct pci_controller* hose,
 101                                resource_size_t cfg_addr,
 102                                resource_size_t cfg_data, u32 flags);
 103 extern void setup_grackle(struct pci_controller *hose);
 104 extern void __init update_bridge_resource(struct pci_dev *dev,
 105                                           struct resource *res);
 106
 107 #else
 108
 109
 110 /*
 111  * This program is free software; you can redistribute it and/or
 112  * modify it under the terms of the GNU General Public License
 113  * as published by the Free Software Foundation; either version
 114  * 2 of the License, or (at your option) any later version.
 115  */
 116
 117 /*
 118  * Structure of a PCI controller (host bridge)
 119  */
 120 struct pci_controller {
 121         struct pci_bus *bus;
 122         char is_dynamic;
 123         int node;
 124         void *arch_data;
 125         struct list_head list_node;
 126         struct device *parent;
 127
 128         int first_busno;
 129         int last_busno;
 130
 131         void __iomem *io_base_virt;
 132         void *io_base_alloc;
 133         resource_size_t io_base_phys;
 134
 135         /* Some machines have a non 1:1 mapping of
 136          * the PCI memory space in the CPU bus space
 137          */
 138         resource_size_t pci_mem_offset;
 139         unsigned long pci_io_size;
 140
 141         struct pci_ops *ops;
 142         volatile unsigned int __iomem *cfg_addr;
 143         volatile void __iomem *cfg_data;
 144
 145         /* Currently, we limit ourselves to 1 IO range and 3 mem
 146          * ranges since the common pci_bus structure can't handle more
 147          */
 148         struct resource io_resource;
 149         struct resource mem_resources[3];
 150         int global_number;
 151         unsigned long buid;
 152         unsigned long dma_window_base_cur;
 153         unsigned long dma_window_size;
 154
 155         void *private_data;
 156 };
 157
 158 /*
 159  * PCI stuff, for nodes representing PCI devices, pointed to
 160  * by device_node->data.
 161  */
 162 struct pci_controller;
 163 struct iommu_table;
 164
 165 struct pci_dn {
 166         int     busno;                  /* pci bus number */
 167         int     bussubno;               /* pci subordinate bus number */
 168         int     devfn;                  /* pci device and function number */
 169         int     class_code;             /* pci device class */
 170
 171         struct  pci_controller *phb;    /* for pci devices */
 172         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 173         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 174         struct  device_node *node;      /* back-pointer to the device_node */
 175
 176         int     pci_ext_config_space;   /* for pci devices */
 177
 178 #ifdef CONFIG_EEH
 179         int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
 180         int     eeh_config_addr;
 181         int     eeh_pe_config_addr; /* new-style partition endpoint address */
 182         int     eeh_check_count;        /* # times driver ignored error */
 183         int     eeh_freeze_count;       /* # times this device froze up. */
 184         int     eeh_false_positives;    /* # times this device reported #ff's */
 185         u32     config_space[16];       /* saved PCI config space */
 186 #endif
 187 };
 188
 189 /* Get the pointer to a device_node's pci_dn */
 190 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 191
 192 struct device_node *fetch_dev_dn(struct pci_dev *dev);
 193
 194 /* Get a device_node from a pci_dev.  This code must be fast except
 195  * in the case where the sysdata is incorrect and needs to be fixed
 196  * up (this will only happen once).
 197  * In this case the sysdata will have been inherited from a PCI host
 198  * bridge or a PCI-PCI bridge further up the tree, so it will point
 199  * to a valid struct pci_dn, just not the one we want.
 200  */
 201 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
 202 {
 203         struct device_node *dn = dev->sysdata;
 204         struct pci_dn *pdn = dn->data;
 205
 206         if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
 207                 return dn;      /* fast path.  sysdata is good */
 208         return fetch_dev_dn(dev);
 209 }
 210
 211 static inline int pci_device_from_OF_node(struct device_node *np,
 212                                           u8 *bus, u8 *devfn)
 213 {
 214         if (!PCI_DN(np))
 215                 return -ENODEV;
 216         *bus = PCI_DN(np)->busno;
 217         *devfn = PCI_DN(np)->devfn;
 218         return 0;
 219 }
 220
 221 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 222 {
 223         if (bus->self)
 224                 return pci_device_to_OF_node(bus->self);
 225         else
 226                 return bus->sysdata; /* Must be root bus (PHB) */
 227 }
 228
 229 /** Find the bus corresponding to the indicated device node */
 230 struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
 231
 232 /** Remove all of the PCI devices under this bus */
 233 void pcibios_remove_pci_devices(struct pci_bus *bus);
 234
 235 /** Discover new pci devices under this bus, and add them */
 236 void pcibios_add_pci_devices(struct pci_bus * bus);
 237 void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
 238
 239 extern int pcibios_remove_root_bus(struct pci_controller *phb);
 240
 241 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
 242 {
 243         struct device_node *busdn = bus->sysdata;
 244
 245         BUG_ON(busdn == NULL);
 246         return PCI_DN(busdn)->phb;
 247 }
 248
 249
 250 extern void isa_bridge_find_early(struct pci_controller *hose);
 251
 252 static inline int isa_vaddr_is_ioport(void __iomem *address)
 253 {
 254         /* Check if address hits the reserved legacy IO range */
 255         unsigned long ea = (unsigned long)address;
 256         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 257 }
 258
 259 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 260 extern int pcibios_map_io_space(struct pci_bus *bus);
 261
 262 /* Return values for ppc_md.pci_probe_mode function */
 263 #define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
 264 #define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
 265 #define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
 266
 267 #ifdef CONFIG_NUMA
 268 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 269 #else
 270 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 271 #endif
 272
 273 #endif /* CONFIG_PPC64 */
 274
 275 /* Get the PCI host controller for an OF device */
 276 extern struct pci_controller*
 277 pci_find_hose_for_OF_device(struct device_node* node);
 278
 279 /* Fill up host controller resources from the OF node */
 280 extern void
 281 pci_process_bridge_OF_ranges(struct pci_controller *hose,
 282                            struct device_node *dev, int primary);
 283
 284 /* Allocate & free a PCI host bridge structure */
 285 extern struct pci_controller *
 286 pcibios_alloc_controller(struct device_node *dev);
 287 extern void pcibios_free_controller(struct pci_controller *phb);
 288
 289 #ifdef CONFIG_PCI
 290 extern unsigned long pci_address_to_pio(phys_addr_t address);
 291 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 292 #else
 293 static inline unsigned long pci_address_to_pio(phys_addr_t address)
 294 {
 295         return (unsigned long)-1;
 296 }
 297 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 298 {
 299         return 0;
 300 }
 301 #endif
 302
 303
 304
 305 #endif /* __KERNEL__ */
 306 #endif