include/asm-sh/dma-mapping.h

   1 #ifndef __ASM_SH_DMA_MAPPING_H
   2 #define __ASM_SH_DMA_MAPPING_H
   3
   4 #include <linux/mm.h>
   5 #include <linux/scatterlist.h>
   6 #include <asm/cacheflush.h>
   7 #include <asm/io.h>
   8
   9 extern struct bus_type pci_bus_type;
  10
  11 /* arch/sh/mm/consistent.c */
  12 extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *handle);
  13 extern void consistent_free(void *vaddr, size_t size);
  14 extern void consistent_sync(void *vaddr, size_t size, int direction);
  15
  16 #define dma_supported(dev, mask)        (1)
  17
  18 static inline int dma_set_mask(struct device *dev, u64 mask)
  19 {
  20         if (!dev->dma_mask || !dma_supported(dev, mask))
  21                 return -EIO;
  22
  23         *dev->dma_mask = mask;
  24
  25         return 0;
  26 }
  27
  28 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
  29                          dma_addr_t *dma_handle, gfp_t flag)
  30 {
  31         if (sh_mv.mv_consistent_alloc) {
  32                 void *ret;
  33
  34                 ret = sh_mv.mv_consistent_alloc(dev, size, dma_handle, flag);
  35                 if (ret != NULL)
  36                         return ret;
  37         }
  38
  39         return consistent_alloc(flag, size, dma_handle);
  40 }
  41
  42 static inline void dma_free_coherent(struct device *dev, size_t size,
  43                        void *vaddr, dma_addr_t dma_handle)
  44 {
  45         if (sh_mv.mv_consistent_free) {
  46                 int ret;
  47
  48                 ret = sh_mv.mv_consistent_free(dev, size, vaddr, dma_handle);
  49                 if (ret == 0)
  50                         return;
  51         }
  52
  53         consistent_free(vaddr, size);
  54 }
  55
  56 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
  57 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
  58 #define dma_is_consistent(d, h) (1)
  59
  60 static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
  61                                   enum dma_data_direction dir)
  62 {
  63         consistent_sync(vaddr, size, (int)dir);
  64 }
  65
  66 static inline dma_addr_t dma_map_single(struct device *dev,
  67                                         void *ptr, size_t size,
  68                                         enum dma_data_direction dir)
  69 {
  70 #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
  71         if (dev->bus == &pci_bus_type)
  72                 return virt_to_phys(ptr);
  73 #endif
  74         dma_cache_sync(dev, ptr, size, dir);
  75
  76         return virt_to_phys(ptr);
  77 }
  78
  79 #define dma_unmap_single(dev, addr, size, dir)  do { } while (0)
  80
  81 static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
  82                              int nents, enum dma_data_direction dir)
  83 {
  84         int i;
  85
  86         for (i = 0; i < nents; i++) {
  87 #if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
  88                 dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
  89 #endif
  90                 sg[i].dma_address = sg_phys(&sg[i]);
  91         }
  92
  93         return nents;
  94 }
  95
  96 #define dma_unmap_sg(dev, sg, nents, dir)       do { } while (0)
  97
  98 static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
  99                                       unsigned long offset, size_t size,
 100                                       enum dma_data_direction dir)
 101 {
 102         return dma_map_single(dev, page_address(page) + offset, size, dir);
 103 }
 104
 105 static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
 106                                   size_t size, enum dma_data_direction dir)
 107 {
 108         dma_unmap_single(dev, dma_address, size, dir);
 109 }
 110
 111 static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
 112                                    size_t size, enum dma_data_direction dir)
 113 {
 114 #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
 115         if (dev->bus == &pci_bus_type)
 116                 return;
 117 #endif
 118         dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir);
 119 }
 120
 121 static inline void dma_sync_single_range(struct device *dev,
 122                                          dma_addr_t dma_handle,
 123                                          unsigned long offset, size_t size,
 124                                          enum dma_data_direction dir)
 125 {
 126 #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
 127         if (dev->bus == &pci_bus_type)
 128                 return;
 129 #endif
 130         dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir);
 131 }
 132
 133 static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
 134                                int nelems, enum dma_data_direction dir)
 135 {
 136         int i;
 137
 138         for (i = 0; i < nelems; i++) {
 139 #if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
 140                 dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
 141 #endif
 142                 sg[i].dma_address = sg_phys(&sg[i]);
 143         }
 144 }
 145
 146 static inline void dma_sync_single_for_cpu(struct device *dev,
 147                                            dma_addr_t dma_handle, size_t size,
 148                                            enum dma_data_direction dir)
 149 {
 150         dma_sync_single(dev, dma_handle, size, dir);
 151 }
 152
 153 static inline void dma_sync_single_for_device(struct device *dev,
 154                                               dma_addr_t dma_handle,
 155                                               size_t size,
 156                                               enum dma_data_direction dir)
 157 {
 158         dma_sync_single(dev, dma_handle, size, dir);
 159 }
 160
 161 static inline void dma_sync_single_range_for_cpu(struct device *dev,
 162                                                  dma_addr_t dma_handle,
 163                                                  unsigned long offset,
 164                                                  size_t size,
 165                                                  enum dma_data_direction direction)
 166 {
 167         dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
 168 }
 169
 170 static inline void dma_sync_single_range_for_device(struct device *dev,
 171                                                     dma_addr_t dma_handle,
 172                                                     unsigned long offset,
 173                                                     size_t size,
 174                                                     enum dma_data_direction direction)
 175 {
 176         dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
 177 }
 178
 179
 180 static inline void dma_sync_sg_for_cpu(struct device *dev,
 181                                        struct scatterlist *sg, int nelems,
 182                                        enum dma_data_direction dir)
 183 {
 184         dma_sync_sg(dev, sg, nelems, dir);
 185 }
 186
 187 static inline void dma_sync_sg_for_device(struct device *dev,
 188                                           struct scatterlist *sg, int nelems,
 189                                           enum dma_data_direction dir)
 190 {
 191         dma_sync_sg(dev, sg, nelems, dir);
 192 }
 193
 194
 195 static inline int dma_get_cache_alignment(void)
 196 {
 197         /*
 198          * Each processor family will define its own L1_CACHE_SHIFT,
 199          * L1_CACHE_BYTES wraps to this, so this is always safe.
 200          */
 201         return L1_CACHE_BYTES;
 202 }
 203
 204 static inline int dma_mapping_error(dma_addr_t dma_addr)
 205 {
 206         return dma_addr == 0;
 207 }
 208 #endif /* __ASM_SH_DMA_MAPPING_H */