drivers/ata/pata_efar.c

   1 /*
   2  *    pata_efar.c - EFAR PIIX clone controller driver
   3  *
   4  *      (C) 2005 Red Hat <alan@redhat.com>
   5  *
   6  *    Some parts based on ata_piix.c by Jeff Garzik and others.
   7  *
   8  *    The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
   9  *    Intel ICH controllers the EFAR widened the UDMA mode register bits
  10  *    and doesn't require the funky clock selection.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <scsi/scsi_host.h>
  21 #include <linux/libata.h>
  22 #include <linux/ata.h>
  23
  24 #define DRV_NAME        "pata_efar"
  25 #define DRV_VERSION     "0.4.4"
  26
  27 /**
  28  *      efar_pre_reset  -       Enable bits
  29  *      @ap: Port
  30  *      @deadline: deadline jiffies for the operation
  31  *
  32  *      Perform cable detection for the EFAR ATA interface. This is
  33  *      different to the PIIX arrangement
  34  */
  35
  36 static int efar_pre_reset(struct ata_port *ap, unsigned long deadline)
  37 {
  38         static const struct pci_bits efar_enable_bits[] = {
  39                 { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
  40                 { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
  41         };
  42         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  43
  44         if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
  45                 return -ENOENT;
  46
  47         return ata_std_prereset(ap, deadline);
  48 }
  49
  50 /**
  51  *      efar_probe_reset - Probe specified port on PATA host controller
  52  *      @ap: Port to probe
  53  *
  54  *      LOCKING:
  55  *      None (inherited from caller).
  56  */
  57
  58 static void efar_error_handler(struct ata_port *ap)
  59 {
  60         ata_bmdma_drive_eh(ap, efar_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  61 }
  62
  63 /**
  64  *      efar_cable_detect       -       check for 40/80 pin
  65  *      @ap: Port
  66  *
  67  *      Perform cable detection for the EFAR ATA interface. This is
  68  *      different to the PIIX arrangement
  69  */
  70
  71 static int efar_cable_detect(struct ata_port *ap)
  72 {
  73         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  74         u8 tmp;
  75
  76         pci_read_config_byte(pdev, 0x47, &tmp);
  77         if (tmp & (2 >> ap->port_no))
  78                 return ATA_CBL_PATA40;
  79         return ATA_CBL_PATA80;
  80 }
  81
  82 /**
  83  *      efar_set_piomode - Initialize host controller PATA PIO timings
  84  *      @ap: Port whose timings we are configuring
  85  *      @adev: um
  86  *
  87  *      Set PIO mode for device, in host controller PCI config space.
  88  *
  89  *      LOCKING:
  90  *      None (inherited from caller).
  91  */
  92
  93 static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
  94 {
  95         unsigned int pio        = adev->pio_mode - XFER_PIO_0;
  96         struct pci_dev *dev     = to_pci_dev(ap->host->dev);
  97         unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
  98         u16 idetm_data;
  99         int control = 0;
 100
 101         /*
 102          *      See Intel Document 298600-004 for the timing programing rules
 103          *      for PIIX/ICH. The EFAR is a clone so very similar
 104          */
 105
 106         static const     /* ISP  RTC */
 107         u8 timings[][2] = { { 0, 0 },
 108                             { 0, 0 },
 109                             { 1, 0 },
 110                             { 2, 1 },
 111                             { 2, 3 }, };
 112
 113         if (pio > 2)
 114                 control |= 1;   /* TIME1 enable */
 115         if (ata_pio_need_iordy(adev))   /* PIO 3/4 require IORDY */
 116                 control |= 2;   /* IE enable */
 117         /* Intel specifies that the PPE functionality is for disk only */
 118         if (adev->class == ATA_DEV_ATA)
 119                 control |= 4;   /* PPE enable */
 120
 121         pci_read_config_word(dev, idetm_port, &idetm_data);
 122
 123         /* Enable PPE, IE and TIME as appropriate */
 124
 125         if (adev->devno == 0) {
 126                 idetm_data &= 0xCCF0;
 127                 idetm_data |= control;
 128                 idetm_data |= (timings[pio][0] << 12) |
 129                         (timings[pio][1] << 8);
 130         } else {
 131                 int shift = 4 * ap->port_no;
 132                 u8 slave_data;
 133
 134                 idetm_data &= 0xCC0F;
 135                 idetm_data |= (control << 4);
 136
 137                 /* Slave timing in seperate register */
 138                 pci_read_config_byte(dev, 0x44, &slave_data);
 139                 slave_data &= 0x0F << shift;
 140                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
 141                 pci_write_config_byte(dev, 0x44, slave_data);
 142         }
 143
 144         idetm_data |= 0x4000;   /* Ensure SITRE is enabled */
 145         pci_write_config_word(dev, idetm_port, idetm_data);
 146 }
 147
 148 /**
 149  *      efar_set_dmamode - Initialize host controller PATA DMA timings
 150  *      @ap: Port whose timings we are configuring
 151  *      @adev: Device to program
 152  *
 153  *      Set UDMA/MWDMA mode for device, in host controller PCI config space.
 154  *
 155  *      LOCKING:
 156  *      None (inherited from caller).
 157  */
 158
 159 static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 160 {
 161         struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 162         u8 master_port          = ap->port_no ? 0x42 : 0x40;
 163         u16 master_data;
 164         u8 speed                = adev->dma_mode;
 165         int devid               = adev->devno + 2 * ap->port_no;
 166         u8 udma_enable;
 167
 168         static const     /* ISP  RTC */
 169         u8 timings[][2] = { { 0, 0 },
 170                             { 0, 0 },
 171                             { 1, 0 },
 172                             { 2, 1 },
 173                             { 2, 3 }, };
 174
 175         pci_read_config_word(dev, master_port, &master_data);
 176         pci_read_config_byte(dev, 0x48, &udma_enable);
 177
 178         if (speed >= XFER_UDMA_0) {
 179                 unsigned int udma       = adev->dma_mode - XFER_UDMA_0;
 180                 u16 udma_timing;
 181
 182                 udma_enable |= (1 << devid);
 183
 184                 /* Load the UDMA mode number */
 185                 pci_read_config_word(dev, 0x4A, &udma_timing);
 186                 udma_timing &= ~(7 << (4 * devid));
 187                 udma_timing |= udma << (4 * devid);
 188                 pci_write_config_word(dev, 0x4A, udma_timing);
 189         } else {
 190                 /*
 191                  * MWDMA is driven by the PIO timings. We must also enable
 192                  * IORDY unconditionally along with TIME1. PPE has already
 193                  * been set when the PIO timing was set.
 194                  */
 195                 unsigned int mwdma      = adev->dma_mode - XFER_MW_DMA_0;
 196                 unsigned int control;
 197                 u8 slave_data;
 198                 const unsigned int needed_pio[3] = {
 199                         XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 200                 };
 201                 int pio = needed_pio[mwdma] - XFER_PIO_0;
 202
 203                 control = 3;    /* IORDY|TIME1 */
 204
 205                 /* If the drive MWDMA is faster than it can do PIO then
 206                    we must force PIO into PIO0 */
 207
 208                 if (adev->pio_mode < needed_pio[mwdma])
 209                         /* Enable DMA timing only */
 210                         control |= 8;   /* PIO cycles in PIO0 */
 211
 212                 if (adev->devno) {      /* Slave */
 213                         master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
 214                         master_data |= control << 4;
 215                         pci_read_config_byte(dev, 0x44, &slave_data);
 216                         slave_data &= (0x0F + 0xE1 * ap->port_no);
 217                         /* Load the matching timing */
 218                         slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
 219                         pci_write_config_byte(dev, 0x44, slave_data);
 220                 } else {        /* Master */
 221                         master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
 222                                                    and master timing bits */
 223                         master_data |= control;
 224                         master_data |=
 225                                 (timings[pio][0] << 12) |
 226                                 (timings[pio][1] << 8);
 227                 }
 228                 udma_enable &= ~(1 << devid);
 229                 pci_write_config_word(dev, master_port, master_data);
 230         }
 231         pci_write_config_byte(dev, 0x48, udma_enable);
 232 }
 233
 234 static struct scsi_host_template efar_sht = {
 235         .module                 = THIS_MODULE,
 236         .name                   = DRV_NAME,
 237         .ioctl                  = ata_scsi_ioctl,
 238         .queuecommand           = ata_scsi_queuecmd,
 239         .can_queue              = ATA_DEF_QUEUE,
 240         .this_id                = ATA_SHT_THIS_ID,
 241         .sg_tablesize           = LIBATA_MAX_PRD,
 242         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 243         .emulated               = ATA_SHT_EMULATED,
 244         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 245         .proc_name              = DRV_NAME,
 246         .dma_boundary           = ATA_DMA_BOUNDARY,
 247         .slave_configure        = ata_scsi_slave_config,
 248         .slave_destroy          = ata_scsi_slave_destroy,
 249         .bios_param             = ata_std_bios_param,
 250 };
 251
 252 static const struct ata_port_operations efar_ops = {
 253         .port_disable           = ata_port_disable,
 254         .set_piomode            = efar_set_piomode,
 255         .set_dmamode            = efar_set_dmamode,
 256         .mode_filter            = ata_pci_default_filter,
 257
 258         .tf_load                = ata_tf_load,
 259         .tf_read                = ata_tf_read,
 260         .check_status           = ata_check_status,
 261         .exec_command           = ata_exec_command,
 262         .dev_select             = ata_std_dev_select,
 263
 264         .freeze                 = ata_bmdma_freeze,
 265         .thaw                   = ata_bmdma_thaw,
 266         .error_handler          = efar_error_handler,
 267         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
 268         .cable_detect           = efar_cable_detect,
 269
 270         .bmdma_setup            = ata_bmdma_setup,
 271         .bmdma_start            = ata_bmdma_start,
 272         .bmdma_stop             = ata_bmdma_stop,
 273         .bmdma_status           = ata_bmdma_status,
 274         .qc_prep                = ata_qc_prep,
 275         .qc_issue               = ata_qc_issue_prot,
 276         .data_xfer              = ata_data_xfer,
 277
 278         .irq_handler            = ata_interrupt,
 279         .irq_clear              = ata_bmdma_irq_clear,
 280         .irq_on                 = ata_irq_on,
 281         .irq_ack                = ata_irq_ack,
 282
 283         .port_start             = ata_port_start,
 284 };
 285
 286
 287 /**
 288  *      efar_init_one - Register EFAR ATA PCI device with kernel services
 289  *      @pdev: PCI device to register
 290  *      @ent: Entry in efar_pci_tbl matching with @pdev
 291  *
 292  *      Called from kernel PCI layer.
 293  *
 294  *      LOCKING:
 295  *      Inherited from PCI layer (may sleep).
 296  *
 297  *      RETURNS:
 298  *      Zero on success, or -ERRNO value.
 299  */
 300
 301 static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 302 {
 303         static int printed_version;
 304         static const struct ata_port_info info = {
 305                 .sht            = &efar_sht,
 306                 .flags          = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
 307                 .pio_mask       = 0x1f, /* pio0-4 */
 308                 .mwdma_mask     = 0x07, /* mwdma1-2 */
 309                 .udma_mask      = 0x0f, /* UDMA 66 */
 310                 .port_ops       = &efar_ops,
 311         };
 312         const struct ata_port_info *ppi[] = { &info, NULL };
 313
 314         if (!printed_version++)
 315                 dev_printk(KERN_DEBUG, &pdev->dev,
 316                            "version " DRV_VERSION "\n");
 317
 318         return ata_pci_init_one(pdev, ppi);
 319 }
 320
 321 static const struct pci_device_id efar_pci_tbl[] = {
 322         { PCI_VDEVICE(EFAR, 0x9130), },
 323
 324         { }     /* terminate list */
 325 };
 326
 327 static struct pci_driver efar_pci_driver = {
 328         .name                   = DRV_NAME,
 329         .id_table               = efar_pci_tbl,
 330         .probe                  = efar_init_one,
 331         .remove                 = ata_pci_remove_one,
 332 #ifdef CONFIG_PM
 333         .suspend                = ata_pci_device_suspend,
 334         .resume                 = ata_pci_device_resume,
 335 #endif
 336 };
 337
 338 static int __init efar_init(void)
 339 {
 340         return pci_register_driver(&efar_pci_driver);
 341 }
 342
 343 static void __exit efar_exit(void)
 344 {
 345         pci_unregister_driver(&efar_pci_driver);
 346 }
 347
 348 module_init(efar_init);
 349 module_exit(efar_exit);
 350
 351 MODULE_AUTHOR("Alan Cox");
 352 MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
 353 MODULE_LICENSE("GPL");
 354 MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
 355 MODULE_VERSION(DRV_VERSION);
 356