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fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / drivers / infiniband / hw / ehca / ehca_qp.c
blobe2bd62be11e71ba735af508731181cf14b2c9d1b
1 /*
2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
3 *
4 * QP functions
5 *
6 * Authors: Joachim Fenkes <fenkes@de.ibm.com>
7 * Stefan Roscher <stefan.roscher@de.ibm.com>
8 * Waleri Fomin <fomin@de.ibm.com>
9 * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
10 * Reinhard Ernst <rernst@de.ibm.com>
11 * Heiko J Schick <schickhj@de.ibm.com>
12 *
13 * Copyright (c) 2005 IBM Corporation
14 *
15 * All rights reserved.
16 *
17 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
18 * BSD.
19 *
20 * OpenIB BSD License
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 *
25 * Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following disclaimer.
27 *
28 * Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials
31 * provided with the distribution.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
41 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGE.
44 */
45
46
47 #include <asm/current.h>
48
49 #include "ehca_classes.h"
50 #include "ehca_tools.h"
51 #include "ehca_qes.h"
52 #include "ehca_iverbs.h"
53 #include "hcp_if.h"
54 #include "hipz_fns.h"
55
56 static struct kmem_cache *qp_cache;
57
58 /*
59 * attributes not supported by query qp
60 */
61 #define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \
62 IB_QP_MAX_QP_RD_ATOMIC | \
63 IB_QP_ACCESS_FLAGS | \
64 IB_QP_EN_SQD_ASYNC_NOTIFY)
65
66 /*
67 * ehca (internal) qp state values
68 */
69 enum ehca_qp_state {
70 EHCA_QPS_RESET = 1,
71 EHCA_QPS_INIT = 2,
72 EHCA_QPS_RTR = 3,
73 EHCA_QPS_RTS = 5,
74 EHCA_QPS_SQD = 6,
75 EHCA_QPS_SQE = 8,
76 EHCA_QPS_ERR = 128
77 };
78
79 /*
80 * qp state transitions as defined by IB Arch Rel 1.1 page 431
81 */
82 enum ib_qp_statetrans {
83 IB_QPST_ANY2RESET,
84 IB_QPST_ANY2ERR,
85 IB_QPST_RESET2INIT,
86 IB_QPST_INIT2RTR,
87 IB_QPST_INIT2INIT,
88 IB_QPST_RTR2RTS,
89 IB_QPST_RTS2SQD,
90 IB_QPST_RTS2RTS,
91 IB_QPST_SQD2RTS,
92 IB_QPST_SQE2RTS,
93 IB_QPST_SQD2SQD,
94 IB_QPST_MAX /* nr of transitions, this must be last!!! */
95 };
96
97 /*
98 * ib2ehca_qp_state maps IB to ehca qp_state
99 * returns ehca qp state corresponding to given ib qp state
100 */
101 static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state)
102 {
103 switch (ib_qp_state) {
104 case IB_QPS_RESET:
105 return EHCA_QPS_RESET;
106 case IB_QPS_INIT:
107 return EHCA_QPS_INIT;
108 case IB_QPS_RTR:
109 return EHCA_QPS_RTR;
110 case IB_QPS_RTS:
111 return EHCA_QPS_RTS;
112 case IB_QPS_SQD:
113 return EHCA_QPS_SQD;
114 case IB_QPS_SQE:
115 return EHCA_QPS_SQE;
116 case IB_QPS_ERR:
117 return EHCA_QPS_ERR;
118 default:
119 ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state);
120 return -EINVAL;
121 }
122 }
123
124 /*
125 * ehca2ib_qp_state maps ehca to IB qp_state
126 * returns ib qp state corresponding to given ehca qp state
127 */
128 static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state
129 ehca_qp_state)
130 {
131 switch (ehca_qp_state) {
132 case EHCA_QPS_RESET:
133 return IB_QPS_RESET;
134 case EHCA_QPS_INIT:
135 return IB_QPS_INIT;
136 case EHCA_QPS_RTR:
137 return IB_QPS_RTR;
138 case EHCA_QPS_RTS:
139 return IB_QPS_RTS;
140 case EHCA_QPS_SQD:
141 return IB_QPS_SQD;
142 case EHCA_QPS_SQE:
143 return IB_QPS_SQE;
144 case EHCA_QPS_ERR:
145 return IB_QPS_ERR;
146 default:
147 ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state);
148 return -EINVAL;
149 }
150 }
151
152 /*
153 * ehca_qp_type used as index for req_attr and opt_attr of
154 * struct ehca_modqp_statetrans
155 */
156 enum ehca_qp_type {
157 QPT_RC = 0,
158 QPT_UC = 1,
159 QPT_UD = 2,
160 QPT_SQP = 3,
161 QPT_MAX
162 };
163
164 /*
165 * ib2ehcaqptype maps Ib to ehca qp_type
166 * returns ehca qp type corresponding to ib qp type
167 */
168 static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype)
169 {
170 switch (ibqptype) {
171 case IB_QPT_SMI:
172 case IB_QPT_GSI:
173 return QPT_SQP;
174 case IB_QPT_RC:
175 return QPT_RC;
176 case IB_QPT_UC:
177 return QPT_UC;
178 case IB_QPT_UD:
179 return QPT_UD;
180 default:
181 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
182 return -EINVAL;
183 }
184 }
185
186 static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate,
187 int ib_tostate)
188 {
189 int index = -EINVAL;
190 switch (ib_tostate) {
191 case IB_QPS_RESET:
192 index = IB_QPST_ANY2RESET;
193 break;
194 case IB_QPS_INIT:
195 switch (ib_fromstate) {
196 case IB_QPS_RESET:
197 index = IB_QPST_RESET2INIT;
198 break;
199 case IB_QPS_INIT:
200 index = IB_QPST_INIT2INIT;
201 break;
202 }
203 break;
204 case IB_QPS_RTR:
205 if (ib_fromstate == IB_QPS_INIT)
206 index = IB_QPST_INIT2RTR;
207 break;
208 case IB_QPS_RTS:
209 switch (ib_fromstate) {
210 case IB_QPS_RTR:
211 index = IB_QPST_RTR2RTS;
212 break;
213 case IB_QPS_RTS:
214 index = IB_QPST_RTS2RTS;
215 break;
216 case IB_QPS_SQD:
217 index = IB_QPST_SQD2RTS;
218 break;
219 case IB_QPS_SQE:
220 index = IB_QPST_SQE2RTS;
221 break;
222 }
223 break;
224 case IB_QPS_SQD:
225 if (ib_fromstate == IB_QPS_RTS)
226 index = IB_QPST_RTS2SQD;
227 break;
228 case IB_QPS_SQE:
229 break;
230 case IB_QPS_ERR:
231 index = IB_QPST_ANY2ERR;
232 break;
233 default:
234 break;
235 }
236 return index;
237 }
238
239 /*
240 * ibqptype2servicetype returns hcp service type corresponding to given
241 * ib qp type used by create_qp()
242 */
243 static inline int ibqptype2servicetype(enum ib_qp_type ibqptype)
244 {
245 switch (ibqptype) {
246 case IB_QPT_SMI:
247 case IB_QPT_GSI:
248 return ST_UD;
249 case IB_QPT_RC:
250 return ST_RC;
251 case IB_QPT_UC:
252 return ST_UC;
253 case IB_QPT_UD:
254 return ST_UD;
255 case IB_QPT_RAW_IPV6:
256 return -EINVAL;
257 case IB_QPT_RAW_ETY:
258 return -EINVAL;
259 default:
260 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
261 return -EINVAL;
262 }
263 }
264
265 /*
266 * init userspace queue info from ipz_queue data
267 */
268 static inline void queue2resp(struct ipzu_queue_resp *resp,
269 struct ipz_queue *queue)
270 {
271 resp->qe_size = queue->qe_size;
272 resp->act_nr_of_sg = queue->act_nr_of_sg;
273 resp->queue_length = queue->queue_length;
274 resp->pagesize = queue->pagesize;
275 resp->toggle_state = queue->toggle_state;
276 resp->offset = queue->offset;
277 }
278
279 /*
280 * init_qp_queue initializes/constructs r/squeue and registers queue pages.
281 */
282 static inline int init_qp_queue(struct ehca_shca *shca,
283 struct ehca_pd *pd,
284 struct ehca_qp *my_qp,
285 struct ipz_queue *queue,
286 int q_type,
287 u64 expected_hret,
288 struct ehca_alloc_queue_parms *parms,
289 int wqe_size)
290 {
291 int ret, cnt, ipz_rc, nr_q_pages;
292 void *vpage;
293 u64 rpage, h_ret;
294 struct ib_device *ib_dev = &shca->ib_device;
295 struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle;
296
297 if (!parms->queue_size)
298 return 0;
299
300 if (parms->is_small) {
301 nr_q_pages = 1;
302 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
303 128 << parms->page_size,
304 wqe_size, parms->act_nr_sges, 1);
305 } else {
306 nr_q_pages = parms->queue_size;
307 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
308 EHCA_PAGESIZE, wqe_size,
309 parms->act_nr_sges, 0);
310 }
311
312 if (!ipz_rc) {
313 ehca_err(ib_dev, "Cannot allocate page for queue. ipz_rc=%i",
314 ipz_rc);
315 return -EBUSY;
316 }
317
318 /* register queue pages */
319 for (cnt = 0; cnt < nr_q_pages; cnt++) {
320 vpage = ipz_qpageit_get_inc(queue);
321 if (!vpage) {
322 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
323 "failed p_vpage= %p", vpage);
324 ret = -EINVAL;
325 goto init_qp_queue1;
326 }
327 rpage = virt_to_abs(vpage);
328
329 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
330 my_qp->ipz_qp_handle,
331 NULL, 0, q_type,
332 rpage, parms->is_small ? 0 : 1,
333 my_qp->galpas.kernel);
334 if (cnt == (nr_q_pages - 1)) { /* last page! */
335 if (h_ret != expected_hret) {
336 ehca_err(ib_dev, "hipz_qp_register_rpage() "
337 "h_ret=%li", h_ret);
338 ret = ehca2ib_return_code(h_ret);
339 goto init_qp_queue1;
340 }
341 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
342 if (vpage) {
343 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
344 "should not succeed vpage=%p", vpage);
345 ret = -EINVAL;
346 goto init_qp_queue1;
347 }
348 } else {
349 if (h_ret != H_PAGE_REGISTERED) {
350 ehca_err(ib_dev, "hipz_qp_register_rpage() "
351 "h_ret=%li", h_ret);
352 ret = ehca2ib_return_code(h_ret);
353 goto init_qp_queue1;
354 }
355 }
356 }
357
358 ipz_qeit_reset(queue);
359
360 return 0;
361
362 init_qp_queue1:
363 ipz_queue_dtor(pd, queue);
364 return ret;
365 }
366
367 static inline int ehca_calc_wqe_size(int act_nr_sge, int is_llqp)
368 {
369 if (is_llqp)
370 return 128 << act_nr_sge;
371 else
372 return offsetof(struct ehca_wqe,
373 u.nud.sg_list[act_nr_sge]);
374 }
375
376 static void ehca_determine_small_queue(struct ehca_alloc_queue_parms *queue,
377 int req_nr_sge, int is_llqp)
378 {
379 u32 wqe_size, q_size;
380 int act_nr_sge = req_nr_sge;
381
382 if (!is_llqp)
383 /* round up #SGEs so WQE size is a power of 2 */
384 for (act_nr_sge = 4; act_nr_sge <= 252;
385 act_nr_sge = 4 + 2 * act_nr_sge)
386 if (act_nr_sge >= req_nr_sge)
387 break;
388
389 wqe_size = ehca_calc_wqe_size(act_nr_sge, is_llqp);
390 q_size = wqe_size * (queue->max_wr + 1);
391
392 if (q_size <= 512)
393 queue->page_size = 2;
394 else if (q_size <= 1024)
395 queue->page_size = 3;
396 else
397 queue->page_size = 0;
398
399 queue->is_small = (queue->page_size != 0);
400 }
401
402 /*
403 * Create an ib_qp struct that is either a QP or an SRQ, depending on
404 * the value of the is_srq parameter. If init_attr and srq_init_attr share
405 * fields, the field out of init_attr is used.
406 */
407 static struct ehca_qp *internal_create_qp(
408 struct ib_pd *pd,
409 struct ib_qp_init_attr *init_attr,
410 struct ib_srq_init_attr *srq_init_attr,
411 struct ib_udata *udata, int is_srq)
412 {
413 struct ehca_qp *my_qp;
414 struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd);
415 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
416 ib_device);
417 struct ib_ucontext *context = NULL;
418 u64 h_ret;
419 int is_llqp = 0, has_srq = 0;
420 int qp_type, max_send_sge, max_recv_sge, ret;
421
422 /* h_call's out parameters */
423 struct ehca_alloc_qp_parms parms;
424 u32 swqe_size = 0, rwqe_size = 0, ib_qp_num;
425 unsigned long flags;
426
427 memset(&parms, 0, sizeof(parms));
428 qp_type = init_attr->qp_type;
429
430 if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR &&
431 init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) {
432 ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed",
433 init_attr->sq_sig_type);
434 return ERR_PTR(-EINVAL);
435 }
436
437 /* save LLQP info */
438 if (qp_type & 0x80) {
439 is_llqp = 1;
440 parms.ext_type = EQPT_LLQP;
441 parms.ll_comp_flags = qp_type & LLQP_COMP_MASK;
442 }
443 qp_type &= 0x1F;
444 init_attr->qp_type &= 0x1F;
445
446 /* handle SRQ base QPs */
447 if (init_attr->srq) {
448 struct ehca_qp *my_srq =
449 container_of(init_attr->srq, struct ehca_qp, ib_srq);
450
451 has_srq = 1;
452 parms.ext_type = EQPT_SRQBASE;
453 parms.srq_qpn = my_srq->real_qp_num;
454 parms.srq_token = my_srq->token;
455 }
456
457 if (is_llqp && has_srq) {
458 ehca_err(pd->device, "LLQPs can't have an SRQ");
459 return ERR_PTR(-EINVAL);
460 }
461
462 /* handle SRQs */
463 if (is_srq) {
464 parms.ext_type = EQPT_SRQ;
465 parms.srq_limit = srq_init_attr->attr.srq_limit;
466 if (init_attr->cap.max_recv_sge > 3) {
467 ehca_err(pd->device, "no more than three SGEs "
468 "supported for SRQ pd=%p max_sge=%x",
469 pd, init_attr->cap.max_recv_sge);
470 return ERR_PTR(-EINVAL);
471 }
472 }
473
474 /* check QP type */
475 if (qp_type != IB_QPT_UD &&
476 qp_type != IB_QPT_UC &&
477 qp_type != IB_QPT_RC &&
478 qp_type != IB_QPT_SMI &&
479 qp_type != IB_QPT_GSI) {
480 ehca_err(pd->device, "wrong QP Type=%x", qp_type);
481 return ERR_PTR(-EINVAL);
482 }
483
484 if (is_llqp) {
485 switch (qp_type) {
486 case IB_QPT_RC:
487 if ((init_attr->cap.max_send_wr > 255) ||
488 (init_attr->cap.max_recv_wr > 255)) {
489 ehca_err(pd->device,
490 "Invalid Number of max_sq_wr=%x "
491 "or max_rq_wr=%x for RC LLQP",
492 init_attr->cap.max_send_wr,
493 init_attr->cap.max_recv_wr);
494 return ERR_PTR(-EINVAL);
495 }
496 break;
497 case IB_QPT_UD:
498 if (!EHCA_BMASK_GET(HCA_CAP_UD_LL_QP, shca->hca_cap)) {
499 ehca_err(pd->device, "UD LLQP not supported "
500 "by this adapter");
501 return ERR_PTR(-ENOSYS);
502 }
503 if (!(init_attr->cap.max_send_sge <= 5
504 && init_attr->cap.max_send_sge >= 1
505 && init_attr->cap.max_recv_sge <= 5
506 && init_attr->cap.max_recv_sge >= 1)) {
507 ehca_err(pd->device,
508 "Invalid Number of max_send_sge=%x "
509 "or max_recv_sge=%x for UD LLQP",
510 init_attr->cap.max_send_sge,
511 init_attr->cap.max_recv_sge);
512 return ERR_PTR(-EINVAL);
513 } else if (init_attr->cap.max_send_wr > 255) {
514 ehca_err(pd->device,
515 "Invalid Number of "
516 "max_send_wr=%x for UD QP_TYPE=%x",
517 init_attr->cap.max_send_wr, qp_type);
518 return ERR_PTR(-EINVAL);
519 }
520 break;
521 default:
522 ehca_err(pd->device, "unsupported LL QP Type=%x",
523 qp_type);
524 return ERR_PTR(-EINVAL);
525 break;
526 }
527 } else {
528 int max_sge = (qp_type == IB_QPT_UD || qp_type == IB_QPT_SMI
529 || qp_type == IB_QPT_GSI) ? 250 : 252;
530
531 if (init_attr->cap.max_send_sge > max_sge
532 || init_attr->cap.max_recv_sge > max_sge) {
533 ehca_err(pd->device, "Invalid number of SGEs requested "
534 "send_sge=%x recv_sge=%x max_sge=%x",
535 init_attr->cap.max_send_sge,
536 init_attr->cap.max_recv_sge, max_sge);
537 return ERR_PTR(-EINVAL);
538 }
539 }
540
541 if (pd->uobject && udata)
542 context = pd->uobject->context;
543
544 my_qp = kmem_cache_zalloc(qp_cache, GFP_KERNEL);
545 if (!my_qp) {
546 ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd);
547 return ERR_PTR(-ENOMEM);
548 }
549
550 spin_lock_init(&my_qp->spinlock_s);
551 spin_lock_init(&my_qp->spinlock_r);
552 my_qp->qp_type = qp_type;
553 my_qp->ext_type = parms.ext_type;
554
555 if (init_attr->recv_cq)
556 my_qp->recv_cq =
557 container_of(init_attr->recv_cq, struct ehca_cq, ib_cq);
558 if (init_attr->send_cq)
559 my_qp->send_cq =
560 container_of(init_attr->send_cq, struct ehca_cq, ib_cq);
561
562 do {
563 if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) {
564 ret = -ENOMEM;
565 ehca_err(pd->device, "Can't reserve idr resources.");
566 goto create_qp_exit0;
567 }
568
569 write_lock_irqsave(&ehca_qp_idr_lock, flags);
570 ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token);
571 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
572 } while (ret == -EAGAIN);
573
574 if (ret) {
575 ret = -ENOMEM;
576 ehca_err(pd->device, "Can't allocate new idr entry.");
577 goto create_qp_exit0;
578 }
579
580 if (my_qp->token > 0x1FFFFFF) {
581 ret = -EINVAL;
582 ehca_err(pd->device, "Invalid number of qp");
583 goto create_qp_exit1;
584 }
585
586 parms.servicetype = ibqptype2servicetype(qp_type);
587 if (parms.servicetype < 0) {
588 ret = -EINVAL;
589 ehca_err(pd->device, "Invalid qp_type=%x", qp_type);
590 goto create_qp_exit1;
591 }
592
593 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
594 parms.sigtype = HCALL_SIGT_EVERY;
595 else
596 parms.sigtype = HCALL_SIGT_BY_WQE;
597
598 /* UD_AV CIRCUMVENTION */
599 max_send_sge = init_attr->cap.max_send_sge;
600 max_recv_sge = init_attr->cap.max_recv_sge;
601 if (parms.servicetype == ST_UD && !is_llqp) {
602 max_send_sge += 2;
603 max_recv_sge += 2;
604 }
605
606 parms.token = my_qp->token;
607 parms.eq_handle = shca->eq.ipz_eq_handle;
608 parms.pd = my_pd->fw_pd;
609 if (my_qp->send_cq)
610 parms.send_cq_handle = my_qp->send_cq->ipz_cq_handle;
611 if (my_qp->recv_cq)
612 parms.recv_cq_handle = my_qp->recv_cq->ipz_cq_handle;
613
614 parms.squeue.max_wr = init_attr->cap.max_send_wr;
615 parms.rqueue.max_wr = init_attr->cap.max_recv_wr;
616 parms.squeue.max_sge = max_send_sge;
617 parms.rqueue.max_sge = max_recv_sge;
618
619 if (EHCA_BMASK_GET(HCA_CAP_MINI_QP, shca->hca_cap)) {
620 if (HAS_SQ(my_qp))
621 ehca_determine_small_queue(
622 &parms.squeue, max_send_sge, is_llqp);
623 if (HAS_RQ(my_qp))
624 ehca_determine_small_queue(
625 &parms.rqueue, max_recv_sge, is_llqp);
626 parms.qp_storage =
627 (parms.squeue.is_small || parms.rqueue.is_small);
628 }
629
630 h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, &parms);
631 if (h_ret != H_SUCCESS) {
632 ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%li",
633 h_ret);
634 ret = ehca2ib_return_code(h_ret);
635 goto create_qp_exit1;
636 }
637
638 ib_qp_num = my_qp->real_qp_num = parms.real_qp_num;
639 my_qp->ipz_qp_handle = parms.qp_handle;
640 my_qp->galpas = parms.galpas;
641
642 swqe_size = ehca_calc_wqe_size(parms.squeue.act_nr_sges, is_llqp);
643 rwqe_size = ehca_calc_wqe_size(parms.rqueue.act_nr_sges, is_llqp);
644
645 switch (qp_type) {
646 case IB_QPT_RC:
647 if (is_llqp) {
648 parms.squeue.act_nr_sges = 1;
649 parms.rqueue.act_nr_sges = 1;
650 }
651 break;
652 case IB_QPT_UD:
653 case IB_QPT_GSI:
654 case IB_QPT_SMI:
655 /* UD circumvention */
656 if (is_llqp) {
657 parms.squeue.act_nr_sges = 1;
658 parms.rqueue.act_nr_sges = 1;
659 } else {
660 parms.squeue.act_nr_sges -= 2;
661 parms.rqueue.act_nr_sges -= 2;
662 }
663
664 if (IB_QPT_GSI == qp_type || IB_QPT_SMI == qp_type) {
665 parms.squeue.act_nr_wqes = init_attr->cap.max_send_wr;
666 parms.rqueue.act_nr_wqes = init_attr->cap.max_recv_wr;
667 parms.squeue.act_nr_sges = init_attr->cap.max_send_sge;
668 parms.rqueue.act_nr_sges = init_attr->cap.max_recv_sge;
669 ib_qp_num = (qp_type == IB_QPT_SMI) ? 0 : 1;
670 }
671
672 break;
673
674 default:
675 break;
676 }
677
678 /* initialize r/squeue and register queue pages */
679 if (HAS_SQ(my_qp)) {
680 ret = init_qp_queue(
681 shca, my_pd, my_qp, &my_qp->ipz_squeue, 0,
682 HAS_RQ(my_qp) ? H_PAGE_REGISTERED : H_SUCCESS,
683 &parms.squeue, swqe_size);
684 if (ret) {
685 ehca_err(pd->device, "Couldn't initialize squeue "
686 "and pages ret=%i", ret);
687 goto create_qp_exit2;
688 }
689 }
690
691 if (HAS_RQ(my_qp)) {
692 ret = init_qp_queue(
693 shca, my_pd, my_qp, &my_qp->ipz_rqueue, 1,
694 H_SUCCESS, &parms.rqueue, rwqe_size);
695 if (ret) {
696 ehca_err(pd->device, "Couldn't initialize rqueue "
697 "and pages ret=%i", ret);
698 goto create_qp_exit3;
699 }
700 }
701
702 if (is_srq) {
703 my_qp->ib_srq.pd = &my_pd->ib_pd;
704 my_qp->ib_srq.device = my_pd->ib_pd.device;
705
706 my_qp->ib_srq.srq_context = init_attr->qp_context;
707 my_qp->ib_srq.event_handler = init_attr->event_handler;
708 } else {
709 my_qp->ib_qp.qp_num = ib_qp_num;
710 my_qp->ib_qp.pd = &my_pd->ib_pd;
711 my_qp->ib_qp.device = my_pd->ib_pd.device;
712
713 my_qp->ib_qp.recv_cq = init_attr->recv_cq;
714 my_qp->ib_qp.send_cq = init_attr->send_cq;
715
716 my_qp->ib_qp.qp_type = qp_type;
717 my_qp->ib_qp.srq = init_attr->srq;
718
719 my_qp->ib_qp.qp_context = init_attr->qp_context;
720 my_qp->ib_qp.event_handler = init_attr->event_handler;
721 }
722
723 init_attr->cap.max_inline_data = 0; /* not supported yet */
724 init_attr->cap.max_recv_sge = parms.rqueue.act_nr_sges;
725 init_attr->cap.max_recv_wr = parms.rqueue.act_nr_wqes;
726 init_attr->cap.max_send_sge = parms.squeue.act_nr_sges;
727 init_attr->cap.max_send_wr = parms.squeue.act_nr_wqes;
728 my_qp->init_attr = *init_attr;
729
730 /* NOTE: define_apq0() not supported yet */
731 if (qp_type == IB_QPT_GSI) {
732 h_ret = ehca_define_sqp(shca, my_qp, init_attr);
733 if (h_ret != H_SUCCESS) {
734 ret = ehca2ib_return_code(h_ret);
735 goto create_qp_exit4;
736 }
737 }
738
739 if (my_qp->send_cq) {
740 ret = ehca_cq_assign_qp(my_qp->send_cq, my_qp);
741 if (ret) {
742 ehca_err(pd->device,
743 "Couldn't assign qp to send_cq ret=%i", ret);
744 goto create_qp_exit4;
745 }
746 }
747
748 /* copy queues, galpa data to user space */
749 if (context && udata) {
750 struct ehca_create_qp_resp resp;
751 memset(&resp, 0, sizeof(resp));
752
753 resp.qp_num = my_qp->real_qp_num;
754 resp.token = my_qp->token;
755 resp.qp_type = my_qp->qp_type;
756 resp.ext_type = my_qp->ext_type;
757 resp.qkey = my_qp->qkey;
758 resp.real_qp_num = my_qp->real_qp_num;
759
760 if (HAS_SQ(my_qp))
761 queue2resp(&resp.ipz_squeue, &my_qp->ipz_squeue);
762 if (HAS_RQ(my_qp))
763 queue2resp(&resp.ipz_rqueue, &my_qp->ipz_rqueue);
764 resp.fw_handle_ofs = (u32)
765 (my_qp->galpas.user.fw_handle & (PAGE_SIZE - 1));
766
767 if (ib_copy_to_udata(udata, &resp, sizeof resp)) {
768 ehca_err(pd->device, "Copy to udata failed");
769 ret = -EINVAL;
770 goto create_qp_exit4;
771 }
772 }
773
774 return my_qp;
775
776 create_qp_exit4:
777 if (HAS_RQ(my_qp))
778 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
779
780 create_qp_exit3:
781 if (HAS_SQ(my_qp))
782 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
783
784 create_qp_exit2:
785 hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
786
787 create_qp_exit1:
788 write_lock_irqsave(&ehca_qp_idr_lock, flags);
789 idr_remove(&ehca_qp_idr, my_qp->token);
790 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
791
792 create_qp_exit0:
793 kmem_cache_free(qp_cache, my_qp);
794 return ERR_PTR(ret);
795 }
796
797 struct ib_qp *ehca_create_qp(struct ib_pd *pd,
798 struct ib_qp_init_attr *qp_init_attr,
799 struct ib_udata *udata)
800 {
801 struct ehca_qp *ret;
802
803 ret = internal_create_qp(pd, qp_init_attr, NULL, udata, 0);
804 return IS_ERR(ret) ? (struct ib_qp *)ret : &ret->ib_qp;
805 }
806
807 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
808 struct ib_uobject *uobject);
809
810 struct ib_srq *ehca_create_srq(struct ib_pd *pd,
811 struct ib_srq_init_attr *srq_init_attr,
812 struct ib_udata *udata)
813 {
814 struct ib_qp_init_attr qp_init_attr;
815 struct ehca_qp *my_qp;
816 struct ib_srq *ret;
817 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
818 ib_device);
819 struct hcp_modify_qp_control_block *mqpcb;
820 u64 hret, update_mask;
821
822 /* For common attributes, internal_create_qp() takes its info
823 * out of qp_init_attr, so copy all common attrs there.
824 */
825 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
826 qp_init_attr.event_handler = srq_init_attr->event_handler;
827 qp_init_attr.qp_context = srq_init_attr->srq_context;
828 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
829 qp_init_attr.qp_type = IB_QPT_RC;
830 qp_init_attr.cap.max_recv_wr = srq_init_attr->attr.max_wr;
831 qp_init_attr.cap.max_recv_sge = srq_init_attr->attr.max_sge;
832
833 my_qp = internal_create_qp(pd, &qp_init_attr, srq_init_attr, udata, 1);
834 if (IS_ERR(my_qp))
835 return (struct ib_srq *)my_qp;
836
837 /* copy back return values */
838 srq_init_attr->attr.max_wr = qp_init_attr.cap.max_recv_wr;
839 srq_init_attr->attr.max_sge = qp_init_attr.cap.max_recv_sge;
840
841 /* drive SRQ into RTR state */
842 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
843 if (!mqpcb) {
844 ehca_err(pd->device, "Could not get zeroed page for mqpcb "
845 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
846 ret = ERR_PTR(-ENOMEM);
847 goto create_srq1;
848 }
849
850 mqpcb->qp_state = EHCA_QPS_INIT;
851 mqpcb->prim_phys_port = 1;
852 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
853 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
854 my_qp->ipz_qp_handle,
855 &my_qp->pf,
856 update_mask,
857 mqpcb, my_qp->galpas.kernel);
858 if (hret != H_SUCCESS) {
859 ehca_err(pd->device, "Could not modify SRQ to INIT"
860 "ehca_qp=%p qp_num=%x h_ret=%li",
861 my_qp, my_qp->real_qp_num, hret);
862 goto create_srq2;
863 }
864
865 mqpcb->qp_enable = 1;
866 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
867 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
868 my_qp->ipz_qp_handle,
869 &my_qp->pf,
870 update_mask,
871 mqpcb, my_qp->galpas.kernel);
872 if (hret != H_SUCCESS) {
873 ehca_err(pd->device, "Could not enable SRQ"
874 "ehca_qp=%p qp_num=%x h_ret=%li",
875 my_qp, my_qp->real_qp_num, hret);
876 goto create_srq2;
877 }
878
879 mqpcb->qp_state = EHCA_QPS_RTR;
880 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
881 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
882 my_qp->ipz_qp_handle,
883 &my_qp->pf,
884 update_mask,
885 mqpcb, my_qp->galpas.kernel);
886 if (hret != H_SUCCESS) {
887 ehca_err(pd->device, "Could not modify SRQ to RTR"
888 "ehca_qp=%p qp_num=%x h_ret=%li",
889 my_qp, my_qp->real_qp_num, hret);
890 goto create_srq2;
891 }
892
893 ehca_free_fw_ctrlblock(mqpcb);
894
895 return &my_qp->ib_srq;
896
897 create_srq2:
898 ret = ERR_PTR(ehca2ib_return_code(hret));
899 ehca_free_fw_ctrlblock(mqpcb);
900
901 create_srq1:
902 internal_destroy_qp(pd->device, my_qp, my_qp->ib_srq.uobject);
903
904 return ret;
905 }
906
907 /*
908 * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts
909 * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe
910 * returns total number of bad wqes in bad_wqe_cnt
911 */
912 static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
913 int *bad_wqe_cnt)
914 {
915 u64 h_ret;
916 struct ipz_queue *squeue;
917 void *bad_send_wqe_p, *bad_send_wqe_v;
918 u64 q_ofs;
919 struct ehca_wqe *wqe;
920 int qp_num = my_qp->ib_qp.qp_num;
921
922 /* get send wqe pointer */
923 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
924 my_qp->ipz_qp_handle, &my_qp->pf,
925 &bad_send_wqe_p, NULL, 2);
926 if (h_ret != H_SUCCESS) {
927 ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed"
928 " ehca_qp=%p qp_num=%x h_ret=%li",
929 my_qp, qp_num, h_ret);
930 return ehca2ib_return_code(h_ret);
931 }
932 bad_send_wqe_p = (void *)((u64)bad_send_wqe_p & (~(1L << 63)));
933 ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p",
934 qp_num, bad_send_wqe_p);
935 /* convert wqe pointer to vadr */
936 bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p);
937 if (ehca_debug_level)
938 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
939 squeue = &my_qp->ipz_squeue;
940 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) {
941 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x"
942 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
943 return -EFAULT;
944 }
945
946 /* loop sets wqe's purge bit */
947 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
948 *bad_wqe_cnt = 0;
949 while (wqe->optype != 0xff && wqe->wqef != 0xff) {
950 if (ehca_debug_level)
951 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num);
952 wqe->nr_of_data_seg = 0; /* suppress data access */
953 wqe->wqef = WQEF_PURGE; /* WQE to be purged */
954 q_ofs = ipz_queue_advance_offset(squeue, q_ofs);
955 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
956 *bad_wqe_cnt = (*bad_wqe_cnt)+1;
957 }
958 /*
959 * bad wqe will be reprocessed and ignored when pol_cq() is called,
960 * i.e. nr of wqes with flush error status is one less
961 */
962 ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x",
963 qp_num, (*bad_wqe_cnt)-1);
964 wqe->wqef = 0;
965
966 return 0;
967 }
968
969 /*
970 * internal_modify_qp with circumvention to handle aqp0 properly
971 * smi_reset2init indicates if this is an internal reset-to-init-call for
972 * smi. This flag must always be zero if called from ehca_modify_qp()!
973 * This internal func was intorduced to avoid recursion of ehca_modify_qp()!
974 */
975 static int internal_modify_qp(struct ib_qp *ibqp,
976 struct ib_qp_attr *attr,
977 int attr_mask, int smi_reset2init)
978 {
979 enum ib_qp_state qp_cur_state, qp_new_state;
980 int cnt, qp_attr_idx, ret = 0;
981 enum ib_qp_statetrans statetrans;
982 struct hcp_modify_qp_control_block *mqpcb;
983 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
984 struct ehca_shca *shca =
985 container_of(ibqp->pd->device, struct ehca_shca, ib_device);
986 u64 update_mask;
987 u64 h_ret;
988 int bad_wqe_cnt = 0;
989 int squeue_locked = 0;
990 unsigned long flags = 0;
991
992 /* do query_qp to obtain current attr values */
993 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
994 if (!mqpcb) {
995 ehca_err(ibqp->device, "Could not get zeroed page for mqpcb "
996 "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num);
997 return -ENOMEM;
998 }
999
1000 h_ret = hipz_h_query_qp(shca->ipz_hca_handle,
1001 my_qp->ipz_qp_handle,
1002 &my_qp->pf,
1003 mqpcb, my_qp->galpas.kernel);
1004 if (h_ret != H_SUCCESS) {
1005 ehca_err(ibqp->device, "hipz_h_query_qp() failed "
1006 "ehca_qp=%p qp_num=%x h_ret=%li",
1007 my_qp, ibqp->qp_num, h_ret);
1008 ret = ehca2ib_return_code(h_ret);
1009 goto modify_qp_exit1;
1010 }
1011
1012 qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state);
1013
1014 if (qp_cur_state == -EINVAL) { /* invalid qp state */
1015 ret = -EINVAL;
1016 ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x "
1017 "ehca_qp=%p qp_num=%x",
1018 mqpcb->qp_state, my_qp, ibqp->qp_num);
1019 goto modify_qp_exit1;
1020 }
1021 /*
1022 * circumvention to set aqp0 initial state to init
1023 * as expected by IB spec
1024 */
1025 if (smi_reset2init == 0 &&
1026 ibqp->qp_type == IB_QPT_SMI &&
1027 qp_cur_state == IB_QPS_RESET &&
1028 (attr_mask & IB_QP_STATE) &&
1029 attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */
1030 struct ib_qp_attr smiqp_attr = {
1031 .qp_state = IB_QPS_INIT,
1032 .port_num = my_qp->init_attr.port_num,
1033 .pkey_index = 0,
1034 .qkey = 0
1035 };
1036 int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT |
1037 IB_QP_PKEY_INDEX | IB_QP_QKEY;
1038 int smirc = internal_modify_qp(
1039 ibqp, &smiqp_attr, smiqp_attr_mask, 1);
1040 if (smirc) {
1041 ehca_err(ibqp->device, "SMI RESET -> INIT failed. "
1042 "ehca_modify_qp() rc=%i", smirc);
1043 ret = H_PARAMETER;
1044 goto modify_qp_exit1;
1045 }
1046 qp_cur_state = IB_QPS_INIT;
1047 ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded");
1048 }
1049 /* is transmitted current state equal to "real" current state */
1050 if ((attr_mask & IB_QP_CUR_STATE) &&
1051 qp_cur_state != attr->cur_qp_state) {
1052 ret = -EINVAL;
1053 ehca_err(ibqp->device,
1054 "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>"
1055 " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x",
1056 attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num);
1057 goto modify_qp_exit1;
1058 }
1059
1060 ehca_dbg(ibqp->device, "ehca_qp=%p qp_num=%x current qp_state=%x "
1061 "new qp_state=%x attribute_mask=%x",
1062 my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask);
1063
1064 qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state;
1065 if (!smi_reset2init &&
1066 !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type,
1067 attr_mask)) {
1068 ret = -EINVAL;
1069 ehca_err(ibqp->device,
1070 "Invalid qp transition new_state=%x cur_state=%x "
1071 "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state,
1072 qp_cur_state, my_qp, ibqp->qp_num, attr_mask);
1073 goto modify_qp_exit1;
1074 }
1075
1076 mqpcb->qp_state = ib2ehca_qp_state(qp_new_state);
1077 if (mqpcb->qp_state)
1078 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1079 else {
1080 ret = -EINVAL;
1081 ehca_err(ibqp->device, "Invalid new qp state=%x "
1082 "ehca_qp=%p qp_num=%x",
1083 qp_new_state, my_qp, ibqp->qp_num);
1084 goto modify_qp_exit1;
1085 }
1086
1087 /* retrieve state transition struct to get req and opt attrs */
1088 statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state);
1089 if (statetrans < 0) {
1090 ret = -EINVAL;
1091 ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x "
1092 "new_qp_state=%x State_xsition=%x ehca_qp=%p "
1093 "qp_num=%x", qp_cur_state, qp_new_state,
1094 statetrans, my_qp, ibqp->qp_num);
1095 goto modify_qp_exit1;
1096 }
1097
1098 qp_attr_idx = ib2ehcaqptype(ibqp->qp_type);
1099
1100 if (qp_attr_idx < 0) {
1101 ret = qp_attr_idx;
1102 ehca_err(ibqp->device,
1103 "Invalid QP type=%x ehca_qp=%p qp_num=%x",
1104 ibqp->qp_type, my_qp, ibqp->qp_num);
1105 goto modify_qp_exit1;
1106 }
1107
1108 ehca_dbg(ibqp->device,
1109 "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x",
1110 my_qp, ibqp->qp_num, statetrans);
1111
1112 /* eHCA2 rev2 and higher require the SEND_GRH_FLAG to be set
1113 * in non-LL UD QPs.
1114 */
1115 if ((my_qp->qp_type == IB_QPT_UD) &&
1116 (my_qp->ext_type != EQPT_LLQP) &&
1117 (statetrans == IB_QPST_INIT2RTR) &&
1118 (shca->hw_level >= 0x22)) {
1119 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1120 mqpcb->send_grh_flag = 1;
1121 }
1122
1123 /* sqe -> rts: set purge bit of bad wqe before actual trans */
1124 if ((my_qp->qp_type == IB_QPT_UD ||
1125 my_qp->qp_type == IB_QPT_GSI ||
1126 my_qp->qp_type == IB_QPT_SMI) &&
1127 statetrans == IB_QPST_SQE2RTS) {
1128 /* mark next free wqe if kernel */
1129 if (!ibqp->uobject) {
1130 struct ehca_wqe *wqe;
1131 /* lock send queue */
1132 spin_lock_irqsave(&my_qp->spinlock_s, flags);
1133 squeue_locked = 1;
1134 /* mark next free wqe */
1135 wqe = (struct ehca_wqe *)
1136 ipz_qeit_get(&my_qp->ipz_squeue);
1137 wqe->optype = wqe->wqef = 0xff;
1138 ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p",
1139 ibqp->qp_num, wqe);
1140 }
1141 ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt);
1142 if (ret) {
1143 ehca_err(ibqp->device, "prepare_sqe_rts() failed "
1144 "ehca_qp=%p qp_num=%x ret=%i",
1145 my_qp, ibqp->qp_num, ret);
1146 goto modify_qp_exit2;
1147 }
1148 }
1149
1150 /*
1151 * enable RDMA_Atomic_Control if reset->init und reliable con
1152 * this is necessary since gen2 does not provide that flag,
1153 * but pHyp requires it
1154 */
1155 if (statetrans == IB_QPST_RESET2INIT &&
1156 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) {
1157 mqpcb->rdma_atomic_ctrl = 3;
1158 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1);
1159 }
1160 /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */
1161 if (statetrans == IB_QPST_INIT2RTR &&
1162 (ibqp->qp_type == IB_QPT_UC) &&
1163 !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) {
1164 mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */
1165 update_mask |=
1166 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1167 }
1168
1169 if (attr_mask & IB_QP_PKEY_INDEX) {
1170 if (attr->pkey_index >= 16) {
1171 ret = -EINVAL;
1172 ehca_err(ibqp->device, "Invalid pkey_index=%x. "
1173 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1174 attr->pkey_index, my_qp, ibqp->qp_num);
1175 goto modify_qp_exit2;
1176 }
1177 mqpcb->prim_p_key_idx = attr->pkey_index;
1178 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1);
1179 }
1180 if (attr_mask & IB_QP_PORT) {
1181 if (attr->port_num < 1 || attr->port_num > shca->num_ports) {
1182 ret = -EINVAL;
1183 ehca_err(ibqp->device, "Invalid port=%x. "
1184 "ehca_qp=%p qp_num=%x num_ports=%x",
1185 attr->port_num, my_qp, ibqp->qp_num,
1186 shca->num_ports);
1187 goto modify_qp_exit2;
1188 }
1189 mqpcb->prim_phys_port = attr->port_num;
1190 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1);
1191 }
1192 if (attr_mask & IB_QP_QKEY) {
1193 mqpcb->qkey = attr->qkey;
1194 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1);
1195 }
1196 if (attr_mask & IB_QP_AV) {
1197 int ah_mult = ib_rate_to_mult(attr->ah_attr.static_rate);
1198 int ehca_mult = ib_rate_to_mult(shca->sport[my_qp->
1199 init_attr.port_num].rate);
1200
1201 mqpcb->dlid = attr->ah_attr.dlid;
1202 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1);
1203 mqpcb->source_path_bits = attr->ah_attr.src_path_bits;
1204 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1);
1205 mqpcb->service_level = attr->ah_attr.sl;
1206 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1);
1207
1208 if (ah_mult < ehca_mult)
1209 mqpcb->max_static_rate = (ah_mult > 0) ?
1210 ((ehca_mult - 1) / ah_mult) : 0;
1211 else
1212 mqpcb->max_static_rate = 0;
1213 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1);
1214
1215 /*
1216 * Always supply the GRH flag, even if it's zero, to give the
1217 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1218 */
1219 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1220
1221 /*
1222 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1223 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1224 */
1225 if (attr->ah_attr.ah_flags == IB_AH_GRH) {
1226 mqpcb->send_grh_flag = 1;
1227
1228 mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index;
1229 update_mask |=
1230 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1);
1231
1232 for (cnt = 0; cnt < 16; cnt++)
1233 mqpcb->dest_gid.byte[cnt] =
1234 attr->ah_attr.grh.dgid.raw[cnt];
1235
1236 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1);
1237 mqpcb->flow_label = attr->ah_attr.grh.flow_label;
1238 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1);
1239 mqpcb->hop_limit = attr->ah_attr.grh.hop_limit;
1240 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1);
1241 mqpcb->traffic_class = attr->ah_attr.grh.traffic_class;
1242 update_mask |=
1243 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1);
1244 }
1245 }
1246
1247 if (attr_mask & IB_QP_PATH_MTU) {
1248 mqpcb->path_mtu = attr->path_mtu;
1249 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1);
1250 }
1251 if (attr_mask & IB_QP_TIMEOUT) {
1252 mqpcb->timeout = attr->timeout;
1253 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1);
1254 }
1255 if (attr_mask & IB_QP_RETRY_CNT) {
1256 mqpcb->retry_count = attr->retry_cnt;
1257 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1);
1258 }
1259 if (attr_mask & IB_QP_RNR_RETRY) {
1260 mqpcb->rnr_retry_count = attr->rnr_retry;
1261 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1);
1262 }
1263 if (attr_mask & IB_QP_RQ_PSN) {
1264 mqpcb->receive_psn = attr->rq_psn;
1265 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1);
1266 }
1267 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1268 mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ?
1269 attr->max_dest_rd_atomic : 2;
1270 update_mask |=
1271 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1272 }
1273 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1274 mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ?
1275 attr->max_rd_atomic : 2;
1276 update_mask |=
1277 EHCA_BMASK_SET
1278 (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1);
1279 }
1280 if (attr_mask & IB_QP_ALT_PATH) {
1281 int ah_mult = ib_rate_to_mult(attr->alt_ah_attr.static_rate);
1282 int ehca_mult = ib_rate_to_mult(
1283 shca->sport[my_qp->init_attr.port_num].rate);
1284
1285 if (attr->alt_port_num < 1
1286 || attr->alt_port_num > shca->num_ports) {
1287 ret = -EINVAL;
1288 ehca_err(ibqp->device, "Invalid alt_port=%x. "
1289 "ehca_qp=%p qp_num=%x num_ports=%x",
1290 attr->alt_port_num, my_qp, ibqp->qp_num,
1291 shca->num_ports);
1292 goto modify_qp_exit2;
1293 }
1294 mqpcb->alt_phys_port = attr->alt_port_num;
1295
1296 if (attr->alt_pkey_index >= 16) {
1297 ret = -EINVAL;
1298 ehca_err(ibqp->device, "Invalid alt_pkey_index=%x. "
1299 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1300 attr->pkey_index, my_qp, ibqp->qp_num);
1301 goto modify_qp_exit2;
1302 }
1303 mqpcb->alt_p_key_idx = attr->alt_pkey_index;
1304
1305 mqpcb->timeout_al = attr->alt_timeout;
1306 mqpcb->dlid_al = attr->alt_ah_attr.dlid;
1307 mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits;
1308 mqpcb->service_level_al = attr->alt_ah_attr.sl;
1309
1310 if (ah_mult > 0 && ah_mult < ehca_mult)
1311 mqpcb->max_static_rate_al = (ehca_mult - 1) / ah_mult;
1312 else
1313 mqpcb->max_static_rate_al = 0;
1314
1315 /* OpenIB doesn't support alternate retry counts - copy them */
1316 mqpcb->retry_count_al = mqpcb->retry_count;
1317 mqpcb->rnr_retry_count_al = mqpcb->rnr_retry_count;
1318
1319 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_ALT_PHYS_PORT, 1)
1320 | EHCA_BMASK_SET(MQPCB_MASK_ALT_P_KEY_IDX, 1)
1321 | EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT_AL, 1)
1322 | EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1)
1323 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1)
1324 | EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1)
1325 | EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1)
1326 | EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT_AL, 1)
1327 | EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT_AL, 1);
1328
1329 /*
1330 * Always supply the GRH flag, even if it's zero, to give the
1331 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1332 */
1333 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1);
1334
1335 /*
1336 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1337 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1338 */
1339 if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) {
1340 mqpcb->send_grh_flag_al = 1;
1341
1342 for (cnt = 0; cnt < 16; cnt++)
1343 mqpcb->dest_gid_al.byte[cnt] =
1344 attr->alt_ah_attr.grh.dgid.raw[cnt];
1345 mqpcb->source_gid_idx_al =
1346 attr->alt_ah_attr.grh.sgid_index;
1347 mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label;
1348 mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit;
1349 mqpcb->traffic_class_al =
1350 attr->alt_ah_attr.grh.traffic_class;
1351
1352 update_mask |=
1353 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1)
1354 | EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1)
1355 | EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1)
1356 | EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1) |
1357 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1);
1358 }
1359 }
1360
1361 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1362 mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer;
1363 update_mask |=
1364 EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1);
1365 }
1366
1367 if (attr_mask & IB_QP_SQ_PSN) {
1368 mqpcb->send_psn = attr->sq_psn;
1369 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1);
1370 }
1371
1372 if (attr_mask & IB_QP_DEST_QPN) {
1373 mqpcb->dest_qp_nr = attr->dest_qp_num;
1374 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1);
1375 }
1376
1377 if (attr_mask & IB_QP_PATH_MIG_STATE) {
1378 if (attr->path_mig_state != IB_MIG_REARM
1379 && attr->path_mig_state != IB_MIG_MIGRATED) {
1380 ret = -EINVAL;
1381 ehca_err(ibqp->device, "Invalid mig_state=%x",
1382 attr->path_mig_state);
1383 goto modify_qp_exit2;
1384 }
1385 mqpcb->path_migration_state = attr->path_mig_state + 1;
1386 update_mask |=
1387 EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1);
1388 }
1389
1390 if (attr_mask & IB_QP_CAP) {
1391 mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1;
1392 update_mask |=
1393 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1);
1394 mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1;
1395 update_mask |=
1396 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1);
1397 /* no support for max_send/recv_sge yet */
1398 }
1399
1400 if (ehca_debug_level)
1401 ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num);
1402
1403 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1404 my_qp->ipz_qp_handle,
1405 &my_qp->pf,
1406 update_mask,
1407 mqpcb, my_qp->galpas.kernel);
1408
1409 if (h_ret != H_SUCCESS) {
1410 ret = ehca2ib_return_code(h_ret);
1411 ehca_err(ibqp->device, "hipz_h_modify_qp() failed h_ret=%li "
1412 "ehca_qp=%p qp_num=%x", h_ret, my_qp, ibqp->qp_num);
1413 goto modify_qp_exit2;
1414 }
1415
1416 if ((my_qp->qp_type == IB_QPT_UD ||
1417 my_qp->qp_type == IB_QPT_GSI ||
1418 my_qp->qp_type == IB_QPT_SMI) &&
1419 statetrans == IB_QPST_SQE2RTS) {
1420 /* doorbell to reprocessing wqes */
1421 iosync(); /* serialize GAL register access */
1422 hipz_update_sqa(my_qp, bad_wqe_cnt-1);
1423 ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt);
1424 }
1425
1426 if (statetrans == IB_QPST_RESET2INIT ||
1427 statetrans == IB_QPST_INIT2INIT) {
1428 mqpcb->qp_enable = 1;
1429 mqpcb->qp_state = EHCA_QPS_INIT;
1430 update_mask = 0;
1431 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
1432
1433 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1434 my_qp->ipz_qp_handle,
1435 &my_qp->pf,
1436 update_mask,
1437 mqpcb,
1438 my_qp->galpas.kernel);
1439
1440 if (h_ret != H_SUCCESS) {
1441 ret = ehca2ib_return_code(h_ret);
1442 ehca_err(ibqp->device, "ENABLE in context of "
1443 "RESET_2_INIT failed! Maybe you didn't get "
1444 "a LID h_ret=%li ehca_qp=%p qp_num=%x",
1445 h_ret, my_qp, ibqp->qp_num);
1446 goto modify_qp_exit2;
1447 }
1448 }
1449
1450 if (statetrans == IB_QPST_ANY2RESET) {
1451 ipz_qeit_reset(&my_qp->ipz_rqueue);
1452 ipz_qeit_reset(&my_qp->ipz_squeue);
1453 }
1454
1455 if (attr_mask & IB_QP_QKEY)
1456 my_qp->qkey = attr->qkey;
1457
1458 modify_qp_exit2:
1459 if (squeue_locked) { /* this means: sqe -> rts */
1460 spin_unlock_irqrestore(&my_qp->spinlock_s, flags);
1461 my_qp->sqerr_purgeflag = 1;
1462 }
1463
1464 modify_qp_exit1:
1465 ehca_free_fw_ctrlblock(mqpcb);
1466
1467 return ret;
1468 }
1469
1470 int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1471 struct ib_udata *udata)
1472 {
1473 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1474 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1475 ib_pd);
1476 u32 cur_pid = current->tgid;
1477
1478 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1479 my_pd->ownpid != cur_pid) {
1480 ehca_err(ibqp->pd->device, "Invalid caller pid=%x ownpid=%x",
1481 cur_pid, my_pd->ownpid);
1482 return -EINVAL;
1483 }
1484
1485 return internal_modify_qp(ibqp, attr, attr_mask, 0);
1486 }
1487
1488 int ehca_query_qp(struct ib_qp *qp,
1489 struct ib_qp_attr *qp_attr,
1490 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1491 {
1492 struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
1493 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1494 ib_pd);
1495 struct ehca_shca *shca = container_of(qp->device, struct ehca_shca,
1496 ib_device);
1497 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1498 struct hcp_modify_qp_control_block *qpcb;
1499 u32 cur_pid = current->tgid;
1500 int cnt, ret = 0;
1501 u64 h_ret;
1502
1503 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1504 my_pd->ownpid != cur_pid) {
1505 ehca_err(qp->device, "Invalid caller pid=%x ownpid=%x",
1506 cur_pid, my_pd->ownpid);
1507 return -EINVAL;
1508 }
1509
1510 if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) {
1511 ehca_err(qp->device, "Invalid attribute mask "
1512 "ehca_qp=%p qp_num=%x qp_attr_mask=%x ",
1513 my_qp, qp->qp_num, qp_attr_mask);
1514 return -EINVAL;
1515 }
1516
1517 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1518 if (!qpcb) {
1519 ehca_err(qp->device, "Out of memory for qpcb "
1520 "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
1521 return -ENOMEM;
1522 }
1523
1524 h_ret = hipz_h_query_qp(adapter_handle,
1525 my_qp->ipz_qp_handle,
1526 &my_qp->pf,
1527 qpcb, my_qp->galpas.kernel);
1528
1529 if (h_ret != H_SUCCESS) {
1530 ret = ehca2ib_return_code(h_ret);
1531 ehca_err(qp->device, "hipz_h_query_qp() failed "
1532 "ehca_qp=%p qp_num=%x h_ret=%li",
1533 my_qp, qp->qp_num, h_ret);
1534 goto query_qp_exit1;
1535 }
1536
1537 qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state);
1538 qp_attr->qp_state = qp_attr->cur_qp_state;
1539
1540 if (qp_attr->cur_qp_state == -EINVAL) {
1541 ret = -EINVAL;
1542 ehca_err(qp->device, "Got invalid ehca_qp_state=%x "
1543 "ehca_qp=%p qp_num=%x",
1544 qpcb->qp_state, my_qp, qp->qp_num);
1545 goto query_qp_exit1;
1546 }
1547
1548 if (qp_attr->qp_state == IB_QPS_SQD)
1549 qp_attr->sq_draining = 1;
1550
1551 qp_attr->qkey = qpcb->qkey;
1552 qp_attr->path_mtu = qpcb->path_mtu;
1553 qp_attr->path_mig_state = qpcb->path_migration_state - 1;
1554 qp_attr->rq_psn = qpcb->receive_psn;
1555 qp_attr->sq_psn = qpcb->send_psn;
1556 qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field;
1557 qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1;
1558 qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1;
1559 /* UD_AV CIRCUMVENTION */
1560 if (my_qp->qp_type == IB_QPT_UD) {
1561 qp_attr->cap.max_send_sge =
1562 qpcb->actual_nr_sges_in_sq_wqe - 2;
1563 qp_attr->cap.max_recv_sge =
1564 qpcb->actual_nr_sges_in_rq_wqe - 2;
1565 } else {
1566 qp_attr->cap.max_send_sge =
1567 qpcb->actual_nr_sges_in_sq_wqe;
1568 qp_attr->cap.max_recv_sge =
1569 qpcb->actual_nr_sges_in_rq_wqe;
1570 }
1571
1572 qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size;
1573 qp_attr->dest_qp_num = qpcb->dest_qp_nr;
1574
1575 qp_attr->pkey_index =
1576 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx);
1577
1578 qp_attr->port_num =
1579 EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port);
1580
1581 qp_attr->timeout = qpcb->timeout;
1582 qp_attr->retry_cnt = qpcb->retry_count;
1583 qp_attr->rnr_retry = qpcb->rnr_retry_count;
1584
1585 qp_attr->alt_pkey_index =
1586 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx);
1587
1588 qp_attr->alt_port_num = qpcb->alt_phys_port;
1589 qp_attr->alt_timeout = qpcb->timeout_al;
1590
1591 qp_attr->max_dest_rd_atomic = qpcb->rdma_nr_atomic_resp_res;
1592 qp_attr->max_rd_atomic = qpcb->rdma_atomic_outst_dest_qp;
1593
1594 /* primary av */
1595 qp_attr->ah_attr.sl = qpcb->service_level;
1596
1597 if (qpcb->send_grh_flag) {
1598 qp_attr->ah_attr.ah_flags = IB_AH_GRH;
1599 }
1600
1601 qp_attr->ah_attr.static_rate = qpcb->max_static_rate;
1602 qp_attr->ah_attr.dlid = qpcb->dlid;
1603 qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits;
1604 qp_attr->ah_attr.port_num = qp_attr->port_num;
1605
1606 /* primary GRH */
1607 qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class;
1608 qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit;
1609 qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx;
1610 qp_attr->ah_attr.grh.flow_label = qpcb->flow_label;
1611
1612 for (cnt = 0; cnt < 16; cnt++)
1613 qp_attr->ah_attr.grh.dgid.raw[cnt] =
1614 qpcb->dest_gid.byte[cnt];
1615
1616 /* alternate AV */
1617 qp_attr->alt_ah_attr.sl = qpcb->service_level_al;
1618 if (qpcb->send_grh_flag_al) {
1619 qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH;
1620 }
1621
1622 qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al;
1623 qp_attr->alt_ah_attr.dlid = qpcb->dlid_al;
1624 qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al;
1625
1626 /* alternate GRH */
1627 qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al;
1628 qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al;
1629 qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al;
1630 qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al;
1631
1632 for (cnt = 0; cnt < 16; cnt++)
1633 qp_attr->alt_ah_attr.grh.dgid.raw[cnt] =
1634 qpcb->dest_gid_al.byte[cnt];
1635
1636 /* return init attributes given in ehca_create_qp */
1637 if (qp_init_attr)
1638 *qp_init_attr = my_qp->init_attr;
1639
1640 if (ehca_debug_level)
1641 ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num);
1642
1643 query_qp_exit1:
1644 ehca_free_fw_ctrlblock(qpcb);
1645
1646 return ret;
1647 }
1648
1649 int ehca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1650 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
1651 {
1652 struct ehca_qp *my_qp =
1653 container_of(ibsrq, struct ehca_qp, ib_srq);
1654 struct ehca_pd *my_pd =
1655 container_of(ibsrq->pd, struct ehca_pd, ib_pd);
1656 struct ehca_shca *shca =
1657 container_of(ibsrq->pd->device, struct ehca_shca, ib_device);
1658 struct hcp_modify_qp_control_block *mqpcb;
1659 u64 update_mask;
1660 u64 h_ret;
1661 int ret = 0;
1662
1663 u32 cur_pid = current->tgid;
1664 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1665 my_pd->ownpid != cur_pid) {
1666 ehca_err(ibsrq->pd->device, "Invalid caller pid=%x ownpid=%x",
1667 cur_pid, my_pd->ownpid);
1668 return -EINVAL;
1669 }
1670
1671 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1672 if (!mqpcb) {
1673 ehca_err(ibsrq->device, "Could not get zeroed page for mqpcb "
1674 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
1675 return -ENOMEM;
1676 }
1677
1678 update_mask = 0;
1679 if (attr_mask & IB_SRQ_LIMIT) {
1680 attr_mask &= ~IB_SRQ_LIMIT;
1681 update_mask |=
1682 EHCA_BMASK_SET(MQPCB_MASK_CURR_SRQ_LIMIT, 1)
1683 | EHCA_BMASK_SET(MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG, 1);
1684 mqpcb->curr_srq_limit =
1685 EHCA_BMASK_SET(MQPCB_CURR_SRQ_LIMIT, attr->srq_limit);
1686 mqpcb->qp_aff_asyn_ev_log_reg =
1687 EHCA_BMASK_SET(QPX_AAELOG_RESET_SRQ_LIMIT, 1);
1688 }
1689
1690 /* by now, all bits in attr_mask should have been cleared */
1691 if (attr_mask) {
1692 ehca_err(ibsrq->device, "invalid attribute mask bits set "
1693 "attr_mask=%x", attr_mask);
1694 ret = -EINVAL;
1695 goto modify_srq_exit0;
1696 }
1697
1698 if (ehca_debug_level)
1699 ehca_dmp(mqpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1700
1701 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, my_qp->ipz_qp_handle,
1702 NULL, update_mask, mqpcb,
1703 my_qp->galpas.kernel);
1704
1705 if (h_ret != H_SUCCESS) {
1706 ret = ehca2ib_return_code(h_ret);
1707 ehca_err(ibsrq->device, "hipz_h_modify_qp() failed h_ret=%li "
1708 "ehca_qp=%p qp_num=%x",
1709 h_ret, my_qp, my_qp->real_qp_num);
1710 }
1711
1712 modify_srq_exit0:
1713 ehca_free_fw_ctrlblock(mqpcb);
1714
1715 return ret;
1716 }
1717
1718 int ehca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr)
1719 {
1720 struct ehca_qp *my_qp = container_of(srq, struct ehca_qp, ib_srq);
1721 struct ehca_pd *my_pd = container_of(srq->pd, struct ehca_pd, ib_pd);
1722 struct ehca_shca *shca = container_of(srq->device, struct ehca_shca,
1723 ib_device);
1724 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1725 struct hcp_modify_qp_control_block *qpcb;
1726 u32 cur_pid = current->tgid;
1727 int ret = 0;
1728 u64 h_ret;
1729
1730 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1731 my_pd->ownpid != cur_pid) {
1732 ehca_err(srq->device, "Invalid caller pid=%x ownpid=%x",
1733 cur_pid, my_pd->ownpid);
1734 return -EINVAL;
1735 }
1736
1737 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1738 if (!qpcb) {
1739 ehca_err(srq->device, "Out of memory for qpcb "
1740 "ehca_qp=%p qp_num=%x", my_qp, my_qp->real_qp_num);
1741 return -ENOMEM;
1742 }
1743
1744 h_ret = hipz_h_query_qp(adapter_handle, my_qp->ipz_qp_handle,
1745 NULL, qpcb, my_qp->galpas.kernel);
1746
1747 if (h_ret != H_SUCCESS) {
1748 ret = ehca2ib_return_code(h_ret);
1749 ehca_err(srq->device, "hipz_h_query_qp() failed "
1750 "ehca_qp=%p qp_num=%x h_ret=%li",
1751 my_qp, my_qp->real_qp_num, h_ret);
1752 goto query_srq_exit1;
1753 }
1754
1755 srq_attr->max_wr = qpcb->max_nr_outst_recv_wr - 1;
1756 srq_attr->max_sge = qpcb->actual_nr_sges_in_rq_wqe;
1757 srq_attr->srq_limit = EHCA_BMASK_GET(
1758 MQPCB_CURR_SRQ_LIMIT, qpcb->curr_srq_limit);
1759
1760 if (ehca_debug_level)
1761 ehca_dmp(qpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1762
1763 query_srq_exit1:
1764 ehca_free_fw_ctrlblock(qpcb);
1765
1766 return ret;
1767 }
1768
1769 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
1770 struct ib_uobject *uobject)
1771 {
1772 struct ehca_shca *shca = container_of(dev, struct ehca_shca, ib_device);
1773 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1774 ib_pd);
1775 u32 cur_pid = current->tgid;
1776 u32 qp_num = my_qp->real_qp_num;
1777 int ret;
1778 u64 h_ret;
1779 u8 port_num;
1780 enum ib_qp_type qp_type;
1781 unsigned long flags;
1782
1783 if (uobject) {
1784 if (my_qp->mm_count_galpa ||
1785 my_qp->mm_count_rqueue || my_qp->mm_count_squeue) {
1786 ehca_err(dev, "Resources still referenced in "
1787 "user space qp_num=%x", qp_num);
1788 return -EINVAL;
1789 }
1790 if (my_pd->ownpid != cur_pid) {
1791 ehca_err(dev, "Invalid caller pid=%x ownpid=%x",
1792 cur_pid, my_pd->ownpid);
1793 return -EINVAL;
1794 }
1795 }
1796
1797 if (my_qp->send_cq) {
1798 ret = ehca_cq_unassign_qp(my_qp->send_cq, qp_num);
1799 if (ret) {
1800 ehca_err(dev, "Couldn't unassign qp from "
1801 "send_cq ret=%i qp_num=%x cq_num=%x", ret,
1802 qp_num, my_qp->send_cq->cq_number);
1803 return ret;
1804 }
1805 }
1806
1807 write_lock_irqsave(&ehca_qp_idr_lock, flags);
1808 idr_remove(&ehca_qp_idr, my_qp->token);
1809 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
1810
1811 h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
1812 if (h_ret != H_SUCCESS) {
1813 ehca_err(dev, "hipz_h_destroy_qp() failed h_ret=%li "
1814 "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num);
1815 return ehca2ib_return_code(h_ret);
1816 }
1817
1818 port_num = my_qp->init_attr.port_num;
1819 qp_type = my_qp->init_attr.qp_type;
1820
1821 /* no support for IB_QPT_SMI yet */
1822 if (qp_type == IB_QPT_GSI) {
1823 struct ib_event event;
1824 ehca_info(dev, "device %s: port %x is inactive.",
1825 shca->ib_device.name, port_num);
1826 event.device = &shca->ib_device;
1827 event.event = IB_EVENT_PORT_ERR;
1828 event.element.port_num = port_num;
1829 shca->sport[port_num - 1].port_state = IB_PORT_DOWN;
1830 ib_dispatch_event(&event);
1831 }
1832
1833 if (HAS_RQ(my_qp))
1834 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
1835 if (HAS_SQ(my_qp))
1836 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
1837 kmem_cache_free(qp_cache, my_qp);
1838 return 0;
1839 }
1840
1841 int ehca_destroy_qp(struct ib_qp *qp)
1842 {
1843 return internal_destroy_qp(qp->device,
1844 container_of(qp, struct ehca_qp, ib_qp),
1845 qp->uobject);
1846 }
1847
1848 int ehca_destroy_srq(struct ib_srq *srq)
1849 {
1850 return internal_destroy_qp(srq->device,
1851 container_of(srq, struct ehca_qp, ib_srq),
1852 srq->uobject);
1853 }
1854
1855 int ehca_init_qp_cache(void)
1856 {
1857 qp_cache = kmem_cache_create("ehca_cache_qp",
1858 sizeof(struct ehca_qp), 0,
1859 SLAB_HWCACHE_ALIGN,
1860 NULL);
1861 if (!qp_cache)
1862 return -ENOMEM;
1863 return 0;
1864 }
1865
1866 void ehca_cleanup_qp_cache(void)
1867 {
1868 if (qp_cache)
1869 kmem_cache_destroy(qp_cache);
1870 }
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