drivers/mtd/nand/cs553x_nand.c

   1 /*
   2  * drivers/mtd/nand/cs553x_nand.c
   3  *
   4  * (C) 2005, 2006 Red Hat Inc.
   5  *
   6  * Author: David Woodhouse <dwmw2@infradead.org>
   7  *         Tom Sylla <tom.sylla@amd.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  *  Overview:
  14  *   This is a device driver for the NAND flash controller found on
  15  *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
  16  *
  17  */
  18
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/nand.h>
  25 #include <linux/mtd/nand_ecc.h>
  26 #include <linux/mtd/partitions.h>
  27
  28 #include <asm/msr.h>
  29 #include <asm/io.h>
  30
  31 #define NR_CS553X_CONTROLLERS   4
  32
  33 #define MSR_DIVIL_GLD_CAP       0x51400000      /* DIVIL capabilitiies */
  34 #define CAP_CS5535              0x2df000ULL
  35 #define CAP_CS5536              0x5df500ULL
  36
  37 /* NAND Timing MSRs */
  38 #define MSR_NANDF_DATA          0x5140001b      /* NAND Flash Data Timing MSR */
  39 #define MSR_NANDF_CTL           0x5140001c      /* NAND Flash Control Timing */
  40 #define MSR_NANDF_RSVD          0x5140001d      /* Reserved */
  41
  42 /* NAND BAR MSRs */
  43 #define MSR_DIVIL_LBAR_FLSH0    0x51400010      /* Flash Chip Select 0 */
  44 #define MSR_DIVIL_LBAR_FLSH1    0x51400011      /* Flash Chip Select 1 */
  45 #define MSR_DIVIL_LBAR_FLSH2    0x51400012      /* Flash Chip Select 2 */
  46 #define MSR_DIVIL_LBAR_FLSH3    0x51400013      /* Flash Chip Select 3 */
  47         /* Each made up of... */
  48 #define FLSH_LBAR_EN            (1ULL<<32)
  49 #define FLSH_NOR_NAND           (1ULL<<33)      /* 1 for NAND */
  50 #define FLSH_MEM_IO             (1ULL<<34)      /* 1 for MMIO */
  51         /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
  52         /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
  53
  54 /* Pin function selection MSR (IDE vs. flash on the IDE pins) */
  55 #define MSR_DIVIL_BALL_OPTS     0x51400015
  56 #define PIN_OPT_IDE             (1<<0)  /* 0 for flash, 1 for IDE */
  57
  58 /* Registers within the NAND flash controller BAR -- memory mapped */
  59 #define MM_NAND_DATA            0x00    /* 0 to 0x7ff, in fact */
  60 #define MM_NAND_CTL             0x800   /* Any even address 0x800-0x80e */
  61 #define MM_NAND_IO              0x801   /* Any odd address 0x801-0x80f */
  62 #define MM_NAND_STS             0x810
  63 #define MM_NAND_ECC_LSB         0x811
  64 #define MM_NAND_ECC_MSB         0x812
  65 #define MM_NAND_ECC_COL         0x813
  66 #define MM_NAND_LAC             0x814
  67 #define MM_NAND_ECC_CTL         0x815
  68
  69 /* Registers within the NAND flash controller BAR -- I/O mapped */
  70 #define IO_NAND_DATA            0x00    /* 0 to 3, in fact */
  71 #define IO_NAND_CTL             0x04
  72 #define IO_NAND_IO              0x05
  73 #define IO_NAND_STS             0x06
  74 #define IO_NAND_ECC_CTL         0x08
  75 #define IO_NAND_ECC_LSB         0x09
  76 #define IO_NAND_ECC_MSB         0x0a
  77 #define IO_NAND_ECC_COL         0x0b
  78 #define IO_NAND_LAC             0x0c
  79
  80 #define CS_NAND_CTL_DIST_EN     (1<<4)  /* Enable NAND Distract interrupt */
  81 #define CS_NAND_CTL_RDY_INT_MASK        (1<<3)  /* Enable RDY/BUSY# interrupt */
  82 #define CS_NAND_CTL_ALE         (1<<2)
  83 #define CS_NAND_CTL_CLE         (1<<1)
  84 #define CS_NAND_CTL_CE          (1<<0)  /* Keep low; 1 to reset */
  85
  86 #define CS_NAND_STS_FLASH_RDY   (1<<3)
  87 #define CS_NAND_CTLR_BUSY       (1<<2)
  88 #define CS_NAND_CMD_COMP        (1<<1)
  89 #define CS_NAND_DIST_ST         (1<<0)
  90
  91 #define CS_NAND_ECC_PARITY      (1<<2)
  92 #define CS_NAND_ECC_CLRECC      (1<<1)
  93 #define CS_NAND_ECC_ENECC       (1<<0)
  94
  95 static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  96 {
  97         struct nand_chip *this = mtd->priv;
  98
  99         while (unlikely(len > 0x800)) {
 100                 memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
 101                 buf += 0x800;
 102                 len -= 0x800;
 103         }
 104         memcpy_fromio(buf, this->IO_ADDR_R, len);
 105 }
 106
 107 static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 108 {
 109         struct nand_chip *this = mtd->priv;
 110
 111         while (unlikely(len > 0x800)) {
 112                 memcpy_toio(this->IO_ADDR_R, buf, 0x800);
 113                 buf += 0x800;
 114                 len -= 0x800;
 115         }
 116         memcpy_toio(this->IO_ADDR_R, buf, len);
 117 }
 118
 119 static unsigned char cs553x_read_byte(struct mtd_info *mtd)
 120 {
 121         struct nand_chip *this = mtd->priv;
 122         return readb(this->IO_ADDR_R);
 123 }
 124
 125 static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
 126 {
 127         struct nand_chip *this = mtd->priv;
 128         int i = 100000;
 129
 130         while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
 131                 udelay(1);
 132                 i--;
 133         }
 134         writeb(byte, this->IO_ADDR_W + 0x801);
 135 }
 136
 137 static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd,
 138                              unsigned int ctrl)
 139 {
 140         struct nand_chip *this = mtd->priv;
 141         void __iomem *mmio_base = this->IO_ADDR_R;
 142         if (ctrl & NAND_CTRL_CHANGE) {
 143                 unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01;
 144                 writeb(ctl, mmio_base + MM_NAND_CTL);
 145         }
 146         if (cmd != NAND_CMD_NONE)
 147                 cs553x_write_byte(mtd, cmd);
 148 }
 149
 150 static int cs553x_device_ready(struct mtd_info *mtd)
 151 {
 152         struct nand_chip *this = mtd->priv;
 153         void __iomem *mmio_base = this->IO_ADDR_R;
 154         unsigned char foo = readb(mmio_base + MM_NAND_STS);
 155
 156         return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
 157 }
 158
 159 static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
 160 {
 161         struct nand_chip *this = mtd->priv;
 162         void __iomem *mmio_base = this->IO_ADDR_R;
 163
 164         writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
 165 }
 166
 167 static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 168 {
 169         uint32_t ecc;
 170         struct nand_chip *this = mtd->priv;
 171         void __iomem *mmio_base = this->IO_ADDR_R;
 172
 173         ecc = readl(mmio_base + MM_NAND_STS);
 174
 175         ecc_code[1] = ecc >> 8;
 176         ecc_code[0] = ecc >> 16;
 177         ecc_code[2] = ecc >> 24;
 178         return 0;
 179 }
 180
 181 static struct mtd_info *cs553x_mtd[4];
 182
 183 static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
 184 {
 185         int err = 0;
 186         struct nand_chip *this;
 187         struct mtd_info *new_mtd;
 188
 189         printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);
 190
 191         if (!mmio) {
 192                 printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
 193                 return -ENXIO;
 194         }
 195
 196         /* Allocate memory for MTD device structure and private data */
 197         new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 198         if (!new_mtd) {
 199                 printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
 200                 err = -ENOMEM;
 201                 goto out;
 202         }
 203
 204         /* Get pointer to private data */
 205         this = (struct nand_chip *)(&new_mtd[1]);
 206
 207         /* Initialize structures */
 208         memset(new_mtd, 0, sizeof(struct mtd_info));
 209         memset(this, 0, sizeof(struct nand_chip));
 210
 211         /* Link the private data with the MTD structure */
 212         new_mtd->priv = this;
 213         new_mtd->owner = THIS_MODULE;
 214
 215         /* map physical address */
 216         this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
 217         if (!this->IO_ADDR_R) {
 218                 printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
 219                 err = -EIO;
 220                 goto out_mtd;
 221         }
 222
 223         this->cmd_ctrl = cs553x_hwcontrol;
 224         this->dev_ready = cs553x_device_ready;
 225         this->read_byte = cs553x_read_byte;
 226         this->read_buf = cs553x_read_buf;
 227         this->write_buf = cs553x_write_buf;
 228
 229         this->chip_delay = 0;
 230
 231         this->ecc.mode = NAND_ECC_HW;
 232         this->ecc.size = 256;
 233         this->ecc.bytes = 3;
 234         this->ecc.hwctl  = cs_enable_hwecc;
 235         this->ecc.calculate = cs_calculate_ecc;
 236         this->ecc.correct  = nand_correct_data;
 237
 238         /* Enable the following for a flash based bad block table */
 239         this->options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR;
 240
 241         /* Scan to find existance of the device */
 242         if (nand_scan(new_mtd, 1)) {
 243                 err = -ENXIO;
 244                 goto out_ior;
 245         }
 246
 247         cs553x_mtd[cs] = new_mtd;
 248         goto out;
 249
 250 out_ior:
 251         iounmap(this->IO_ADDR_R);
 252 out_mtd:
 253         kfree(new_mtd);
 254 out:
 255         return err;
 256 }
 257
 258 static int is_geode(void)
 259 {
 260         /* These are the CPUs which will have a CS553[56] companion chip */
 261         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
 262             boot_cpu_data.x86 == 5 &&
 263             boot_cpu_data.x86_model == 10)
 264                 return 1; /* Geode LX */
 265
 266         if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
 267              boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
 268             boot_cpu_data.x86 == 5 &&
 269             boot_cpu_data.x86_model == 5)
 270                 return 1; /* Geode GX (née GX2) */
 271
 272         return 0;
 273 }
 274
 275 static int __init cs553x_init(void)
 276 {
 277         int err = -ENXIO;
 278         int i;
 279         uint64_t val;
 280
 281         /* If the CPU isn't a Geode GX or LX, abort */
 282         if (!is_geode())
 283                 return -ENXIO;
 284
 285         /* If it doesn't have the CS553[56], abort */
 286         rdmsrl(MSR_DIVIL_GLD_CAP, val);
 287         val &= ~0xFFULL;
 288         if (val != CAP_CS5535 && val != CAP_CS5536)
 289                 return -ENXIO;
 290
 291         /* If it doesn't have the NAND controller enabled, abort */
 292         rdmsrl(MSR_DIVIL_BALL_OPTS, val);
 293         if (val & 1) {
 294                 printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
 295                 return -ENXIO;
 296         }
 297
 298         for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 299                 rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
 300
 301                 if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
 302                         err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
 303         }
 304
 305         /* Register all devices together here. This means we can easily hack it to
 306            do mtdconcat etc. if we want to. */
 307         for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 308                 if (cs553x_mtd[i]) {
 309                         add_mtd_device(cs553x_mtd[i]);
 310
 311                         /* If any devices registered, return success. Else the last error. */
 312                         err = 0;
 313                 }
 314         }
 315
 316         return err;
 317 }
 318
 319 module_init(cs553x_init);
 320
 321 static void __exit cs553x_cleanup(void)
 322 {
 323         int i;
 324
 325         for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 326                 struct mtd_info *mtd = cs553x_mtd[i];
 327                 struct nand_chip *this;
 328                 void __iomem *mmio_base;
 329
 330                 if (!mtd)
 331                         break;
 332
 333                 this = cs553x_mtd[i]->priv;
 334                 mmio_base = this->IO_ADDR_R;
 335
 336                 /* Release resources, unregister device */
 337                 nand_release(cs553x_mtd[i]);
 338                 cs553x_mtd[i] = NULL;
 339
 340                 /* unmap physical adress */
 341                 iounmap(mmio_base);
 342
 343                 /* Free the MTD device structure */
 344                 kfree(mtd);
 345         }
 346 }
 347
 348 module_exit(cs553x_cleanup);
 349
 350 MODULE_LICENSE("GPL");
 351 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 352 MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");