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fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / drivers / net / chelsio / pm3393.c
blob678778a8d1338ca55adb7c824d8153e40f1495cb
1 /*****************************************************************************
2 * *
3 * File: pm3393.c *
4 * $Revision: 1.16 $ *
5 * $Date: 2005/05/14 00:59:32 $ *
6 * Description: *
7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40 #include "common.h"
41 #include "regs.h"
42 #include "gmac.h"
43 #include "elmer0.h"
44 #include "suni1x10gexp_regs.h"
45
46 #include <linux/crc32.h>
47
48 #define OFFSET(REG_ADDR) (REG_ADDR << 2)
49
50 /* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
51 #define MAX_FRAME_SIZE 9600
52
53 #define IPG 12
54 #define TXXG_CONF1_VAL ((IPG << SUNI1x10GEXP_BITOFF_TXXG_IPGT) | \
55 SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN | SUNI1x10GEXP_BITMSK_TXXG_CRCEN | \
56 SUNI1x10GEXP_BITMSK_TXXG_PADEN)
57 #define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
58 SUNI1x10GEXP_BITMSK_RXXG_FLCHK | SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP)
59
60 /* Update statistics every 15 minutes */
61 #define STATS_TICK_SECS (15 * 60)
62
63 enum { /* RMON registers */
64 RxOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW,
65 RxUnicastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW,
66 RxMulticastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW,
67 RxBroadcastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW,
68 RxPAUSEMACCtrlFramesReceived = SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW,
69 RxFrameCheckSequenceErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW,
70 RxFramesLostDueToInternalMACErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW,
71 RxSymbolErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW,
72 RxInRangeLengthErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW,
73 RxFramesTooLongErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW,
74 RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
75 RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
76 RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
77 RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW,
78 RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW,
79
80 TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
81 TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
82 TxTransmitSystemError = SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW,
83 TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
84 TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
85 TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
86 TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW,
87 TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW,
88 TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW
89 };
90
91 struct _cmac_instance {
92 u8 enabled;
93 u8 fc;
94 u8 mac_addr[6];
95 };
96
97 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
98 {
99 t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
100 return 0;
101 }
102
103 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
104 {
105 t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
106 return 0;
107 }
108
109 /* Port reset. */
110 static int pm3393_reset(struct cmac *cmac)
111 {
112 return 0;
113 }
114
115 /*
116 * Enable interrupts for the PM3393
117 *
118 * 1. Enable PM3393 BLOCK interrupts.
119 * 2. Enable PM3393 Master Interrupt bit(INTE)
120 * 3. Enable ELMER's PM3393 bit.
121 * 4. Enable Terminator external interrupt.
122 */
123 static int pm3393_interrupt_enable(struct cmac *cmac)
124 {
125 u32 pl_intr;
126
127 /* PM3393 - Enabling all hardware block interrupts.
128 */
129 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
130 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
131 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
132 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
133
134 /* Don't interrupt on statistics overflow, we are polling */
135 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
136 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
137 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
138 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
139
140 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
141 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
142 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
143 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
144 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
145 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
146 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
147 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
148 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
149
150 /* PM3393 - Global interrupt enable
151 */
152 /* TBD XXX Disable for now until we figure out why error interrupts keep asserting. */
153 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
154 0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ );
155
156 /* TERMINATOR - PL_INTERUPTS_EXT */
157 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
158 pl_intr |= F_PL_INTR_EXT;
159 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
160 return 0;
161 }
162
163 static int pm3393_interrupt_disable(struct cmac *cmac)
164 {
165 u32 elmer;
166
167 /* PM3393 - Enabling HW interrupt blocks. */
168 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
169 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
170 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
171 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
172 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
173 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
174 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
175 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
176 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
177 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
178 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
179 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
180 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
181 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
182 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
183 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
184 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
185
186 /* PM3393 - Global interrupt enable */
187 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
188
189 /* ELMER - External chip interrupts. */
190 t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
191 elmer &= ~ELMER0_GP_BIT1;
192 t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
193
194 /* TERMINATOR - PL_INTERUPTS_EXT */
195 /* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP
196 * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level.
197 */
198
199 return 0;
200 }
201
202 static int pm3393_interrupt_clear(struct cmac *cmac)
203 {
204 u32 elmer;
205 u32 pl_intr;
206 u32 val32;
207
208 /* PM3393 - Clearing HW interrupt blocks. Note, this assumes
209 * bit WCIMODE=0 for a clear-on-read.
210 */
211 pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
212 pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
213 pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
214 pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
215 pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
216 pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
217 pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
218 pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
219 pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
220 pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
221 pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
222 pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
223 &val32);
224 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
225 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
226
227 /* PM3393 - Global interrupt status
228 */
229 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
230
231 /* ELMER - External chip interrupts.
232 */
233 t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
234 elmer |= ELMER0_GP_BIT1;
235 t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
236
237 /* TERMINATOR - PL_INTERUPTS_EXT
238 */
239 pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
240 pl_intr |= F_PL_INTR_EXT;
241 writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
242
243 return 0;
244 }
245
246 /* Interrupt handler */
247 static int pm3393_interrupt_handler(struct cmac *cmac)
248 {
249 u32 master_intr_status;
250
251 /* Read the master interrupt status register. */
252 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
253 &master_intr_status);
254 CH_DBG(cmac->adapter, INTR, "PM3393 intr cause 0x%x\n",
255 master_intr_status);
256
257 /* TBD XXX Lets just clear everything for now */
258 pm3393_interrupt_clear(cmac);
259
260 return 0;
261 }
262
263 static int pm3393_enable(struct cmac *cmac, int which)
264 {
265 if (which & MAC_DIRECTION_RX)
266 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
267 (RXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_RXXG_RXEN));
268
269 if (which & MAC_DIRECTION_TX) {
270 u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0;
271
272 if (cmac->instance->fc & PAUSE_RX)
273 val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX;
274 if (cmac->instance->fc & PAUSE_TX)
275 val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX;
276 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
277 }
278
279 cmac->instance->enabled |= which;
280 return 0;
281 }
282
283 static int pm3393_enable_port(struct cmac *cmac, int which)
284 {
285 /* Clear port statistics */
286 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
287 SUNI1x10GEXP_BITMSK_MSTAT_CLEAR);
288 udelay(2);
289 memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
290
291 pm3393_enable(cmac, which);
292
293 /*
294 * XXX This should be done by the PHY and preferrably not at all.
295 * The PHY doesn't give us link status indication on its own so have
296 * the link management code query it instead.
297 */
298 t1_link_changed(cmac->adapter, 0);
299 return 0;
300 }
301
302 static int pm3393_disable(struct cmac *cmac, int which)
303 {
304 if (which & MAC_DIRECTION_RX)
305 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
306 if (which & MAC_DIRECTION_TX)
307 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
308
309 /*
310 * The disable is graceful. Give the PM3393 time. Can't wait very
311 * long here, we may be holding locks.
312 */
313 udelay(20);
314
315 cmac->instance->enabled &= ~which;
316 return 0;
317 }
318
319 static int pm3393_loopback_enable(struct cmac *cmac)
320 {
321 return 0;
322 }
323
324 static int pm3393_loopback_disable(struct cmac *cmac)
325 {
326 return 0;
327 }
328
329 static int pm3393_set_mtu(struct cmac *cmac, int mtu)
330 {
331 int enabled = cmac->instance->enabled;
332
333 /* MAX_FRAME_SIZE includes header + FCS, mtu doesn't */
334 mtu += 14 + 4;
335 if (mtu > MAX_FRAME_SIZE)
336 return -EINVAL;
337
338 /* Disable Rx/Tx MAC before configuring it. */
339 if (enabled)
340 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
341
342 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
343 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
344
345 if (enabled)
346 pm3393_enable(cmac, enabled);
347 return 0;
348 }
349
350 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
351 {
352 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
353 u32 rx_mode;
354
355 /* Disable MAC RX before reconfiguring it */
356 if (enabled)
357 pm3393_disable(cmac, MAC_DIRECTION_RX);
358
359 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
360 rx_mode &= ~(SUNI1x10GEXP_BITMSK_RXXG_PMODE |
361 SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN);
362 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
363 (u16)rx_mode);
364
365 if (t1_rx_mode_promisc(rm)) {
366 /* Promiscuous mode. */
367 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_PMODE;
368 }
369 if (t1_rx_mode_allmulti(rm)) {
370 /* Accept all multicast. */
371 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
372 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
373 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
374 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
375 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
376 } else if (t1_rx_mode_mc_cnt(rm)) {
377 /* Accept one or more multicast(s). */
378 u8 *addr;
379 int bit;
380 u16 mc_filter[4] = { 0, };
381
382 while ((addr = t1_get_next_mcaddr(rm))) {
383 bit = (ether_crc(ETH_ALEN, addr) >> 23) & 0x3f; /* bit[23:28] */
384 mc_filter[bit >> 4] |= 1 << (bit & 0xf);
385 }
386 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
387 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
388 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
389 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
390 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
391 }
392
393 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
394
395 if (enabled)
396 pm3393_enable(cmac, MAC_DIRECTION_RX);
397
398 return 0;
399 }
400
401 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
402 int *duplex, int *fc)
403 {
404 if (speed)
405 *speed = SPEED_10000;
406 if (duplex)
407 *duplex = DUPLEX_FULL;
408 if (fc)
409 *fc = cmac->instance->fc;
410 return 0;
411 }
412
413 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
414 int fc)
415 {
416 if (speed >= 0 && speed != SPEED_10000)
417 return -1;
418 if (duplex >= 0 && duplex != DUPLEX_FULL)
419 return -1;
420 if (fc & ~(PAUSE_TX | PAUSE_RX))
421 return -1;
422
423 if (fc != cmac->instance->fc) {
424 cmac->instance->fc = (u8) fc;
425 if (cmac->instance->enabled & MAC_DIRECTION_TX)
426 pm3393_enable(cmac, MAC_DIRECTION_TX);
427 }
428 return 0;
429 }
430
431 static void pm3393_rmon_update(struct adapter *adapter, u32 offs, u64 *val,
432 int over)
433 {
434 u32 val0, val1, val2;
435
436 t1_tpi_read(adapter, offs, &val0);
437 t1_tpi_read(adapter, offs + 4, &val1);
438 t1_tpi_read(adapter, offs + 8, &val2);
439
440 *val &= ~0ull << 40;
441 *val |= val0 & 0xffff;
442 *val |= (val1 & 0xffff) << 16;
443 *val |= (u64)(val2 & 0xff) << 32;
444
445 if (over)
446 *val += 1ull << 40;
447 }
448
449 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
450 int flag)
451 {
452 static struct {
453 unsigned int reg;
454 unsigned int offset;
455 } hw_stats [] = {
456
457 #define HW_STAT(name, stat_name) \
458 { name, (&((struct cmac_statistics *)NULL)->stat_name) - (u64 *)NULL }
459
460 /* Rx stats */
461 HW_STAT(RxOctetsReceivedOK, RxOctetsOK),
462 HW_STAT(RxUnicastFramesReceivedOK, RxUnicastFramesOK),
463 HW_STAT(RxMulticastFramesReceivedOK, RxMulticastFramesOK),
464 HW_STAT(RxBroadcastFramesReceivedOK, RxBroadcastFramesOK),
465 HW_STAT(RxPAUSEMACCtrlFramesReceived, RxPauseFrames),
466 HW_STAT(RxFrameCheckSequenceErrors, RxFCSErrors),
467 HW_STAT(RxFramesLostDueToInternalMACErrors,
468 RxInternalMACRcvError),
469 HW_STAT(RxSymbolErrors, RxSymbolErrors),
470 HW_STAT(RxInRangeLengthErrors, RxInRangeLengthErrors),
471 HW_STAT(RxFramesTooLongErrors , RxFrameTooLongErrors),
472 HW_STAT(RxJabbers, RxJabberErrors),
473 HW_STAT(RxFragments, RxRuntErrors),
474 HW_STAT(RxUndersizedFrames, RxRuntErrors),
475 HW_STAT(RxJumboFramesReceivedOK, RxJumboFramesOK),
476 HW_STAT(RxJumboOctetsReceivedOK, RxJumboOctetsOK),
477
478 /* Tx stats */
479 HW_STAT(TxOctetsTransmittedOK, TxOctetsOK),
480 HW_STAT(TxFramesLostDueToInternalMACTransmissionError,
481 TxInternalMACXmitError),
482 HW_STAT(TxTransmitSystemError, TxFCSErrors),
483 HW_STAT(TxUnicastFramesTransmittedOK, TxUnicastFramesOK),
484 HW_STAT(TxMulticastFramesTransmittedOK, TxMulticastFramesOK),
485 HW_STAT(TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK),
486 HW_STAT(TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames),
487 HW_STAT(TxJumboFramesReceivedOK, TxJumboFramesOK),
488 HW_STAT(TxJumboOctetsReceivedOK, TxJumboOctetsOK)
489 }, *p = hw_stats;
490 u64 ro;
491 u32 val0, val1, val2, val3;
492 u64 *stats = (u64 *) &mac->stats;
493 unsigned int i;
494
495 /* Snap the counters */
496 pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
497 SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
498
499 /* Counter rollover, clear on read */
500 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0);
501 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1, &val1);
502 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2, &val2);
503 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3, &val3);
504 ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
505 (((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48);
506
507 for (i = 0; i < ARRAY_SIZE(hw_stats); i++) {
508 unsigned reg = p->reg - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW;
509
510 pm3393_rmon_update((mac)->adapter, OFFSET(p->reg),
511 stats + p->offset, ro & (reg >> 2));
512 }
513
514
515
516 return &mac->stats;
517 }
518
519 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
520 {
521 memcpy(mac_addr, cmac->instance->mac_addr, 6);
522 return 0;
523 }
524
525 static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
526 {
527 u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
528
529 /*
530 * MAC addr: 00:07:43:00:13:09
531 *
532 * ma[5] = 0x09
533 * ma[4] = 0x13
534 * ma[3] = 0x00
535 * ma[2] = 0x43
536 * ma[1] = 0x07
537 * ma[0] = 0x00
538 *
539 * The PM3393 requires byte swapping and reverse order entry
540 * when programming MAC addresses:
541 *
542 * low_bits[15:0] = ma[1]:ma[0]
543 * mid_bits[31:16] = ma[3]:ma[2]
544 * high_bits[47:32] = ma[5]:ma[4]
545 */
546
547 /* Store local copy */
548 memcpy(cmac->instance->mac_addr, ma, 6);
549
550 lo = ((u32) ma[1] << 8) | (u32) ma[0];
551 mid = ((u32) ma[3] << 8) | (u32) ma[2];
552 hi = ((u32) ma[5] << 8) | (u32) ma[4];
553
554 /* Disable Rx/Tx MAC before configuring it. */
555 if (enabled)
556 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
557
558 /* Set RXXG Station Address */
559 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
560 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
561 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
562
563 /* Set TXXG Station Address */
564 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
565 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
566 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
567
568 /* Setup Exact Match Filter 1 with our MAC address
569 *
570 * Must disable exact match filter before configuring it.
571 */
572 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
573 val &= 0xff0f;
574 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
575
576 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
577 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
578 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
579
580 val |= 0x0090;
581 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
582
583 if (enabled)
584 pm3393_enable(cmac, enabled);
585 return 0;
586 }
587
588 static void pm3393_destroy(struct cmac *cmac)
589 {
590 kfree(cmac);
591 }
592
593 static struct cmac_ops pm3393_ops = {
594 .destroy = pm3393_destroy,
595 .reset = pm3393_reset,
596 .interrupt_enable = pm3393_interrupt_enable,
597 .interrupt_disable = pm3393_interrupt_disable,
598 .interrupt_clear = pm3393_interrupt_clear,
599 .interrupt_handler = pm3393_interrupt_handler,
600 .enable = pm3393_enable_port,
601 .disable = pm3393_disable,
602 .loopback_enable = pm3393_loopback_enable,
603 .loopback_disable = pm3393_loopback_disable,
604 .set_mtu = pm3393_set_mtu,
605 .set_rx_mode = pm3393_set_rx_mode,
606 .get_speed_duplex_fc = pm3393_get_speed_duplex_fc,
607 .set_speed_duplex_fc = pm3393_set_speed_duplex_fc,
608 .statistics_update = pm3393_update_statistics,
609 .macaddress_get = pm3393_macaddress_get,
610 .macaddress_set = pm3393_macaddress_set
611 };
612
613 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
614 {
615 struct cmac *cmac;
616
617 cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
618 if (!cmac)
619 return NULL;
620
621 cmac->ops = &pm3393_ops;
622 cmac->instance = (cmac_instance *) (cmac + 1);
623 cmac->adapter = adapter;
624 cmac->instance->fc = PAUSE_TX | PAUSE_RX;
625
626 t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
627 t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
628 t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
629 t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */
630 t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
631 t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
632 t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
633 t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
634 t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
635 t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
636 t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
637 t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
638 t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
639 t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
640 t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
641 t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
642 t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
643 t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
644 t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
645 t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
646 t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
647 t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */
648
649 t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */
650 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */
651 t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */
652 t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */
653 t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */
654 t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */
655 t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */
656 t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */
657 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */
658 t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */
659 t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */
660 t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit are undocumented */
661 t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */
662
663 t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */
664 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */
665 t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */
666 t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */
667 t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */
668 t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */
669 t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */
670 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */
671 t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */
672 t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */
673 t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other bit are undocumented */
674
675 t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */
676 t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */
677 t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */
678 t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */
679 t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */
680 t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */
681
682 t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */
683 t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */
684
685 t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
686 t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */
687
688 t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */
689 /* For T1 use timer based Mac flow control. */
690 t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
691 t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */
692 t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */
693 t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */
694
695 /* Setup Exact Match Filter 0 to allow broadcast packets.
696 */
697 t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */
698 t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */
699 t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */
700 t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */
701 t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */
702
703 t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */
704 t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */
705 t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */
706
707 return cmac;
708 }
709
710 static int pm3393_mac_reset(adapter_t * adapter)
711 {
712 u32 val;
713 u32 x;
714 u32 is_pl4_reset_finished;
715 u32 is_pl4_outof_lock;
716 u32 is_xaui_mabc_pll_locked;
717 u32 successful_reset;
718 int i;
719
720 /* The following steps are required to properly reset
721 * the PM3393. This information is provided in the
722 * PM3393 datasheet (Issue 2: November 2002)
723 * section 13.1 -- Device Reset.
724 *
725 * The PM3393 has three types of components that are
726 * individually reset:
727 *
728 * DRESETB - Digital circuitry
729 * PL4_ARESETB - PL4 analog circuitry
730 * XAUI_ARESETB - XAUI bus analog circuitry
731 *
732 * Steps to reset PM3393 using RSTB pin:
733 *
734 * 1. Assert RSTB pin low ( write 0 )
735 * 2. Wait at least 1ms to initiate a complete initialization of device.
736 * 3. Wait until all external clocks and REFSEL are stable.
737 * 4. Wait minimum of 1ms. (after external clocks and REFEL are stable)
738 * 5. De-assert RSTB ( write 1 )
739 * 6. Wait until internal timers to expires after ~14ms.
740 * - Allows analog clock synthesizer(PL4CSU) to stabilize to
741 * selected reference frequency before allowing the digital
742 * portion of the device to operate.
743 * 7. Wait at least 200us for XAUI interface to stabilize.
744 * 8. Verify the PM3393 came out of reset successfully.
745 * Set successful reset flag if everything worked else try again
746 * a few more times.
747 */
748
749 successful_reset = 0;
750 for (i = 0; i < 3 && !successful_reset; i++) {
751 /* 1 */
752 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
753 val &= ~1;
754 t1_tpi_write(adapter, A_ELMER0_GPO, val);
755
756 /* 2 */
757 msleep(1);
758
759 /* 3 */
760 msleep(1);
761
762 /* 4 */
763 msleep(2 /*1 extra ms for safety */ );
764
765 /* 5 */
766 val |= 1;
767 t1_tpi_write(adapter, A_ELMER0_GPO, val);
768
769 /* 6 */
770 msleep(15 /*1 extra ms for safety */ );
771
772 /* 7 */
773 msleep(1);
774
775 /* 8 */
776
777 /* Has PL4 analog block come out of reset correctly? */
778 t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);
779 is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED);
780
781 /* TBD XXX SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL gets locked later in the init sequence
782 * figure out why? */
783
784 /* Have all PL4 block clocks locked? */
785 x = (SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL
786 /*| SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL */ |
787 SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL |
788 SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL |
789 SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL);
790 is_pl4_outof_lock = (val & x);
791
792 /* ??? If this fails, might be able to software reset the XAUI part
793 * and try to recover... thus saving us from doing another HW reset */
794 /* Has the XAUI MABC PLL circuitry stablized? */
795 is_xaui_mabc_pll_locked =
796 (val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED);
797
798 successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
799 && is_xaui_mabc_pll_locked);
800
801 CH_DBG(adapter, HW,
802 "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, "
803 "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n",
804 i, is_pl4_reset_finished, val, is_pl4_outof_lock,
805 is_xaui_mabc_pll_locked);
806 }
807 return successful_reset ? 0 : 1;
808 }
809
810 const struct gmac t1_pm3393_ops = {
811 .stats_update_period = STATS_TICK_SECS,
812 .create = pm3393_mac_create,
813 .reset = pm3393_mac_reset,
814 };
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