?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / drivers / net / epic100.c
blobecdd3fc8d70ca8af89dc4fbd2f3033139a1fbeb0
1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22 [this link no longer provides anything useful -jgarzik]
23
24 ---------------------------------------------------------------------
25
26 */
27
28 #define DRV_NAME "epic100"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sept 11, 2006"
31
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37 /* Used to pass the full-duplex flag, etc. */
38 #define MAX_UNITS 8 /* More are supported, limit only on options */
39 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44 static int rx_copybreak;
45
46 /* Operational parameters that are set at compile time. */
47
48 /* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53 #define TX_RING_SIZE 256
54 #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55 #define RX_RING_SIZE 256
56 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59 /* Operational parameters that usually are not changed. */
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (2*HZ)
62
63 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65 /* Bytes transferred to chip before transmission starts. */
66 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67 #define TX_FIFO_THRESH 256
68 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/errno.h>
75 #include <linux/ioport.h>
76 #include <linux/slab.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/delay.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/spinlock.h>
85 #include <linux/ethtool.h>
86 #include <linux/mii.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89 #include <asm/io.h>
90 #include <asm/uaccess.h>
91
92 /* These identify the driver base version and may not be removed. */
93 static char version[] __devinitdata =
94 DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
95 static char version2[] __devinitdata =
96 " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
97
98 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
99 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
100 MODULE_LICENSE("GPL");
101
102 module_param(debug, int, 0);
103 module_param(rx_copybreak, int, 0);
104 module_param_array(options, int, NULL, 0);
105 module_param_array(full_duplex, int, NULL, 0);
106 MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107 MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
108 MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
109 MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
110
111 /*
112 Theory of Operation
113
114 I. Board Compatibility
115
116 This device driver is designed for the SMC "EPIC/100", the SMC
117 single-chip Ethernet controllers for PCI. This chip is used on
118 the SMC EtherPower II boards.
119
120 II. Board-specific settings
121
122 PCI bus devices are configured by the system at boot time, so no jumpers
123 need to be set on the board. The system BIOS will assign the
124 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
125 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
126 interrupt lines.
127
128 III. Driver operation
129
130 IIIa. Ring buffers
131
132 IVb. References
133
134 http://www.smsc.com/main/datasheets/83c171.pdf
135 http://www.smsc.com/main/datasheets/83c175.pdf
136 http://scyld.com/expert/NWay.html
137 http://www.national.com/pf/DP/DP83840A.html
138
139 IVc. Errata
140
141 */
142
143
144 enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
145
146 #define EPIC_TOTAL_SIZE 0x100
147 #define USE_IO_OPS 1
148
149 typedef enum {
150 SMSC_83C170_0,
151 SMSC_83C170,
152 SMSC_83C175,
153 } chip_t;
154
155
156 struct epic_chip_info {
157 const char *name;
158 int drv_flags; /* Driver use, intended as capability flags. */
159 };
160
161
162 /* indexed by chip_t */
163 static const struct epic_chip_info pci_id_tbl[] = {
164 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
165 { "SMSC EPIC/100 83c170", TYPE2_INTR },
166 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
167 };
168
169
170 static struct pci_device_id epic_pci_tbl[] = {
171 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
172 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
173 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
174 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
175 { 0,}
176 };
177 MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
178
179
180 #ifndef USE_IO_OPS
181 #undef inb
182 #undef inw
183 #undef inl
184 #undef outb
185 #undef outw
186 #undef outl
187 #define inb readb
188 #define inw readw
189 #define inl readl
190 #define outb writeb
191 #define outw writew
192 #define outl writel
193 #endif
194
195 /* Offsets to registers, using the (ugh) SMC names. */
196 enum epic_registers {
197 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
198 PCIBurstCnt=0x18,
199 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
200 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
201 LAN0=64, /* MAC address. */
202 MC0=80, /* Multicast filter table. */
203 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
204 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205 };
206
207 /* Interrupt register bits, using my own meaningful names. */
208 enum IntrStatus {
209 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
210 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
211 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
212 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
213 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
214 };
215 enum CommandBits {
216 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
217 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
218 };
219
220 #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221
222 #define EpicNapiEvent (TxEmpty | TxDone | \
223 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
224 #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225
226 static const u16 media2miictl[16] = {
227 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0 };
229
230 /* The EPIC100 Rx and Tx buffer descriptors. */
231
232 struct epic_tx_desc {
233 u32 txstatus;
234 u32 bufaddr;
235 u32 buflength;
236 u32 next;
237 };
238
239 struct epic_rx_desc {
240 u32 rxstatus;
241 u32 bufaddr;
242 u32 buflength;
243 u32 next;
244 };
245
246 enum desc_status_bits {
247 DescOwn=0x8000,
248 };
249
250 #define PRIV_ALIGN 15 /* Required alignment mask */
251 struct epic_private {
252 struct epic_rx_desc *rx_ring;
253 struct epic_tx_desc *tx_ring;
254 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
255 struct sk_buff* tx_skbuff[TX_RING_SIZE];
256 /* The addresses of receive-in-place skbuffs. */
257 struct sk_buff* rx_skbuff[RX_RING_SIZE];
258
259 dma_addr_t tx_ring_dma;
260 dma_addr_t rx_ring_dma;
261
262 /* Ring pointers. */
263 spinlock_t lock; /* Group with Tx control cache line. */
264 spinlock_t napi_lock;
265 struct napi_struct napi;
266 unsigned int reschedule_in_poll;
267 unsigned int cur_tx, dirty_tx;
268
269 unsigned int cur_rx, dirty_rx;
270 u32 irq_mask;
271 unsigned int rx_buf_sz; /* Based on MTU+slack. */
272
273 struct pci_dev *pci_dev; /* PCI bus location. */
274 int chip_id, chip_flags;
275
276 struct net_device_stats stats;
277 struct timer_list timer; /* Media selection timer. */
278 int tx_threshold;
279 unsigned char mc_filter[8];
280 signed char phys[4]; /* MII device addresses. */
281 u16 advertising; /* NWay media advertisement */
282 int mii_phy_cnt;
283 struct mii_if_info mii;
284 unsigned int tx_full:1; /* The Tx queue is full. */
285 unsigned int default_port:4; /* Last dev->if_port value. */
286 };
287
288 static int epic_open(struct net_device *dev);
289 static int read_eeprom(long ioaddr, int location);
290 static int mdio_read(struct net_device *dev, int phy_id, int location);
291 static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
292 static void epic_restart(struct net_device *dev);
293 static void epic_timer(unsigned long data);
294 static void epic_tx_timeout(struct net_device *dev);
295 static void epic_init_ring(struct net_device *dev);
296 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
297 static int epic_rx(struct net_device *dev, int budget);
298 static int epic_poll(struct napi_struct *napi, int budget);
299 static irqreturn_t epic_interrupt(int irq, void *dev_instance);
300 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
301 static const struct ethtool_ops netdev_ethtool_ops;
302 static int epic_close(struct net_device *dev);
303 static struct net_device_stats *epic_get_stats(struct net_device *dev);
304 static void set_rx_mode(struct net_device *dev);
305
306
307
308 static int __devinit epic_init_one (struct pci_dev *pdev,
309 const struct pci_device_id *ent)
310 {
311 static int card_idx = -1;
312 long ioaddr;
313 int chip_idx = (int) ent->driver_data;
314 int irq;
315 struct net_device *dev;
316 struct epic_private *ep;
317 int i, ret, option = 0, duplex = 0;
318 void *ring_space;
319 dma_addr_t ring_dma;
320 DECLARE_MAC_BUF(mac);
321
322 /* when built into the kernel, we only print version if device is found */
323 #ifndef MODULE
324 static int printed_version;
325 if (!printed_version++)
326 printk (KERN_INFO "%s" KERN_INFO "%s",
327 version, version2);
328 #endif
329
330 card_idx++;
331
332 ret = pci_enable_device(pdev);
333 if (ret)
334 goto out;
335 irq = pdev->irq;
336
337 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
338 dev_err(&pdev->dev, "no PCI region space\n");
339 ret = -ENODEV;
340 goto err_out_disable;
341 }
342
343 pci_set_master(pdev);
344
345 ret = pci_request_regions(pdev, DRV_NAME);
346 if (ret < 0)
347 goto err_out_disable;
348
349 ret = -ENOMEM;
350
351 dev = alloc_etherdev(sizeof (*ep));
352 if (!dev) {
353 dev_err(&pdev->dev, "no memory for eth device\n");
354 goto err_out_free_res;
355 }
356 SET_NETDEV_DEV(dev, &pdev->dev);
357
358 #ifdef USE_IO_OPS
359 ioaddr = pci_resource_start (pdev, 0);
360 #else
361 ioaddr = pci_resource_start (pdev, 1);
362 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
363 if (!ioaddr) {
364 dev_err(&pdev->dev, "ioremap failed\n");
365 goto err_out_free_netdev;
366 }
367 #endif
368
369 pci_set_drvdata(pdev, dev);
370 ep = dev->priv;
371 ep->mii.dev = dev;
372 ep->mii.mdio_read = mdio_read;
373 ep->mii.mdio_write = mdio_write;
374 ep->mii.phy_id_mask = 0x1f;
375 ep->mii.reg_num_mask = 0x1f;
376
377 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
378 if (!ring_space)
379 goto err_out_iounmap;
380 ep->tx_ring = (struct epic_tx_desc *)ring_space;
381 ep->tx_ring_dma = ring_dma;
382
383 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
384 if (!ring_space)
385 goto err_out_unmap_tx;
386 ep->rx_ring = (struct epic_rx_desc *)ring_space;
387 ep->rx_ring_dma = ring_dma;
388
389 if (dev->mem_start) {
390 option = dev->mem_start;
391 duplex = (dev->mem_start & 16) ? 1 : 0;
392 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
393 if (options[card_idx] >= 0)
394 option = options[card_idx];
395 if (full_duplex[card_idx] >= 0)
396 duplex = full_duplex[card_idx];
397 }
398
399 dev->base_addr = ioaddr;
400 dev->irq = irq;
401
402 spin_lock_init(&ep->lock);
403 spin_lock_init(&ep->napi_lock);
404 ep->reschedule_in_poll = 0;
405
406 /* Bring the chip out of low-power mode. */
407 outl(0x4200, ioaddr + GENCTL);
408 /* Magic?! If we don't set this bit the MII interface won't work. */
409 /* This magic is documented in SMSC app note 7.15 */
410 for (i = 16; i > 0; i--)
411 outl(0x0008, ioaddr + TEST1);
412
413 /* Turn on the MII transceiver. */
414 outl(0x12, ioaddr + MIICfg);
415 if (chip_idx == 1)
416 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
417 outl(0x0200, ioaddr + GENCTL);
418
419 /* Note: the '175 does not have a serial EEPROM. */
420 for (i = 0; i < 3; i++)
421 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
422
423 if (debug > 2) {
424 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
425 for (i = 0; i < 64; i++)
426 printk(" %4.4x%s", read_eeprom(ioaddr, i),
427 i % 16 == 15 ? "\n" : "");
428 }
429
430 ep->pci_dev = pdev;
431 ep->chip_id = chip_idx;
432 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
433 ep->irq_mask =
434 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
435 | CntFull | TxUnderrun | EpicNapiEvent;
436
437 /* Find the connected MII xcvrs.
438 Doing this in open() would allow detecting external xcvrs later, but
439 takes much time and no cards have external MII. */
440 {
441 int phy, phy_idx = 0;
442 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
443 int mii_status = mdio_read(dev, phy, MII_BMSR);
444 if (mii_status != 0xffff && mii_status != 0x0000) {
445 ep->phys[phy_idx++] = phy;
446 dev_info(&pdev->dev,
447 "MII transceiver #%d control "
448 "%4.4x status %4.4x.\n",
449 phy, mdio_read(dev, phy, 0), mii_status);
450 }
451 }
452 ep->mii_phy_cnt = phy_idx;
453 if (phy_idx != 0) {
454 phy = ep->phys[0];
455 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
456 dev_info(&pdev->dev,
457 "Autonegotiation advertising %4.4x link "
458 "partner %4.4x.\n",
459 ep->mii.advertising, mdio_read(dev, phy, 5));
460 } else if ( ! (ep->chip_flags & NO_MII)) {
461 dev_warn(&pdev->dev,
462 "***WARNING***: No MII transceiver found!\n");
463 /* Use the known PHY address of the EPII. */
464 ep->phys[0] = 3;
465 }
466 ep->mii.phy_id = ep->phys[0];
467 }
468
469 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
470 if (ep->chip_flags & MII_PWRDWN)
471 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
472 outl(0x0008, ioaddr + GENCTL);
473
474 /* The lower four bits are the media type. */
475 if (duplex) {
476 ep->mii.force_media = ep->mii.full_duplex = 1;
477 dev_info(&pdev->dev, "Forced full duplex requested.\n");
478 }
479 dev->if_port = ep->default_port = option;
480
481 /* The Epic-specific entries in the device structure. */
482 dev->open = &epic_open;
483 dev->hard_start_xmit = &epic_start_xmit;
484 dev->stop = &epic_close;
485 dev->get_stats = &epic_get_stats;
486 dev->set_multicast_list = &set_rx_mode;
487 dev->do_ioctl = &netdev_ioctl;
488 dev->ethtool_ops = &netdev_ethtool_ops;
489 dev->watchdog_timeo = TX_TIMEOUT;
490 dev->tx_timeout = &epic_tx_timeout;
491 netif_napi_add(dev, &ep->napi, epic_poll, 64);
492
493 ret = register_netdev(dev);
494 if (ret < 0)
495 goto err_out_unmap_rx;
496
497 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %s\n",
498 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq,
499 print_mac(mac, dev->dev_addr));
500
501 out:
502 return ret;
503
504 err_out_unmap_rx:
505 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
506 err_out_unmap_tx:
507 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
508 err_out_iounmap:
509 #ifndef USE_IO_OPS
510 iounmap(ioaddr);
511 err_out_free_netdev:
512 #endif
513 free_netdev(dev);
514 err_out_free_res:
515 pci_release_regions(pdev);
516 err_out_disable:
517 pci_disable_device(pdev);
518 goto out;
519 }
520
521 /* Serial EEPROM section. */
522
523 /* EEPROM_Ctrl bits. */
524 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
525 #define EE_CS 0x02 /* EEPROM chip select. */
526 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
527 #define EE_WRITE_0 0x01
528 #define EE_WRITE_1 0x09
529 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
530 #define EE_ENB (0x0001 | EE_CS)
531
532 /* Delay between EEPROM clock transitions.
533 This serves to flush the operation to the PCI bus.
534 */
535
536 #define eeprom_delay() inl(ee_addr)
537
538 /* The EEPROM commands include the alway-set leading bit. */
539 #define EE_WRITE_CMD (5 << 6)
540 #define EE_READ64_CMD (6 << 6)
541 #define EE_READ256_CMD (6 << 8)
542 #define EE_ERASE_CMD (7 << 6)
543
544 static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
545 {
546 long ioaddr = dev->base_addr;
547
548 outl(0x00000000, ioaddr + INTMASK);
549 }
550
551 static inline void __epic_pci_commit(long ioaddr)
552 {
553 #ifndef USE_IO_OPS
554 inl(ioaddr + INTMASK);
555 #endif
556 }
557
558 static inline void epic_napi_irq_off(struct net_device *dev,
559 struct epic_private *ep)
560 {
561 long ioaddr = dev->base_addr;
562
563 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
564 __epic_pci_commit(ioaddr);
565 }
566
567 static inline void epic_napi_irq_on(struct net_device *dev,
568 struct epic_private *ep)
569 {
570 long ioaddr = dev->base_addr;
571
572 /* No need to commit possible posted write */
573 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
574 }
575
576 static int __devinit read_eeprom(long ioaddr, int location)
577 {
578 int i;
579 int retval = 0;
580 long ee_addr = ioaddr + EECTL;
581 int read_cmd = location |
582 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
583
584 outl(EE_ENB & ~EE_CS, ee_addr);
585 outl(EE_ENB, ee_addr);
586
587 /* Shift the read command bits out. */
588 for (i = 12; i >= 0; i--) {
589 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
590 outl(EE_ENB | dataval, ee_addr);
591 eeprom_delay();
592 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
593 eeprom_delay();
594 }
595 outl(EE_ENB, ee_addr);
596
597 for (i = 16; i > 0; i--) {
598 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
599 eeprom_delay();
600 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
601 outl(EE_ENB, ee_addr);
602 eeprom_delay();
603 }
604
605 /* Terminate the EEPROM access. */
606 outl(EE_ENB & ~EE_CS, ee_addr);
607 return retval;
608 }
609
610 #define MII_READOP 1
611 #define MII_WRITEOP 2
612 static int mdio_read(struct net_device *dev, int phy_id, int location)
613 {
614 long ioaddr = dev->base_addr;
615 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
616 int i;
617
618 outl(read_cmd, ioaddr + MIICtrl);
619 /* Typical operation takes 25 loops. */
620 for (i = 400; i > 0; i--) {
621 barrier();
622 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
623 /* Work around read failure bug. */
624 if (phy_id == 1 && location < 6
625 && inw(ioaddr + MIIData) == 0xffff) {
626 outl(read_cmd, ioaddr + MIICtrl);
627 continue;
628 }
629 return inw(ioaddr + MIIData);
630 }
631 }
632 return 0xffff;
633 }
634
635 static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
636 {
637 long ioaddr = dev->base_addr;
638 int i;
639
640 outw(value, ioaddr + MIIData);
641 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
642 for (i = 10000; i > 0; i--) {
643 barrier();
644 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
645 break;
646 }
647 return;
648 }
649
650
651 static int epic_open(struct net_device *dev)
652 {
653 struct epic_private *ep = dev->priv;
654 long ioaddr = dev->base_addr;
655 int i;
656 int retval;
657
658 /* Soft reset the chip. */
659 outl(0x4001, ioaddr + GENCTL);
660
661 napi_enable(&ep->napi);
662 if ((retval = request_irq(dev->irq, &epic_interrupt, IRQF_SHARED, dev->name, dev))) {
663 napi_disable(&ep->napi);
664 return retval;
665 }
666
667 epic_init_ring(dev);
668
669 outl(0x4000, ioaddr + GENCTL);
670 /* This magic is documented in SMSC app note 7.15 */
671 for (i = 16; i > 0; i--)
672 outl(0x0008, ioaddr + TEST1);
673
674 /* Pull the chip out of low-power mode, enable interrupts, and set for
675 PCI read multiple. The MIIcfg setting and strange write order are
676 required by the details of which bits are reset and the transceiver
677 wiring on the Ositech CardBus card.
678 */
679 #if 0
680 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
681 #endif
682 if (ep->chip_flags & MII_PWRDWN)
683 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
684
685 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
686 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
687 inl(ioaddr + GENCTL);
688 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
689 #else
690 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
691 inl(ioaddr + GENCTL);
692 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
693 #endif
694
695 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
696
697 for (i = 0; i < 3; i++)
698 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
699
700 ep->tx_threshold = TX_FIFO_THRESH;
701 outl(ep->tx_threshold, ioaddr + TxThresh);
702
703 if (media2miictl[dev->if_port & 15]) {
704 if (ep->mii_phy_cnt)
705 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
706 if (dev->if_port == 1) {
707 if (debug > 1)
708 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
709 "status %4.4x.\n",
710 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
711 }
712 } else {
713 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
714 if (mii_lpa != 0xffff) {
715 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
716 ep->mii.full_duplex = 1;
717 else if (! (mii_lpa & LPA_LPACK))
718 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
719 if (debug > 1)
720 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
721 " register read of %4.4x.\n", dev->name,
722 ep->mii.full_duplex ? "full" : "half",
723 ep->phys[0], mii_lpa);
724 }
725 }
726
727 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
728 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
729 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
730
731 /* Start the chip's Rx process. */
732 set_rx_mode(dev);
733 outl(StartRx | RxQueued, ioaddr + COMMAND);
734
735 netif_start_queue(dev);
736
737 /* Enable interrupts by setting the interrupt mask. */
738 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
739 | CntFull | TxUnderrun
740 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
741
742 if (debug > 1)
743 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
744 "%s-duplex.\n",
745 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
746 ep->mii.full_duplex ? "full" : "half");
747
748 /* Set the timer to switch to check for link beat and perhaps switch
749 to an alternate media type. */
750 init_timer(&ep->timer);
751 ep->timer.expires = jiffies + 3*HZ;
752 ep->timer.data = (unsigned long)dev;
753 ep->timer.function = &epic_timer; /* timer handler */
754 add_timer(&ep->timer);
755
756 return 0;
757 }
758
759 /* Reset the chip to recover from a PCI transaction error.
760 This may occur at interrupt time. */
761 static void epic_pause(struct net_device *dev)
762 {
763 long ioaddr = dev->base_addr;
764 struct epic_private *ep = dev->priv;
765
766 netif_stop_queue (dev);
767
768 /* Disable interrupts by clearing the interrupt mask. */
769 outl(0x00000000, ioaddr + INTMASK);
770 /* Stop the chip's Tx and Rx DMA processes. */
771 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
772
773 /* Update the error counts. */
774 if (inw(ioaddr + COMMAND) != 0xffff) {
775 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
776 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
777 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
778 }
779
780 /* Remove the packets on the Rx queue. */
781 epic_rx(dev, RX_RING_SIZE);
782 }
783
784 static void epic_restart(struct net_device *dev)
785 {
786 long ioaddr = dev->base_addr;
787 struct epic_private *ep = dev->priv;
788 int i;
789
790 /* Soft reset the chip. */
791 outl(0x4001, ioaddr + GENCTL);
792
793 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
794 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
795 udelay(1);
796
797 /* This magic is documented in SMSC app note 7.15 */
798 for (i = 16; i > 0; i--)
799 outl(0x0008, ioaddr + TEST1);
800
801 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
802 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
803 #else
804 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
805 #endif
806 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
807 if (ep->chip_flags & MII_PWRDWN)
808 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
809
810 for (i = 0; i < 3; i++)
811 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
812
813 ep->tx_threshold = TX_FIFO_THRESH;
814 outl(ep->tx_threshold, ioaddr + TxThresh);
815 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
816 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
817 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
818 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
819 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
820
821 /* Start the chip's Rx process. */
822 set_rx_mode(dev);
823 outl(StartRx | RxQueued, ioaddr + COMMAND);
824
825 /* Enable interrupts by setting the interrupt mask. */
826 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
827 | CntFull | TxUnderrun
828 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
829
830 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
831 " interrupt %4.4x.\n",
832 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
833 (int)inl(ioaddr + INTSTAT));
834 return;
835 }
836
837 static void check_media(struct net_device *dev)
838 {
839 struct epic_private *ep = dev->priv;
840 long ioaddr = dev->base_addr;
841 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
842 int negotiated = mii_lpa & ep->mii.advertising;
843 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
844
845 if (ep->mii.force_media)
846 return;
847 if (mii_lpa == 0xffff) /* Bogus read */
848 return;
849 if (ep->mii.full_duplex != duplex) {
850 ep->mii.full_duplex = duplex;
851 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
852 " partner capability of %4.4x.\n", dev->name,
853 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
854 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
855 }
856 }
857
858 static void epic_timer(unsigned long data)
859 {
860 struct net_device *dev = (struct net_device *)data;
861 struct epic_private *ep = dev->priv;
862 long ioaddr = dev->base_addr;
863 int next_tick = 5*HZ;
864
865 if (debug > 3) {
866 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
867 dev->name, (int)inl(ioaddr + TxSTAT));
868 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
869 "IntStatus %4.4x RxStatus %4.4x.\n",
870 dev->name, (int)inl(ioaddr + INTMASK),
871 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
872 }
873
874 check_media(dev);
875
876 ep->timer.expires = jiffies + next_tick;
877 add_timer(&ep->timer);
878 }
879
880 static void epic_tx_timeout(struct net_device *dev)
881 {
882 struct epic_private *ep = dev->priv;
883 long ioaddr = dev->base_addr;
884
885 if (debug > 0) {
886 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
887 "Tx status %4.4x.\n",
888 dev->name, (int)inw(ioaddr + TxSTAT));
889 if (debug > 1) {
890 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
891 dev->name, ep->dirty_tx, ep->cur_tx);
892 }
893 }
894 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
895 ep->stats.tx_fifo_errors++;
896 outl(RestartTx, ioaddr + COMMAND);
897 } else {
898 epic_restart(dev);
899 outl(TxQueued, dev->base_addr + COMMAND);
900 }
901
902 dev->trans_start = jiffies;
903 ep->stats.tx_errors++;
904 if (!ep->tx_full)
905 netif_wake_queue(dev);
906 }
907
908 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
909 static void epic_init_ring(struct net_device *dev)
910 {
911 struct epic_private *ep = dev->priv;
912 int i;
913
914 ep->tx_full = 0;
915 ep->dirty_tx = ep->cur_tx = 0;
916 ep->cur_rx = ep->dirty_rx = 0;
917 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
918
919 /* Initialize all Rx descriptors. */
920 for (i = 0; i < RX_RING_SIZE; i++) {
921 ep->rx_ring[i].rxstatus = 0;
922 ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
923 ep->rx_ring[i].next = ep->rx_ring_dma +
924 (i+1)*sizeof(struct epic_rx_desc);
925 ep->rx_skbuff[i] = NULL;
926 }
927 /* Mark the last entry as wrapping the ring. */
928 ep->rx_ring[i-1].next = ep->rx_ring_dma;
929
930 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
931 for (i = 0; i < RX_RING_SIZE; i++) {
932 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
933 ep->rx_skbuff[i] = skb;
934 if (skb == NULL)
935 break;
936 skb_reserve(skb, 2); /* 16 byte align the IP header. */
937 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
938 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
939 ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
940 }
941 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
942
943 /* The Tx buffer descriptor is filled in as needed, but we
944 do need to clear the ownership bit. */
945 for (i = 0; i < TX_RING_SIZE; i++) {
946 ep->tx_skbuff[i] = NULL;
947 ep->tx_ring[i].txstatus = 0x0000;
948 ep->tx_ring[i].next = ep->tx_ring_dma +
949 (i+1)*sizeof(struct epic_tx_desc);
950 }
951 ep->tx_ring[i-1].next = ep->tx_ring_dma;
952 return;
953 }
954
955 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
956 {
957 struct epic_private *ep = dev->priv;
958 int entry, free_count;
959 u32 ctrl_word;
960 unsigned long flags;
961
962 if (skb_padto(skb, ETH_ZLEN))
963 return 0;
964
965 /* Caution: the write order is important here, set the field with the
966 "ownership" bit last. */
967
968 /* Calculate the next Tx descriptor entry. */
969 spin_lock_irqsave(&ep->lock, flags);
970 free_count = ep->cur_tx - ep->dirty_tx;
971 entry = ep->cur_tx % TX_RING_SIZE;
972
973 ep->tx_skbuff[entry] = skb;
974 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
975 skb->len, PCI_DMA_TODEVICE);
976 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
977 ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
978 } else if (free_count == TX_QUEUE_LEN/2) {
979 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
980 } else if (free_count < TX_QUEUE_LEN - 1) {
981 ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
982 } else {
983 /* Leave room for an additional entry. */
984 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
985 ep->tx_full = 1;
986 }
987 ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
988 ep->tx_ring[entry].txstatus =
989 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
990 | cpu_to_le32(DescOwn);
991
992 ep->cur_tx++;
993 if (ep->tx_full)
994 netif_stop_queue(dev);
995
996 spin_unlock_irqrestore(&ep->lock, flags);
997 /* Trigger an immediate transmit demand. */
998 outl(TxQueued, dev->base_addr + COMMAND);
999
1000 dev->trans_start = jiffies;
1001 if (debug > 4)
1002 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1003 "flag %2.2x Tx status %8.8x.\n",
1004 dev->name, (int)skb->len, entry, ctrl_word,
1005 (int)inl(dev->base_addr + TxSTAT));
1006
1007 return 0;
1008 }
1009
1010 static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1011 int status)
1012 {
1013 struct net_device_stats *stats = &ep->stats;
1014
1015 #ifndef final_version
1016 /* There was an major error, log it. */
1017 if (debug > 1)
1018 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1019 dev->name, status);
1020 #endif
1021 stats->tx_errors++;
1022 if (status & 0x1050)
1023 stats->tx_aborted_errors++;
1024 if (status & 0x0008)
1025 stats->tx_carrier_errors++;
1026 if (status & 0x0040)
1027 stats->tx_window_errors++;
1028 if (status & 0x0010)
1029 stats->tx_fifo_errors++;
1030 }
1031
1032 static void epic_tx(struct net_device *dev, struct epic_private *ep)
1033 {
1034 unsigned int dirty_tx, cur_tx;
1035
1036 /*
1037 * Note: if this lock becomes a problem we can narrow the locked
1038 * region at the cost of occasionally grabbing the lock more times.
1039 */
1040 cur_tx = ep->cur_tx;
1041 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1042 struct sk_buff *skb;
1043 int entry = dirty_tx % TX_RING_SIZE;
1044 int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
1045
1046 if (txstatus & DescOwn)
1047 break; /* It still hasn't been Txed */
1048
1049 if (likely(txstatus & 0x0001)) {
1050 ep->stats.collisions += (txstatus >> 8) & 15;
1051 ep->stats.tx_packets++;
1052 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1053 } else
1054 epic_tx_error(dev, ep, txstatus);
1055
1056 /* Free the original skb. */
1057 skb = ep->tx_skbuff[entry];
1058 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1059 skb->len, PCI_DMA_TODEVICE);
1060 dev_kfree_skb_irq(skb);
1061 ep->tx_skbuff[entry] = NULL;
1062 }
1063
1064 #ifndef final_version
1065 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1066 printk(KERN_WARNING
1067 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1068 dev->name, dirty_tx, cur_tx, ep->tx_full);
1069 dirty_tx += TX_RING_SIZE;
1070 }
1071 #endif
1072 ep->dirty_tx = dirty_tx;
1073 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1074 /* The ring is no longer full, allow new TX entries. */
1075 ep->tx_full = 0;
1076 netif_wake_queue(dev);
1077 }
1078 }
1079
1080 /* The interrupt handler does all of the Rx thread work and cleans up
1081 after the Tx thread. */
1082 static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1083 {
1084 struct net_device *dev = dev_instance;
1085 struct epic_private *ep = dev->priv;
1086 long ioaddr = dev->base_addr;
1087 unsigned int handled = 0;
1088 int status;
1089
1090 status = inl(ioaddr + INTSTAT);
1091 /* Acknowledge all of the current interrupt sources ASAP. */
1092 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1093
1094 if (debug > 4) {
1095 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1096 "intstat=%#8.8x.\n", dev->name, status,
1097 (int)inl(ioaddr + INTSTAT));
1098 }
1099
1100 if ((status & IntrSummary) == 0)
1101 goto out;
1102
1103 handled = 1;
1104
1105 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1106 spin_lock(&ep->napi_lock);
1107 if (netif_rx_schedule_prep(dev, &ep->napi)) {
1108 epic_napi_irq_off(dev, ep);
1109 __netif_rx_schedule(dev, &ep->napi);
1110 } else
1111 ep->reschedule_in_poll++;
1112 spin_unlock(&ep->napi_lock);
1113 }
1114 status &= ~EpicNapiEvent;
1115
1116 /* Check uncommon events all at once. */
1117 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1118 if (status == EpicRemoved)
1119 goto out;
1120
1121 /* Always update the error counts to avoid overhead later. */
1122 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1123 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1124 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1125
1126 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1127 ep->stats.tx_fifo_errors++;
1128 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1129 /* Restart the transmit process. */
1130 outl(RestartTx, ioaddr + COMMAND);
1131 }
1132 if (status & PCIBusErr170) {
1133 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1134 dev->name, status);
1135 epic_pause(dev);
1136 epic_restart(dev);
1137 }
1138 /* Clear all error sources. */
1139 outl(status & 0x7f18, ioaddr + INTSTAT);
1140 }
1141
1142 out:
1143 if (debug > 3) {
1144 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1145 dev->name, status);
1146 }
1147
1148 return IRQ_RETVAL(handled);
1149 }
1150
1151 static int epic_rx(struct net_device *dev, int budget)
1152 {
1153 struct epic_private *ep = dev->priv;
1154 int entry = ep->cur_rx % RX_RING_SIZE;
1155 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1156 int work_done = 0;
1157
1158 if (debug > 4)
1159 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1160 ep->rx_ring[entry].rxstatus);
1161
1162 if (rx_work_limit > budget)
1163 rx_work_limit = budget;
1164
1165 /* If we own the next entry, it's a new packet. Send it up. */
1166 while ((ep->rx_ring[entry].rxstatus & cpu_to_le32(DescOwn)) == 0) {
1167 int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
1168
1169 if (debug > 4)
1170 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1171 if (--rx_work_limit < 0)
1172 break;
1173 if (status & 0x2006) {
1174 if (debug > 2)
1175 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1176 dev->name, status);
1177 if (status & 0x2000) {
1178 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1179 "multiple buffers, status %4.4x!\n", dev->name, status);
1180 ep->stats.rx_length_errors++;
1181 } else if (status & 0x0006)
1182 /* Rx Frame errors are counted in hardware. */
1183 ep->stats.rx_errors++;
1184 } else {
1185 /* Malloc up new buffer, compatible with net-2e. */
1186 /* Omit the four octet CRC from the length. */
1187 short pkt_len = (status >> 16) - 4;
1188 struct sk_buff *skb;
1189
1190 if (pkt_len > PKT_BUF_SZ - 4) {
1191 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1192 "%d bytes.\n",
1193 dev->name, status, pkt_len);
1194 pkt_len = 1514;
1195 }
1196 /* Check if the packet is long enough to accept without copying
1197 to a minimally-sized skbuff. */
1198 if (pkt_len < rx_copybreak
1199 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1200 skb_reserve(skb, 2); /* 16 byte align the IP header */
1201 pci_dma_sync_single_for_cpu(ep->pci_dev,
1202 ep->rx_ring[entry].bufaddr,
1203 ep->rx_buf_sz,
1204 PCI_DMA_FROMDEVICE);
1205 skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len);
1206 skb_put(skb, pkt_len);
1207 pci_dma_sync_single_for_device(ep->pci_dev,
1208 ep->rx_ring[entry].bufaddr,
1209 ep->rx_buf_sz,
1210 PCI_DMA_FROMDEVICE);
1211 } else {
1212 pci_unmap_single(ep->pci_dev,
1213 ep->rx_ring[entry].bufaddr,
1214 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1215 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1216 ep->rx_skbuff[entry] = NULL;
1217 }
1218 skb->protocol = eth_type_trans(skb, dev);
1219 netif_receive_skb(skb);
1220 dev->last_rx = jiffies;
1221 ep->stats.rx_packets++;
1222 ep->stats.rx_bytes += pkt_len;
1223 }
1224 work_done++;
1225 entry = (++ep->cur_rx) % RX_RING_SIZE;
1226 }
1227
1228 /* Refill the Rx ring buffers. */
1229 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1230 entry = ep->dirty_rx % RX_RING_SIZE;
1231 if (ep->rx_skbuff[entry] == NULL) {
1232 struct sk_buff *skb;
1233 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1234 if (skb == NULL)
1235 break;
1236 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1237 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1238 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1239 work_done++;
1240 }
1241 ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
1242 }
1243 return work_done;
1244 }
1245
1246 static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1247 {
1248 long ioaddr = dev->base_addr;
1249 int status;
1250
1251 status = inl(ioaddr + INTSTAT);
1252
1253 if (status == EpicRemoved)
1254 return;
1255 if (status & RxOverflow) /* Missed a Rx frame. */
1256 ep->stats.rx_errors++;
1257 if (status & (RxOverflow | RxFull))
1258 outw(RxQueued, ioaddr + COMMAND);
1259 }
1260
1261 static int epic_poll(struct napi_struct *napi, int budget)
1262 {
1263 struct epic_private *ep = container_of(napi, struct epic_private, napi);
1264 struct net_device *dev = ep->mii.dev;
1265 int work_done = 0;
1266 long ioaddr = dev->base_addr;
1267
1268 rx_action:
1269
1270 epic_tx(dev, ep);
1271
1272 work_done += epic_rx(dev, budget);
1273
1274 epic_rx_err(dev, ep);
1275
1276 if (netif_running(dev) && (work_done < budget)) {
1277 unsigned long flags;
1278 int more;
1279
1280 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1281
1282 spin_lock_irqsave(&ep->napi_lock, flags);
1283
1284 more = ep->reschedule_in_poll;
1285 if (!more) {
1286 __netif_rx_complete(dev, napi);
1287 outl(EpicNapiEvent, ioaddr + INTSTAT);
1288 epic_napi_irq_on(dev, ep);
1289 } else
1290 ep->reschedule_in_poll--;
1291
1292 spin_unlock_irqrestore(&ep->napi_lock, flags);
1293
1294 if (more)
1295 goto rx_action;
1296 }
1297
1298 return work_done;
1299 }
1300
1301 static int epic_close(struct net_device *dev)
1302 {
1303 long ioaddr = dev->base_addr;
1304 struct epic_private *ep = dev->priv;
1305 struct sk_buff *skb;
1306 int i;
1307
1308 netif_stop_queue(dev);
1309 napi_disable(&ep->napi);
1310
1311 if (debug > 1)
1312 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1313 dev->name, (int)inl(ioaddr + INTSTAT));
1314
1315 del_timer_sync(&ep->timer);
1316
1317 epic_disable_int(dev, ep);
1318
1319 free_irq(dev->irq, dev);
1320
1321 epic_pause(dev);
1322
1323 /* Free all the skbuffs in the Rx queue. */
1324 for (i = 0; i < RX_RING_SIZE; i++) {
1325 skb = ep->rx_skbuff[i];
1326 ep->rx_skbuff[i] = NULL;
1327 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1328 ep->rx_ring[i].buflength = 0;
1329 if (skb) {
1330 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1331 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1332 dev_kfree_skb(skb);
1333 }
1334 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1335 }
1336 for (i = 0; i < TX_RING_SIZE; i++) {
1337 skb = ep->tx_skbuff[i];
1338 ep->tx_skbuff[i] = NULL;
1339 if (!skb)
1340 continue;
1341 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1342 skb->len, PCI_DMA_TODEVICE);
1343 dev_kfree_skb(skb);
1344 }
1345
1346 /* Green! Leave the chip in low-power mode. */
1347 outl(0x0008, ioaddr + GENCTL);
1348
1349 return 0;
1350 }
1351
1352 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1353 {
1354 struct epic_private *ep = dev->priv;
1355 long ioaddr = dev->base_addr;
1356
1357 if (netif_running(dev)) {
1358 /* Update the error counts. */
1359 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1360 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1361 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1362 }
1363
1364 return &ep->stats;
1365 }
1366
1367 /* Set or clear the multicast filter for this adaptor.
1368 Note that we only use exclusion around actually queueing the
1369 new frame, not around filling ep->setup_frame. This is non-deterministic
1370 when re-entered but still correct. */
1371
1372 static void set_rx_mode(struct net_device *dev)
1373 {
1374 long ioaddr = dev->base_addr;
1375 struct epic_private *ep = dev->priv;
1376 unsigned char mc_filter[8]; /* Multicast hash filter */
1377 int i;
1378
1379 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1380 outl(0x002C, ioaddr + RxCtrl);
1381 /* Unconditionally log net taps. */
1382 memset(mc_filter, 0xff, sizeof(mc_filter));
1383 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1384 /* There is apparently a chip bug, so the multicast filter
1385 is never enabled. */
1386 /* Too many to filter perfectly -- accept all multicasts. */
1387 memset(mc_filter, 0xff, sizeof(mc_filter));
1388 outl(0x000C, ioaddr + RxCtrl);
1389 } else if (dev->mc_count == 0) {
1390 outl(0x0004, ioaddr + RxCtrl);
1391 return;
1392 } else { /* Never executed, for now. */
1393 struct dev_mc_list *mclist;
1394
1395 memset(mc_filter, 0, sizeof(mc_filter));
1396 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1397 i++, mclist = mclist->next) {
1398 unsigned int bit_nr =
1399 ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f;
1400 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1401 }
1402 }
1403 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1404 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1405 for (i = 0; i < 4; i++)
1406 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1407 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1408 }
1409 return;
1410 }
1411
1412 static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1413 {
1414 struct epic_private *np = dev->priv;
1415
1416 strcpy (info->driver, DRV_NAME);
1417 strcpy (info->version, DRV_VERSION);
1418 strcpy (info->bus_info, pci_name(np->pci_dev));
1419 }
1420
1421 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1422 {
1423 struct epic_private *np = dev->priv;
1424 int rc;
1425
1426 spin_lock_irq(&np->lock);
1427 rc = mii_ethtool_gset(&np->mii, cmd);
1428 spin_unlock_irq(&np->lock);
1429
1430 return rc;
1431 }
1432
1433 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1434 {
1435 struct epic_private *np = dev->priv;
1436 int rc;
1437
1438 spin_lock_irq(&np->lock);
1439 rc = mii_ethtool_sset(&np->mii, cmd);
1440 spin_unlock_irq(&np->lock);
1441
1442 return rc;
1443 }
1444
1445 static int netdev_nway_reset(struct net_device *dev)
1446 {
1447 struct epic_private *np = dev->priv;
1448 return mii_nway_restart(&np->mii);
1449 }
1450
1451 static u32 netdev_get_link(struct net_device *dev)
1452 {
1453 struct epic_private *np = dev->priv;
1454 return mii_link_ok(&np->mii);
1455 }
1456
1457 static u32 netdev_get_msglevel(struct net_device *dev)
1458 {
1459 return debug;
1460 }
1461
1462 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1463 {
1464 debug = value;
1465 }
1466
1467 static int ethtool_begin(struct net_device *dev)
1468 {
1469 unsigned long ioaddr = dev->base_addr;
1470 /* power-up, if interface is down */
1471 if (! netif_running(dev)) {
1472 outl(0x0200, ioaddr + GENCTL);
1473 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1474 }
1475 return 0;
1476 }
1477
1478 static void ethtool_complete(struct net_device *dev)
1479 {
1480 unsigned long ioaddr = dev->base_addr;
1481 /* power-down, if interface is down */
1482 if (! netif_running(dev)) {
1483 outl(0x0008, ioaddr + GENCTL);
1484 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1485 }
1486 }
1487
1488 static const struct ethtool_ops netdev_ethtool_ops = {
1489 .get_drvinfo = netdev_get_drvinfo,
1490 .get_settings = netdev_get_settings,
1491 .set_settings = netdev_set_settings,
1492 .nway_reset = netdev_nway_reset,
1493 .get_link = netdev_get_link,
1494 .get_msglevel = netdev_get_msglevel,
1495 .set_msglevel = netdev_set_msglevel,
1496 .begin = ethtool_begin,
1497 .complete = ethtool_complete
1498 };
1499
1500 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1501 {
1502 struct epic_private *np = dev->priv;
1503 long ioaddr = dev->base_addr;
1504 struct mii_ioctl_data *data = if_mii(rq);
1505 int rc;
1506
1507 /* power-up, if interface is down */
1508 if (! netif_running(dev)) {
1509 outl(0x0200, ioaddr + GENCTL);
1510 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1511 }
1512
1513 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1514 spin_lock_irq(&np->lock);
1515 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1516 spin_unlock_irq(&np->lock);
1517
1518 /* power-down, if interface is down */
1519 if (! netif_running(dev)) {
1520 outl(0x0008, ioaddr + GENCTL);
1521 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1522 }
1523 return rc;
1524 }
1525
1526
1527 static void __devexit epic_remove_one (struct pci_dev *pdev)
1528 {
1529 struct net_device *dev = pci_get_drvdata(pdev);
1530 struct epic_private *ep = dev->priv;
1531
1532 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1533 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1534 unregister_netdev(dev);
1535 #ifndef USE_IO_OPS
1536 iounmap((void*) dev->base_addr);
1537 #endif
1538 pci_release_regions(pdev);
1539 free_netdev(dev);
1540 pci_disable_device(pdev);
1541 pci_set_drvdata(pdev, NULL);
1542 /* pci_power_off(pdev, -1); */
1543 }
1544
1545
1546 #ifdef CONFIG_PM
1547
1548 static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1549 {
1550 struct net_device *dev = pci_get_drvdata(pdev);
1551 long ioaddr = dev->base_addr;
1552
1553 if (!netif_running(dev))
1554 return 0;
1555 epic_pause(dev);
1556 /* Put the chip into low-power mode. */
1557 outl(0x0008, ioaddr + GENCTL);
1558 /* pci_power_off(pdev, -1); */
1559 return 0;
1560 }
1561
1562
1563 static int epic_resume (struct pci_dev *pdev)
1564 {
1565 struct net_device *dev = pci_get_drvdata(pdev);
1566
1567 if (!netif_running(dev))
1568 return 0;
1569 epic_restart(dev);
1570 /* pci_power_on(pdev); */
1571 return 0;
1572 }
1573
1574 #endif /* CONFIG_PM */
1575
1576
1577 static struct pci_driver epic_driver = {
1578 .name = DRV_NAME,
1579 .id_table = epic_pci_tbl,
1580 .probe = epic_init_one,
1581 .remove = __devexit_p(epic_remove_one),
1582 #ifdef CONFIG_PM
1583 .suspend = epic_suspend,
1584 .resume = epic_resume,
1585 #endif /* CONFIG_PM */
1586 };
1587
1588
1589 static int __init epic_init (void)
1590 {
1591 /* when a module, this is printed whether or not devices are found in probe */
1592 #ifdef MODULE
1593 printk (KERN_INFO "%s" KERN_INFO "%s",
1594 version, version2);
1595 #endif
1596
1597 return pci_register_driver(&epic_driver);
1598 }
1599
1600
1601 static void __exit epic_cleanup (void)
1602 {
1603 pci_unregister_driver (&epic_driver);
1604 }
1605
1606
1607 module_init(epic_init);
1608 module_exit(epic_cleanup);
Mirror for ia64_pv_ops.git