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fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / drivers / net / sky2.c
blob7967240534d5b647d97313920c9d5ff7b2455bc0
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/aer.h>
35 #include <linux/ip.h>
36 #include <net/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/debugfs.h>
44 #include <linux/mii.h>
45
46 #include <asm/irq.h>
47
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define SKY2_VLAN_TAG_USED 1
50 #endif
51
52 #include "sky2.h"
53
54 #define DRV_NAME "sky2"
55 #define DRV_VERSION "1.19"
56 #define PFX DRV_NAME " "
57
58 /*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
61 * similar to Tigon3.
62 */
63
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
80
81 #define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
84 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95 static int copybreak __read_mostly = 128;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 { 0 }
138 };
139
140 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
145 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
154 "FE+", /* 0xb8 */
155 };
156
157 static void sky2_set_multicast(struct net_device *dev);
158
159 /* Access to external PHY */
160 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 {
162 int i;
163
164 gma_write16(hw, port, GM_SMI_DATA, val);
165 gma_write16(hw, port, GM_SMI_CTRL,
166 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167
168 for (i = 0; i < PHY_RETRIES; i++) {
169 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
170 return 0;
171 udelay(1);
172 }
173
174 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
175 return -ETIMEDOUT;
176 }
177
178 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
179 {
180 int i;
181
182 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
183 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184
185 for (i = 0; i < PHY_RETRIES; i++) {
186 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
187 *val = gma_read16(hw, port, GM_SMI_DATA);
188 return 0;
189 }
190
191 udelay(1);
192 }
193
194 return -ETIMEDOUT;
195 }
196
197 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
198 {
199 u16 v;
200
201 if (__gm_phy_read(hw, port, reg, &v) != 0)
202 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
203 return v;
204 }
205
206
207 static void sky2_power_on(struct sky2_hw *hw)
208 {
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
226 struct pci_dev *pdev = hw->pdev;
227 u32 reg;
228
229 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
230
231 pci_read_config_dword(pdev, PCI_DEV_REG4, &reg);
232 /* set all bits to 0 except bits 15..12 and 8 */
233 reg &= P_ASPM_CONTROL_MSK;
234 pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
235
236 pci_read_config_dword(pdev, PCI_DEV_REG5, &reg);
237 /* set all bits to 0 except bits 28 & 27 */
238 reg &= P_CTL_TIM_VMAIN_AV_MSK;
239 pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
240
241 pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
242
243 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
244 reg = sky2_read32(hw, B2_GP_IO);
245 reg |= GLB_GPIO_STAT_RACE_DIS;
246 sky2_write32(hw, B2_GP_IO, reg);
247
248 sky2_read32(hw, B2_GP_IO);
249 }
250 }
251
252 static void sky2_power_aux(struct sky2_hw *hw)
253 {
254 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
256 else
257 /* enable bits are inverted */
258 sky2_write8(hw, B2_Y2_CLK_GATE,
259 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
260 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
261 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
262
263 /* switch power to VAUX */
264 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
265 sky2_write8(hw, B0_POWER_CTRL,
266 (PC_VAUX_ENA | PC_VCC_ENA |
267 PC_VAUX_ON | PC_VCC_OFF));
268 }
269
270 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
271 {
272 u16 reg;
273
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
278
279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
287 }
288
289 /* flow control to advertise bits */
290 static const u16 copper_fc_adv[] = {
291 [FC_NONE] = 0,
292 [FC_TX] = PHY_M_AN_ASP,
293 [FC_RX] = PHY_M_AN_PC,
294 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
295 };
296
297 /* flow control to advertise bits when using 1000BaseX */
298 static const u16 fiber_fc_adv[] = {
299 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300 [FC_TX] = PHY_M_P_ASYM_MD_X,
301 [FC_RX] = PHY_M_P_SYM_MD_X,
302 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
303 };
304
305 /* flow control to GMA disable bits */
306 static const u16 gm_fc_disable[] = {
307 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
308 [FC_TX] = GM_GPCR_FC_RX_DIS,
309 [FC_RX] = GM_GPCR_FC_TX_DIS,
310 [FC_BOTH] = 0,
311 };
312
313
314 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
315 {
316 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
317 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
318
319 if (sky2->autoneg == AUTONEG_ENABLE &&
320 !(hw->flags & SKY2_HW_NEWER_PHY)) {
321 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
322
323 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
324 PHY_M_EC_MAC_S_MSK);
325 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
326
327 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
328 if (hw->chip_id == CHIP_ID_YUKON_EC)
329 /* set downshift counter to 3x and enable downshift */
330 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
331 else
332 /* set master & slave downshift counter to 1x */
333 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
334
335 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
336 }
337
338 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
339 if (sky2_is_copper(hw)) {
340 if (!(hw->flags & SKY2_HW_GIGABIT)) {
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
343
344 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
345 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
346 u16 spec;
347
348 /* Enable Class A driver for FE+ A0 */
349 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
350 spec |= PHY_M_FESC_SEL_CL_A;
351 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
352 }
353 } else {
354 /* disable energy detect */
355 ctrl &= ~PHY_M_PC_EN_DET_MSK;
356
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
359
360 /* downshift on PHY 88E1112 and 88E1149 is changed */
361 if (sky2->autoneg == AUTONEG_ENABLE
362 && (hw->flags & SKY2_HW_NEWER_PHY)) {
363 /* set downshift counter to 3x and enable downshift */
364 ctrl &= ~PHY_M_PC_DSC_MSK;
365 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
366 }
367 }
368 } else {
369 /* workaround for deviation #4.88 (CRC errors) */
370 /* disable Automatic Crossover */
371
372 ctrl &= ~PHY_M_PC_MDIX_MSK;
373 }
374
375 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
376
377 /* special setup for PHY 88E1112 Fiber */
378 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
379 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
380
381 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
383 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
384 ctrl &= ~PHY_M_MAC_MD_MSK;
385 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
386 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
387
388 if (hw->pmd_type == 'P') {
389 /* select page 1 to access Fiber registers */
390 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
391
392 /* for SFP-module set SIGDET polarity to low */
393 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
394 ctrl |= PHY_M_FIB_SIGD_POL;
395 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
396 }
397
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
399 }
400
401 ctrl = PHY_CT_RESET;
402 ct1000 = 0;
403 adv = PHY_AN_CSMA;
404 reg = 0;
405
406 if (sky2->autoneg == AUTONEG_ENABLE) {
407 if (sky2_is_copper(hw)) {
408 if (sky2->advertising & ADVERTISED_1000baseT_Full)
409 ct1000 |= PHY_M_1000C_AFD;
410 if (sky2->advertising & ADVERTISED_1000baseT_Half)
411 ct1000 |= PHY_M_1000C_AHD;
412 if (sky2->advertising & ADVERTISED_100baseT_Full)
413 adv |= PHY_M_AN_100_FD;
414 if (sky2->advertising & ADVERTISED_100baseT_Half)
415 adv |= PHY_M_AN_100_HD;
416 if (sky2->advertising & ADVERTISED_10baseT_Full)
417 adv |= PHY_M_AN_10_FD;
418 if (sky2->advertising & ADVERTISED_10baseT_Half)
419 adv |= PHY_M_AN_10_HD;
420
421 adv |= copper_fc_adv[sky2->flow_mode];
422 } else { /* special defines for FIBER (88E1040S only) */
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 adv |= PHY_M_AN_1000X_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 adv |= PHY_M_AN_1000X_AHD;
427
428 adv |= fiber_fc_adv[sky2->flow_mode];
429 }
430
431 /* Restart Auto-negotiation */
432 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
433 } else {
434 /* forced speed/duplex settings */
435 ct1000 = PHY_M_1000C_MSE;
436
437 /* Disable auto update for duplex flow control and speed */
438 reg |= GM_GPCR_AU_ALL_DIS;
439
440 switch (sky2->speed) {
441 case SPEED_1000:
442 ctrl |= PHY_CT_SP1000;
443 reg |= GM_GPCR_SPEED_1000;
444 break;
445 case SPEED_100:
446 ctrl |= PHY_CT_SP100;
447 reg |= GM_GPCR_SPEED_100;
448 break;
449 }
450
451 if (sky2->duplex == DUPLEX_FULL) {
452 reg |= GM_GPCR_DUP_FULL;
453 ctrl |= PHY_CT_DUP_MD;
454 } else if (sky2->speed < SPEED_1000)
455 sky2->flow_mode = FC_NONE;
456
457
458 reg |= gm_fc_disable[sky2->flow_mode];
459
460 /* Forward pause packets to GMAC? */
461 if (sky2->flow_mode & FC_RX)
462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
463 else
464 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
465 }
466
467 gma_write16(hw, port, GM_GP_CTRL, reg);
468
469 if (hw->flags & SKY2_HW_GIGABIT)
470 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
471
472 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
473 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
474
475 /* Setup Phy LED's */
476 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
477 ledover = 0;
478
479 switch (hw->chip_id) {
480 case CHIP_ID_YUKON_FE:
481 /* on 88E3082 these bits are at 11..9 (shifted left) */
482 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
483
484 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
485
486 /* delete ACT LED control bits */
487 ctrl &= ~PHY_M_FELP_LED1_MSK;
488 /* change ACT LED control to blink mode */
489 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
490 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
491 break;
492
493 case CHIP_ID_YUKON_FE_P:
494 /* Enable Link Partner Next Page */
495 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
496 ctrl |= PHY_M_PC_ENA_LIP_NP;
497
498 /* disable Energy Detect and enable scrambler */
499 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
500 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
501
502 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
503 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
504 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
505 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
506
507 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 break;
509
510 case CHIP_ID_YUKON_XL:
511 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
512
513 /* select page 3 to access LED control register */
514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
515
516 /* set LED Function Control register */
517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
518 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
519 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
520 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
521 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
522
523 /* set Polarity Control register */
524 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
525 (PHY_M_POLC_LS1_P_MIX(4) |
526 PHY_M_POLC_IS0_P_MIX(4) |
527 PHY_M_POLC_LOS_CTRL(2) |
528 PHY_M_POLC_INIT_CTRL(2) |
529 PHY_M_POLC_STA1_CTRL(2) |
530 PHY_M_POLC_STA0_CTRL(2)));
531
532 /* restore page register */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
534 break;
535
536 case CHIP_ID_YUKON_EC_U:
537 case CHIP_ID_YUKON_EX:
538 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
539
540 /* select page 3 to access LED control register */
541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
542
543 /* set LED Function Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
545 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
546 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
547 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
548 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
549
550 /* set Blink Rate in LED Timer Control Register */
551 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
552 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
553 /* restore page register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
555 break;
556
557 default:
558 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
559 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
560 /* turn off the Rx LED (LED_RX) */
561 ledover &= ~PHY_M_LED_MO_RX;
562 }
563
564 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
565 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
566 /* apply fixes in PHY AFE */
567 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
568
569 /* increase differential signal amplitude in 10BASE-T */
570 gm_phy_write(hw, port, 0x18, 0xaa99);
571 gm_phy_write(hw, port, 0x17, 0x2011);
572
573 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
574 gm_phy_write(hw, port, 0x18, 0xa204);
575 gm_phy_write(hw, port, 0x17, 0x2002);
576
577 /* set page register to 0 */
578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
579 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
580 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
581 /* apply workaround for integrated resistors calibration */
582 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
583 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
584 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
585 /* no effect on Yukon-XL */
586 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
587
588 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
589 /* turn on 100 Mbps LED (LED_LINK100) */
590 ledover |= PHY_M_LED_MO_100;
591 }
592
593 if (ledover)
594 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
595
596 }
597
598 /* Enable phy interrupt on auto-negotiation complete (or link up) */
599 if (sky2->autoneg == AUTONEG_ENABLE)
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
601 else
602 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
603 }
604
605 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
606 {
607 struct pci_dev *pdev = hw->pdev;
608 u32 reg1;
609 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
610 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
611
612 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
613 /* Turn on/off phy power saving */
614 if (onoff)
615 reg1 &= ~phy_power[port];
616 else
617 reg1 |= phy_power[port];
618
619 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
620 reg1 |= coma_mode[port];
621
622 pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
623 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
624
625 udelay(100);
626 }
627
628 /* Force a renegotiation */
629 static void sky2_phy_reinit(struct sky2_port *sky2)
630 {
631 spin_lock_bh(&sky2->phy_lock);
632 sky2_phy_init(sky2->hw, sky2->port);
633 spin_unlock_bh(&sky2->phy_lock);
634 }
635
636 /* Put device in state to listen for Wake On Lan */
637 static void sky2_wol_init(struct sky2_port *sky2)
638 {
639 struct sky2_hw *hw = sky2->hw;
640 unsigned port = sky2->port;
641 enum flow_control save_mode;
642 u16 ctrl;
643 u32 reg1;
644
645 /* Bring hardware out of reset */
646 sky2_write16(hw, B0_CTST, CS_RST_CLR);
647 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
648
649 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
650 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
651
652 /* Force to 10/100
653 * sky2_reset will re-enable on resume
654 */
655 save_mode = sky2->flow_mode;
656 ctrl = sky2->advertising;
657
658 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
659 sky2->flow_mode = FC_NONE;
660 sky2_phy_power(hw, port, 1);
661 sky2_phy_reinit(sky2);
662
663 sky2->flow_mode = save_mode;
664 sky2->advertising = ctrl;
665
666 /* Set GMAC to no flow control and auto update for speed/duplex */
667 gma_write16(hw, port, GM_GP_CTRL,
668 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
669 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
670
671 /* Set WOL address */
672 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
673 sky2->netdev->dev_addr, ETH_ALEN);
674
675 /* Turn on appropriate WOL control bits */
676 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
677 ctrl = 0;
678 if (sky2->wol & WAKE_PHY)
679 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
680 else
681 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
682
683 if (sky2->wol & WAKE_MAGIC)
684 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
685 else
686 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
687
688 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
689 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
690
691 /* Turn on legacy PCI-Express PME mode */
692 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
693 reg1 |= PCI_Y2_PME_LEGACY;
694 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
695
696 /* block receiver */
697 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
698
699 }
700
701 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
702 {
703 struct net_device *dev = hw->dev[port];
704
705 if (dev->mtu <= ETH_DATA_LEN)
706 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
707 TX_JUMBO_DIS | TX_STFW_ENA);
708
709 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
710 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
711 TX_STFW_ENA | TX_JUMBO_ENA);
712 else {
713 /* set Tx GMAC FIFO Almost Empty Threshold */
714 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
715 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
716
717 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
718 TX_JUMBO_ENA | TX_STFW_DIS);
719
720 /* Can't do offload because of lack of store/forward */
721 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
722 }
723 }
724
725 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
726 {
727 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
728 u16 reg;
729 u32 rx_reg;
730 int i;
731 const u8 *addr = hw->dev[port]->dev_addr;
732
733 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
735
736 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
737
738 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
739 /* WA DEV_472 -- looks like crossed wires on port 2 */
740 /* clear GMAC 1 Control reset */
741 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
742 do {
743 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
744 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
745 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
746 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
747 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
748 }
749
750 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
751
752 /* Enable Transmit FIFO Underrun */
753 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
754
755 spin_lock_bh(&sky2->phy_lock);
756 sky2_phy_init(hw, port);
757 spin_unlock_bh(&sky2->phy_lock);
758
759 /* MIB clear */
760 reg = gma_read16(hw, port, GM_PHY_ADDR);
761 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
762
763 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
764 gma_read16(hw, port, i);
765 gma_write16(hw, port, GM_PHY_ADDR, reg);
766
767 /* transmit control */
768 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
769
770 /* receive control reg: unicast + multicast + no FCS */
771 gma_write16(hw, port, GM_RX_CTRL,
772 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
773
774 /* transmit flow control */
775 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
776
777 /* transmit parameter */
778 gma_write16(hw, port, GM_TX_PARAM,
779 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
780 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
781 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
782 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
783
784 /* serial mode register */
785 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
786 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
787
788 if (hw->dev[port]->mtu > ETH_DATA_LEN)
789 reg |= GM_SMOD_JUMBO_ENA;
790
791 gma_write16(hw, port, GM_SERIAL_MODE, reg);
792
793 /* virtual address for data */
794 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
795
796 /* physical address: used for pause frames */
797 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
798
799 /* ignore counter overflows */
800 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
801 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
802 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
803
804 /* Configure Rx MAC FIFO */
805 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
806 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
807 if (hw->chip_id == CHIP_ID_YUKON_EX ||
808 hw->chip_id == CHIP_ID_YUKON_FE_P)
809 rx_reg |= GMF_RX_OVER_ON;
810
811 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
812
813 /* Flush Rx MAC FIFO on any flow control or error */
814 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
815
816 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
817 reg = RX_GMF_FL_THR_DEF + 1;
818 /* Another magic mystery workaround from sk98lin */
819 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
820 hw->chip_rev == CHIP_REV_YU_FE2_A0)
821 reg = 0x178;
822 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
823
824 /* Configure Tx MAC FIFO */
825 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
826 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
827
828 /* On chips without ram buffer, pause is controled by MAC level */
829 if (sky2_read8(hw, B2_E_0) == 0) {
830 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
831 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
832
833 sky2_set_tx_stfwd(hw, port);
834 }
835
836 }
837
838 /* Assign Ram Buffer allocation to queue */
839 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
840 {
841 u32 end;
842
843 /* convert from K bytes to qwords used for hw register */
844 start *= 1024/8;
845 space *= 1024/8;
846 end = start + space - 1;
847
848 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
849 sky2_write32(hw, RB_ADDR(q, RB_START), start);
850 sky2_write32(hw, RB_ADDR(q, RB_END), end);
851 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
852 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
853
854 if (q == Q_R1 || q == Q_R2) {
855 u32 tp = space - space/4;
856
857 /* On receive queue's set the thresholds
858 * give receiver priority when > 3/4 full
859 * send pause when down to 2K
860 */
861 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
862 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
863
864 tp = space - 2048/8;
865 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
866 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
867 } else {
868 /* Enable store & forward on Tx queue's because
869 * Tx FIFO is only 1K on Yukon
870 */
871 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
872 }
873
874 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
875 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
876 }
877
878 /* Setup Bus Memory Interface */
879 static void sky2_qset(struct sky2_hw *hw, u16 q)
880 {
881 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
882 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
883 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
884 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
885 }
886
887 /* Setup prefetch unit registers. This is the interface between
888 * hardware and driver list elements
889 */
890 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
891 u64 addr, u32 last)
892 {
893 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
894 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
896 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
897 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
898 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
899
900 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
901 }
902
903 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
904 {
905 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
906
907 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
908 le->ctrl = 0;
909 return le;
910 }
911
912 static void tx_init(struct sky2_port *sky2)
913 {
914 struct sky2_tx_le *le;
915
916 sky2->tx_prod = sky2->tx_cons = 0;
917 sky2->tx_tcpsum = 0;
918 sky2->tx_last_mss = 0;
919
920 le = get_tx_le(sky2);
921 le->addr = 0;
922 le->opcode = OP_ADDR64 | HW_OWNER;
923 sky2->tx_addr64 = 0;
924 }
925
926 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
927 struct sky2_tx_le *le)
928 {
929 return sky2->tx_ring + (le - sky2->tx_le);
930 }
931
932 /* Update chip's next pointer */
933 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
934 {
935 /* Make sure write' to descriptors are complete before we tell hardware */
936 wmb();
937 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
938
939 /* Synchronize I/O on since next processor may write to tail */
940 mmiowb();
941 }
942
943
944 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
945 {
946 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
947 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
948 le->ctrl = 0;
949 return le;
950 }
951
952 /* Build description to hardware for one receive segment */
953 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
954 dma_addr_t map, unsigned len)
955 {
956 struct sky2_rx_le *le;
957 u32 hi = upper_32_bits(map);
958
959 if (sky2->rx_addr64 != hi) {
960 le = sky2_next_rx(sky2);
961 le->addr = cpu_to_le32(hi);
962 le->opcode = OP_ADDR64 | HW_OWNER;
963 sky2->rx_addr64 = upper_32_bits(map + len);
964 }
965
966 le = sky2_next_rx(sky2);
967 le->addr = cpu_to_le32((u32) map);
968 le->length = cpu_to_le16(len);
969 le->opcode = op | HW_OWNER;
970 }
971
972 /* Build description to hardware for one possibly fragmented skb */
973 static void sky2_rx_submit(struct sky2_port *sky2,
974 const struct rx_ring_info *re)
975 {
976 int i;
977
978 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
979
980 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
981 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
982 }
983
984
985 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
986 unsigned size)
987 {
988 struct sk_buff *skb = re->skb;
989 int i;
990
991 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
992 pci_unmap_len_set(re, data_size, size);
993
994 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
995 re->frag_addr[i] = pci_map_page(pdev,
996 skb_shinfo(skb)->frags[i].page,
997 skb_shinfo(skb)->frags[i].page_offset,
998 skb_shinfo(skb)->frags[i].size,
999 PCI_DMA_FROMDEVICE);
1000 }
1001
1002 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1003 {
1004 struct sk_buff *skb = re->skb;
1005 int i;
1006
1007 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1008 PCI_DMA_FROMDEVICE);
1009
1010 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1011 pci_unmap_page(pdev, re->frag_addr[i],
1012 skb_shinfo(skb)->frags[i].size,
1013 PCI_DMA_FROMDEVICE);
1014 }
1015
1016 /* Tell chip where to start receive checksum.
1017 * Actually has two checksums, but set both same to avoid possible byte
1018 * order problems.
1019 */
1020 static void rx_set_checksum(struct sky2_port *sky2)
1021 {
1022 struct sky2_rx_le *le = sky2_next_rx(sky2);
1023
1024 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1025 le->ctrl = 0;
1026 le->opcode = OP_TCPSTART | HW_OWNER;
1027
1028 sky2_write32(sky2->hw,
1029 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1030 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1031 }
1032
1033 /*
1034 * The RX Stop command will not work for Yukon-2 if the BMU does not
1035 * reach the end of packet and since we can't make sure that we have
1036 * incoming data, we must reset the BMU while it is not doing a DMA
1037 * transfer. Since it is possible that the RX path is still active,
1038 * the RX RAM buffer will be stopped first, so any possible incoming
1039 * data will not trigger a DMA. After the RAM buffer is stopped, the
1040 * BMU is polled until any DMA in progress is ended and only then it
1041 * will be reset.
1042 */
1043 static void sky2_rx_stop(struct sky2_port *sky2)
1044 {
1045 struct sky2_hw *hw = sky2->hw;
1046 unsigned rxq = rxqaddr[sky2->port];
1047 int i;
1048
1049 /* disable the RAM Buffer receive queue */
1050 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1051
1052 for (i = 0; i < 0xffff; i++)
1053 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1054 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1055 goto stopped;
1056
1057 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1058 sky2->netdev->name);
1059 stopped:
1060 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1061
1062 /* reset the Rx prefetch unit */
1063 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1064 mmiowb();
1065 }
1066
1067 /* Clean out receive buffer area, assumes receiver hardware stopped */
1068 static void sky2_rx_clean(struct sky2_port *sky2)
1069 {
1070 unsigned i;
1071
1072 memset(sky2->rx_le, 0, RX_LE_BYTES);
1073 for (i = 0; i < sky2->rx_pending; i++) {
1074 struct rx_ring_info *re = sky2->rx_ring + i;
1075
1076 if (re->skb) {
1077 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1078 kfree_skb(re->skb);
1079 re->skb = NULL;
1080 }
1081 }
1082 }
1083
1084 /* Basic MII support */
1085 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1086 {
1087 struct mii_ioctl_data *data = if_mii(ifr);
1088 struct sky2_port *sky2 = netdev_priv(dev);
1089 struct sky2_hw *hw = sky2->hw;
1090 int err = -EOPNOTSUPP;
1091
1092 if (!netif_running(dev))
1093 return -ENODEV; /* Phy still in reset */
1094
1095 switch (cmd) {
1096 case SIOCGMIIPHY:
1097 data->phy_id = PHY_ADDR_MARV;
1098
1099 /* fallthru */
1100 case SIOCGMIIREG: {
1101 u16 val = 0;
1102
1103 spin_lock_bh(&sky2->phy_lock);
1104 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1105 spin_unlock_bh(&sky2->phy_lock);
1106
1107 data->val_out = val;
1108 break;
1109 }
1110
1111 case SIOCSMIIREG:
1112 if (!capable(CAP_NET_ADMIN))
1113 return -EPERM;
1114
1115 spin_lock_bh(&sky2->phy_lock);
1116 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1117 data->val_in);
1118 spin_unlock_bh(&sky2->phy_lock);
1119 break;
1120 }
1121 return err;
1122 }
1123
1124 #ifdef SKY2_VLAN_TAG_USED
1125 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1126 {
1127 struct sky2_port *sky2 = netdev_priv(dev);
1128 struct sky2_hw *hw = sky2->hw;
1129 u16 port = sky2->port;
1130
1131 netif_tx_lock_bh(dev);
1132 napi_disable(&hw->napi);
1133
1134 sky2->vlgrp = grp;
1135 if (grp) {
1136 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1137 RX_VLAN_STRIP_ON);
1138 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1139 TX_VLAN_TAG_ON);
1140 } else {
1141 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1142 RX_VLAN_STRIP_OFF);
1143 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1144 TX_VLAN_TAG_OFF);
1145 }
1146
1147 napi_enable(&hw->napi);
1148 netif_tx_unlock_bh(dev);
1149 }
1150 #endif
1151
1152 /*
1153 * Allocate an skb for receiving. If the MTU is large enough
1154 * make the skb non-linear with a fragment list of pages.
1155 *
1156 * It appears the hardware has a bug in the FIFO logic that
1157 * cause it to hang if the FIFO gets overrun and the receive buffer
1158 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1159 * aligned except if slab debugging is enabled.
1160 */
1161 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1162 {
1163 struct sk_buff *skb;
1164 unsigned long p;
1165 int i;
1166
1167 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1168 if (!skb)
1169 goto nomem;
1170
1171 p = (unsigned long) skb->data;
1172 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1173
1174 for (i = 0; i < sky2->rx_nfrags; i++) {
1175 struct page *page = alloc_page(GFP_ATOMIC);
1176
1177 if (!page)
1178 goto free_partial;
1179 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1180 }
1181
1182 return skb;
1183 free_partial:
1184 kfree_skb(skb);
1185 nomem:
1186 return NULL;
1187 }
1188
1189 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1190 {
1191 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1192 }
1193
1194 /*
1195 * Allocate and setup receiver buffer pool.
1196 * Normal case this ends up creating one list element for skb
1197 * in the receive ring. Worst case if using large MTU and each
1198 * allocation falls on a different 64 bit region, that results
1199 * in 6 list elements per ring entry.
1200 * One element is used for checksum enable/disable, and one
1201 * extra to avoid wrap.
1202 */
1203 static int sky2_rx_start(struct sky2_port *sky2)
1204 {
1205 struct sky2_hw *hw = sky2->hw;
1206 struct rx_ring_info *re;
1207 unsigned rxq = rxqaddr[sky2->port];
1208 unsigned i, size, space, thresh;
1209
1210 sky2->rx_put = sky2->rx_next = 0;
1211 sky2_qset(hw, rxq);
1212
1213 /* On PCI express lowering the watermark gives better performance */
1214 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1215 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1216
1217 /* These chips have no ram buffer?
1218 * MAC Rx RAM Read is controlled by hardware */
1219 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1220 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1221 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1222 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1223
1224 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1225
1226 if (!(hw->flags & SKY2_HW_NEW_LE))
1227 rx_set_checksum(sky2);
1228
1229 /* Space needed for frame data + headers rounded up */
1230 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1231
1232 /* Stopping point for hardware truncation */
1233 thresh = (size - 8) / sizeof(u32);
1234
1235 /* Account for overhead of skb - to avoid order > 0 allocation */
1236 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1237 + sizeof(struct skb_shared_info);
1238
1239 sky2->rx_nfrags = space >> PAGE_SHIFT;
1240 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1241
1242 if (sky2->rx_nfrags != 0) {
1243 /* Compute residue after pages */
1244 space = sky2->rx_nfrags << PAGE_SHIFT;
1245
1246 if (space < size)
1247 size -= space;
1248 else
1249 size = 0;
1250
1251 /* Optimize to handle small packets and headers */
1252 if (size < copybreak)
1253 size = copybreak;
1254 if (size < ETH_HLEN)
1255 size = ETH_HLEN;
1256 }
1257 sky2->rx_data_size = size;
1258
1259 /* Fill Rx ring */
1260 for (i = 0; i < sky2->rx_pending; i++) {
1261 re = sky2->rx_ring + i;
1262
1263 re->skb = sky2_rx_alloc(sky2);
1264 if (!re->skb)
1265 goto nomem;
1266
1267 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1268 sky2_rx_submit(sky2, re);
1269 }
1270
1271 /*
1272 * The receiver hangs if it receives frames larger than the
1273 * packet buffer. As a workaround, truncate oversize frames, but
1274 * the register is limited to 9 bits, so if you do frames > 2052
1275 * you better get the MTU right!
1276 */
1277 if (thresh > 0x1ff)
1278 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1279 else {
1280 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1281 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1282 }
1283
1284 /* Tell chip about available buffers */
1285 sky2_rx_update(sky2, rxq);
1286 return 0;
1287 nomem:
1288 sky2_rx_clean(sky2);
1289 return -ENOMEM;
1290 }
1291
1292 /* Bring up network interface. */
1293 static int sky2_up(struct net_device *dev)
1294 {
1295 struct sky2_port *sky2 = netdev_priv(dev);
1296 struct sky2_hw *hw = sky2->hw;
1297 unsigned port = sky2->port;
1298 u32 imask, ramsize;
1299 int cap, err = -ENOMEM;
1300 struct net_device *otherdev = hw->dev[sky2->port^1];
1301
1302 /*
1303 * On dual port PCI-X card, there is an problem where status
1304 * can be received out of order due to split transactions
1305 */
1306 if (otherdev && netif_running(otherdev) &&
1307 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1308 struct sky2_port *osky2 = netdev_priv(otherdev);
1309 u16 cmd;
1310
1311 pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd);
1312 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1313 pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd);
1314
1315 sky2->rx_csum = 0;
1316 osky2->rx_csum = 0;
1317 }
1318
1319 if (netif_msg_ifup(sky2))
1320 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1321
1322 netif_carrier_off(dev);
1323
1324 /* must be power of 2 */
1325 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1326 TX_RING_SIZE *
1327 sizeof(struct sky2_tx_le),
1328 &sky2->tx_le_map);
1329 if (!sky2->tx_le)
1330 goto err_out;
1331
1332 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1333 GFP_KERNEL);
1334 if (!sky2->tx_ring)
1335 goto err_out;
1336
1337 tx_init(sky2);
1338
1339 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1340 &sky2->rx_le_map);
1341 if (!sky2->rx_le)
1342 goto err_out;
1343 memset(sky2->rx_le, 0, RX_LE_BYTES);
1344
1345 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1346 GFP_KERNEL);
1347 if (!sky2->rx_ring)
1348 goto err_out;
1349
1350 sky2_phy_power(hw, port, 1);
1351
1352 sky2_mac_init(hw, port);
1353
1354 /* Register is number of 4K blocks on internal RAM buffer. */
1355 ramsize = sky2_read8(hw, B2_E_0) * 4;
1356 if (ramsize > 0) {
1357 u32 rxspace;
1358
1359 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1360 if (ramsize < 16)
1361 rxspace = ramsize / 2;
1362 else
1363 rxspace = 8 + (2*(ramsize - 16))/3;
1364
1365 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1366 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1367
1368 /* Make sure SyncQ is disabled */
1369 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1370 RB_RST_SET);
1371 }
1372
1373 sky2_qset(hw, txqaddr[port]);
1374
1375 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1376 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1377 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1378
1379 /* Set almost empty threshold */
1380 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1381 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1382 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1383
1384 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1385 TX_RING_SIZE - 1);
1386
1387 napi_enable(&hw->napi);
1388
1389 err = sky2_rx_start(sky2);
1390 if (err) {
1391 napi_disable(&hw->napi);
1392 goto err_out;
1393 }
1394
1395 /* Enable interrupts from phy/mac for port */
1396 imask = sky2_read32(hw, B0_IMSK);
1397 imask |= portirq_msk[port];
1398 sky2_write32(hw, B0_IMSK, imask);
1399
1400 return 0;
1401
1402 err_out:
1403 if (sky2->rx_le) {
1404 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1405 sky2->rx_le, sky2->rx_le_map);
1406 sky2->rx_le = NULL;
1407 }
1408 if (sky2->tx_le) {
1409 pci_free_consistent(hw->pdev,
1410 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1411 sky2->tx_le, sky2->tx_le_map);
1412 sky2->tx_le = NULL;
1413 }
1414 kfree(sky2->tx_ring);
1415 kfree(sky2->rx_ring);
1416
1417 sky2->tx_ring = NULL;
1418 sky2->rx_ring = NULL;
1419 return err;
1420 }
1421
1422 /* Modular subtraction in ring */
1423 static inline int tx_dist(unsigned tail, unsigned head)
1424 {
1425 return (head - tail) & (TX_RING_SIZE - 1);
1426 }
1427
1428 /* Number of list elements available for next tx */
1429 static inline int tx_avail(const struct sky2_port *sky2)
1430 {
1431 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1432 }
1433
1434 /* Estimate of number of transmit list elements required */
1435 static unsigned tx_le_req(const struct sk_buff *skb)
1436 {
1437 unsigned count;
1438
1439 count = sizeof(dma_addr_t) / sizeof(u32);
1440 count += skb_shinfo(skb)->nr_frags * count;
1441
1442 if (skb_is_gso(skb))
1443 ++count;
1444
1445 if (skb->ip_summed == CHECKSUM_PARTIAL)
1446 ++count;
1447
1448 return count;
1449 }
1450
1451 /*
1452 * Put one packet in ring for transmit.
1453 * A single packet can generate multiple list elements, and
1454 * the number of ring elements will probably be less than the number
1455 * of list elements used.
1456 */
1457 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1458 {
1459 struct sky2_port *sky2 = netdev_priv(dev);
1460 struct sky2_hw *hw = sky2->hw;
1461 struct sky2_tx_le *le = NULL;
1462 struct tx_ring_info *re;
1463 unsigned i, len;
1464 dma_addr_t mapping;
1465 u32 addr64;
1466 u16 mss;
1467 u8 ctrl;
1468
1469 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1470 return NETDEV_TX_BUSY;
1471
1472 if (unlikely(netif_msg_tx_queued(sky2)))
1473 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1474 dev->name, sky2->tx_prod, skb->len);
1475
1476 len = skb_headlen(skb);
1477 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1478 addr64 = upper_32_bits(mapping);
1479
1480 /* Send high bits if changed or crosses boundary */
1481 if (addr64 != sky2->tx_addr64 ||
1482 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1483 le = get_tx_le(sky2);
1484 le->addr = cpu_to_le32(addr64);
1485 le->opcode = OP_ADDR64 | HW_OWNER;
1486 sky2->tx_addr64 = upper_32_bits(mapping + len);
1487 }
1488
1489 /* Check for TCP Segmentation Offload */
1490 mss = skb_shinfo(skb)->gso_size;
1491 if (mss != 0) {
1492
1493 if (!(hw->flags & SKY2_HW_NEW_LE))
1494 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1495
1496 if (mss != sky2->tx_last_mss) {
1497 le = get_tx_le(sky2);
1498 le->addr = cpu_to_le32(mss);
1499
1500 if (hw->flags & SKY2_HW_NEW_LE)
1501 le->opcode = OP_MSS | HW_OWNER;
1502 else
1503 le->opcode = OP_LRGLEN | HW_OWNER;
1504 sky2->tx_last_mss = mss;
1505 }
1506 }
1507
1508 ctrl = 0;
1509 #ifdef SKY2_VLAN_TAG_USED
1510 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1511 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1512 if (!le) {
1513 le = get_tx_le(sky2);
1514 le->addr = 0;
1515 le->opcode = OP_VLAN|HW_OWNER;
1516 } else
1517 le->opcode |= OP_VLAN;
1518 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1519 ctrl |= INS_VLAN;
1520 }
1521 #endif
1522
1523 /* Handle TCP checksum offload */
1524 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1525 /* On Yukon EX (some versions) encoding change. */
1526 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1527 ctrl |= CALSUM; /* auto checksum */
1528 else {
1529 const unsigned offset = skb_transport_offset(skb);
1530 u32 tcpsum;
1531
1532 tcpsum = offset << 16; /* sum start */
1533 tcpsum |= offset + skb->csum_offset; /* sum write */
1534
1535 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1536 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1537 ctrl |= UDPTCP;
1538
1539 if (tcpsum != sky2->tx_tcpsum) {
1540 sky2->tx_tcpsum = tcpsum;
1541
1542 le = get_tx_le(sky2);
1543 le->addr = cpu_to_le32(tcpsum);
1544 le->length = 0; /* initial checksum value */
1545 le->ctrl = 1; /* one packet */
1546 le->opcode = OP_TCPLISW | HW_OWNER;
1547 }
1548 }
1549 }
1550
1551 le = get_tx_le(sky2);
1552 le->addr = cpu_to_le32((u32) mapping);
1553 le->length = cpu_to_le16(len);
1554 le->ctrl = ctrl;
1555 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1556
1557 re = tx_le_re(sky2, le);
1558 re->skb = skb;
1559 pci_unmap_addr_set(re, mapaddr, mapping);
1560 pci_unmap_len_set(re, maplen, len);
1561
1562 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1563 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1564
1565 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1566 frag->size, PCI_DMA_TODEVICE);
1567 addr64 = upper_32_bits(mapping);
1568 if (addr64 != sky2->tx_addr64) {
1569 le = get_tx_le(sky2);
1570 le->addr = cpu_to_le32(addr64);
1571 le->ctrl = 0;
1572 le->opcode = OP_ADDR64 | HW_OWNER;
1573 sky2->tx_addr64 = addr64;
1574 }
1575
1576 le = get_tx_le(sky2);
1577 le->addr = cpu_to_le32((u32) mapping);
1578 le->length = cpu_to_le16(frag->size);
1579 le->ctrl = ctrl;
1580 le->opcode = OP_BUFFER | HW_OWNER;
1581
1582 re = tx_le_re(sky2, le);
1583 re->skb = skb;
1584 pci_unmap_addr_set(re, mapaddr, mapping);
1585 pci_unmap_len_set(re, maplen, frag->size);
1586 }
1587
1588 le->ctrl |= EOP;
1589
1590 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1591 netif_stop_queue(dev);
1592
1593 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1594
1595 dev->trans_start = jiffies;
1596 return NETDEV_TX_OK;
1597 }
1598
1599 /*
1600 * Free ring elements from starting at tx_cons until "done"
1601 *
1602 * NB: the hardware will tell us about partial completion of multi-part
1603 * buffers so make sure not to free skb to early.
1604 */
1605 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1606 {
1607 struct net_device *dev = sky2->netdev;
1608 struct pci_dev *pdev = sky2->hw->pdev;
1609 unsigned idx;
1610
1611 BUG_ON(done >= TX_RING_SIZE);
1612
1613 for (idx = sky2->tx_cons; idx != done;
1614 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1615 struct sky2_tx_le *le = sky2->tx_le + idx;
1616 struct tx_ring_info *re = sky2->tx_ring + idx;
1617
1618 switch(le->opcode & ~HW_OWNER) {
1619 case OP_LARGESEND:
1620 case OP_PACKET:
1621 pci_unmap_single(pdev,
1622 pci_unmap_addr(re, mapaddr),
1623 pci_unmap_len(re, maplen),
1624 PCI_DMA_TODEVICE);
1625 break;
1626 case OP_BUFFER:
1627 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1628 pci_unmap_len(re, maplen),
1629 PCI_DMA_TODEVICE);
1630 break;
1631 }
1632
1633 if (le->ctrl & EOP) {
1634 if (unlikely(netif_msg_tx_done(sky2)))
1635 printk(KERN_DEBUG "%s: tx done %u\n",
1636 dev->name, idx);
1637
1638 dev->stats.tx_packets++;
1639 dev->stats.tx_bytes += re->skb->len;
1640
1641 dev_kfree_skb_any(re->skb);
1642 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1643 }
1644 }
1645
1646 sky2->tx_cons = idx;
1647 smp_mb();
1648
1649 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1650 netif_wake_queue(dev);
1651 }
1652
1653 /* Cleanup all untransmitted buffers, assume transmitter not running */
1654 static void sky2_tx_clean(struct net_device *dev)
1655 {
1656 struct sky2_port *sky2 = netdev_priv(dev);
1657
1658 netif_tx_lock_bh(dev);
1659 sky2_tx_complete(sky2, sky2->tx_prod);
1660 netif_tx_unlock_bh(dev);
1661 }
1662
1663 /* Network shutdown */
1664 static int sky2_down(struct net_device *dev)
1665 {
1666 struct sky2_port *sky2 = netdev_priv(dev);
1667 struct sky2_hw *hw = sky2->hw;
1668 unsigned port = sky2->port;
1669 u16 ctrl;
1670 u32 imask;
1671
1672 /* Never really got started! */
1673 if (!sky2->tx_le)
1674 return 0;
1675
1676 if (netif_msg_ifdown(sky2))
1677 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1678
1679 /* Stop more packets from being queued */
1680 netif_stop_queue(dev);
1681
1682 napi_disable(&hw->napi);
1683
1684 /* Disable port IRQ */
1685 imask = sky2_read32(hw, B0_IMSK);
1686 imask &= ~portirq_msk[port];
1687 sky2_write32(hw, B0_IMSK, imask);
1688
1689 sky2_gmac_reset(hw, port);
1690
1691 /* Stop transmitter */
1692 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1693 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1694
1695 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1696 RB_RST_SET | RB_DIS_OP_MD);
1697
1698 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1699 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1700 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1701
1702 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1703
1704 /* Workaround shared GMAC reset */
1705 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1706 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1707 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1708
1709 /* Disable Force Sync bit and Enable Alloc bit */
1710 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1711 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1712
1713 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1714 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1715 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1716
1717 /* Reset the PCI FIFO of the async Tx queue */
1718 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1719 BMU_RST_SET | BMU_FIFO_RST);
1720
1721 /* Reset the Tx prefetch units */
1722 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1723 PREF_UNIT_RST_SET);
1724
1725 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1726
1727 sky2_rx_stop(sky2);
1728
1729 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1730 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1731
1732 sky2_phy_power(hw, port, 0);
1733
1734 netif_carrier_off(dev);
1735
1736 /* turn off LED's */
1737 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1738
1739 synchronize_irq(hw->pdev->irq);
1740
1741 sky2_tx_clean(dev);
1742 sky2_rx_clean(sky2);
1743
1744 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1745 sky2->rx_le, sky2->rx_le_map);
1746 kfree(sky2->rx_ring);
1747
1748 pci_free_consistent(hw->pdev,
1749 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1750 sky2->tx_le, sky2->tx_le_map);
1751 kfree(sky2->tx_ring);
1752
1753 sky2->tx_le = NULL;
1754 sky2->rx_le = NULL;
1755
1756 sky2->rx_ring = NULL;
1757 sky2->tx_ring = NULL;
1758
1759 return 0;
1760 }
1761
1762 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1763 {
1764 if (hw->flags & SKY2_HW_FIBRE_PHY)
1765 return SPEED_1000;
1766
1767 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1768 if (aux & PHY_M_PS_SPEED_100)
1769 return SPEED_100;
1770 else
1771 return SPEED_10;
1772 }
1773
1774 switch (aux & PHY_M_PS_SPEED_MSK) {
1775 case PHY_M_PS_SPEED_1000:
1776 return SPEED_1000;
1777 case PHY_M_PS_SPEED_100:
1778 return SPEED_100;
1779 default:
1780 return SPEED_10;
1781 }
1782 }
1783
1784 static void sky2_link_up(struct sky2_port *sky2)
1785 {
1786 struct sky2_hw *hw = sky2->hw;
1787 unsigned port = sky2->port;
1788 u16 reg;
1789 static const char *fc_name[] = {
1790 [FC_NONE] = "none",
1791 [FC_TX] = "tx",
1792 [FC_RX] = "rx",
1793 [FC_BOTH] = "both",
1794 };
1795
1796 /* enable Rx/Tx */
1797 reg = gma_read16(hw, port, GM_GP_CTRL);
1798 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1799 gma_write16(hw, port, GM_GP_CTRL, reg);
1800
1801 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1802
1803 netif_carrier_on(sky2->netdev);
1804
1805 mod_timer(&hw->watchdog_timer, jiffies + 1);
1806
1807 /* Turn on link LED */
1808 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1809 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1810
1811 if (hw->flags & SKY2_HW_NEWER_PHY) {
1812 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1813 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1814
1815 switch(sky2->speed) {
1816 case SPEED_10:
1817 led |= PHY_M_LEDC_INIT_CTRL(7);
1818 break;
1819
1820 case SPEED_100:
1821 led |= PHY_M_LEDC_STA1_CTRL(7);
1822 break;
1823
1824 case SPEED_1000:
1825 led |= PHY_M_LEDC_STA0_CTRL(7);
1826 break;
1827 }
1828
1829 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1830 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1831 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1832 }
1833
1834 if (netif_msg_link(sky2))
1835 printk(KERN_INFO PFX
1836 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1837 sky2->netdev->name, sky2->speed,
1838 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1839 fc_name[sky2->flow_status]);
1840 }
1841
1842 static void sky2_link_down(struct sky2_port *sky2)
1843 {
1844 struct sky2_hw *hw = sky2->hw;
1845 unsigned port = sky2->port;
1846 u16 reg;
1847
1848 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1849
1850 reg = gma_read16(hw, port, GM_GP_CTRL);
1851 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1852 gma_write16(hw, port, GM_GP_CTRL, reg);
1853
1854 netif_carrier_off(sky2->netdev);
1855
1856 /* Turn on link LED */
1857 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1858
1859 if (netif_msg_link(sky2))
1860 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1861
1862 sky2_phy_init(hw, port);
1863 }
1864
1865 static enum flow_control sky2_flow(int rx, int tx)
1866 {
1867 if (rx)
1868 return tx ? FC_BOTH : FC_RX;
1869 else
1870 return tx ? FC_TX : FC_NONE;
1871 }
1872
1873 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1874 {
1875 struct sky2_hw *hw = sky2->hw;
1876 unsigned port = sky2->port;
1877 u16 advert, lpa;
1878
1879 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1880 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1881 if (lpa & PHY_M_AN_RF) {
1882 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1883 return -1;
1884 }
1885
1886 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1887 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1888 sky2->netdev->name);
1889 return -1;
1890 }
1891
1892 sky2->speed = sky2_phy_speed(hw, aux);
1893 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1894
1895 /* Since the pause result bits seem to in different positions on
1896 * different chips. look at registers.
1897 */
1898 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1899 /* Shift for bits in fiber PHY */
1900 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1901 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1902
1903 if (advert & ADVERTISE_1000XPAUSE)
1904 advert |= ADVERTISE_PAUSE_CAP;
1905 if (advert & ADVERTISE_1000XPSE_ASYM)
1906 advert |= ADVERTISE_PAUSE_ASYM;
1907 if (lpa & LPA_1000XPAUSE)
1908 lpa |= LPA_PAUSE_CAP;
1909 if (lpa & LPA_1000XPAUSE_ASYM)
1910 lpa |= LPA_PAUSE_ASYM;
1911 }
1912
1913 sky2->flow_status = FC_NONE;
1914 if (advert & ADVERTISE_PAUSE_CAP) {
1915 if (lpa & LPA_PAUSE_CAP)
1916 sky2->flow_status = FC_BOTH;
1917 else if (advert & ADVERTISE_PAUSE_ASYM)
1918 sky2->flow_status = FC_RX;
1919 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1920 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1921 sky2->flow_status = FC_TX;
1922 }
1923
1924 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1925 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1926 sky2->flow_status = FC_NONE;
1927
1928 if (sky2->flow_status & FC_TX)
1929 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1930 else
1931 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1932
1933 return 0;
1934 }
1935
1936 /* Interrupt from PHY */
1937 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1938 {
1939 struct net_device *dev = hw->dev[port];
1940 struct sky2_port *sky2 = netdev_priv(dev);
1941 u16 istatus, phystat;
1942
1943 if (!netif_running(dev))
1944 return;
1945
1946 spin_lock(&sky2->phy_lock);
1947 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1948 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1949
1950 if (netif_msg_intr(sky2))
1951 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1952 sky2->netdev->name, istatus, phystat);
1953
1954 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1955 if (sky2_autoneg_done(sky2, phystat) == 0)
1956 sky2_link_up(sky2);
1957 goto out;
1958 }
1959
1960 if (istatus & PHY_M_IS_LSP_CHANGE)
1961 sky2->speed = sky2_phy_speed(hw, phystat);
1962
1963 if (istatus & PHY_M_IS_DUP_CHANGE)
1964 sky2->duplex =
1965 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1966
1967 if (istatus & PHY_M_IS_LST_CHANGE) {
1968 if (phystat & PHY_M_PS_LINK_UP)
1969 sky2_link_up(sky2);
1970 else
1971 sky2_link_down(sky2);
1972 }
1973 out:
1974 spin_unlock(&sky2->phy_lock);
1975 }
1976
1977 /* Transmit timeout is only called if we are running, carrier is up
1978 * and tx queue is full (stopped).
1979 */
1980 static void sky2_tx_timeout(struct net_device *dev)
1981 {
1982 struct sky2_port *sky2 = netdev_priv(dev);
1983 struct sky2_hw *hw = sky2->hw;
1984
1985 if (netif_msg_timer(sky2))
1986 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1987
1988 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1989 dev->name, sky2->tx_cons, sky2->tx_prod,
1990 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1991 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1992
1993 /* can't restart safely under softirq */
1994 schedule_work(&hw->restart_work);
1995 }
1996
1997 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1998 {
1999 struct sky2_port *sky2 = netdev_priv(dev);
2000 struct sky2_hw *hw = sky2->hw;
2001 unsigned port = sky2->port;
2002 int err;
2003 u16 ctl, mode;
2004 u32 imask;
2005
2006 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2007 return -EINVAL;
2008
2009 if (new_mtu > ETH_DATA_LEN &&
2010 (hw->chip_id == CHIP_ID_YUKON_FE ||
2011 hw->chip_id == CHIP_ID_YUKON_FE_P))
2012 return -EINVAL;
2013
2014 if (!netif_running(dev)) {
2015 dev->mtu = new_mtu;
2016 return 0;
2017 }
2018
2019 imask = sky2_read32(hw, B0_IMSK);
2020 sky2_write32(hw, B0_IMSK, 0);
2021
2022 dev->trans_start = jiffies; /* prevent tx timeout */
2023 netif_stop_queue(dev);
2024 napi_disable(&hw->napi);
2025
2026 synchronize_irq(hw->pdev->irq);
2027
2028 if (sky2_read8(hw, B2_E_0) == 0)
2029 sky2_set_tx_stfwd(hw, port);
2030
2031 ctl = gma_read16(hw, port, GM_GP_CTRL);
2032 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2033 sky2_rx_stop(sky2);
2034 sky2_rx_clean(sky2);
2035
2036 dev->mtu = new_mtu;
2037
2038 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2039 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2040
2041 if (dev->mtu > ETH_DATA_LEN)
2042 mode |= GM_SMOD_JUMBO_ENA;
2043
2044 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2045
2046 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2047
2048 err = sky2_rx_start(sky2);
2049 sky2_write32(hw, B0_IMSK, imask);
2050
2051 /* Unconditionally re-enable NAPI because even if we
2052 * call dev_close() that will do a napi_disable().
2053 */
2054 napi_enable(&hw->napi);
2055
2056 if (err)
2057 dev_close(dev);
2058 else {
2059 gma_write16(hw, port, GM_GP_CTRL, ctl);
2060
2061 netif_wake_queue(dev);
2062 }
2063
2064 return err;
2065 }
2066
2067 /* For small just reuse existing skb for next receive */
2068 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2069 const struct rx_ring_info *re,
2070 unsigned length)
2071 {
2072 struct sk_buff *skb;
2073
2074 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2075 if (likely(skb)) {
2076 skb_reserve(skb, 2);
2077 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2078 length, PCI_DMA_FROMDEVICE);
2079 skb_copy_from_linear_data(re->skb, skb->data, length);
2080 skb->ip_summed = re->skb->ip_summed;
2081 skb->csum = re->skb->csum;
2082 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2083 length, PCI_DMA_FROMDEVICE);
2084 re->skb->ip_summed = CHECKSUM_NONE;
2085 skb_put(skb, length);
2086 }
2087 return skb;
2088 }
2089
2090 /* Adjust length of skb with fragments to match received data */
2091 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2092 unsigned int length)
2093 {
2094 int i, num_frags;
2095 unsigned int size;
2096
2097 /* put header into skb */
2098 size = min(length, hdr_space);
2099 skb->tail += size;
2100 skb->len += size;
2101 length -= size;
2102
2103 num_frags = skb_shinfo(skb)->nr_frags;
2104 for (i = 0; i < num_frags; i++) {
2105 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2106
2107 if (length == 0) {
2108 /* don't need this page */
2109 __free_page(frag->page);
2110 --skb_shinfo(skb)->nr_frags;
2111 } else {
2112 size = min(length, (unsigned) PAGE_SIZE);
2113
2114 frag->size = size;
2115 skb->data_len += size;
2116 skb->truesize += size;
2117 skb->len += size;
2118 length -= size;
2119 }
2120 }
2121 }
2122
2123 /* Normal packet - take skb from ring element and put in a new one */
2124 static struct sk_buff *receive_new(struct sky2_port *sky2,
2125 struct rx_ring_info *re,
2126 unsigned int length)
2127 {
2128 struct sk_buff *skb, *nskb;
2129 unsigned hdr_space = sky2->rx_data_size;
2130
2131 /* Don't be tricky about reusing pages (yet) */
2132 nskb = sky2_rx_alloc(sky2);
2133 if (unlikely(!nskb))
2134 return NULL;
2135
2136 skb = re->skb;
2137 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2138
2139 prefetch(skb->data);
2140 re->skb = nskb;
2141 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2142
2143 if (skb_shinfo(skb)->nr_frags)
2144 skb_put_frags(skb, hdr_space, length);
2145 else
2146 skb_put(skb, length);
2147 return skb;
2148 }
2149
2150 /*
2151 * Receive one packet.
2152 * For larger packets, get new buffer.
2153 */
2154 static struct sk_buff *sky2_receive(struct net_device *dev,
2155 u16 length, u32 status)
2156 {
2157 struct sky2_port *sky2 = netdev_priv(dev);
2158 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2159 struct sk_buff *skb = NULL;
2160 u16 count = (status & GMR_FS_LEN) >> 16;
2161
2162 #ifdef SKY2_VLAN_TAG_USED
2163 /* Account for vlan tag */
2164 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2165 count -= VLAN_HLEN;
2166 #endif
2167
2168 if (unlikely(netif_msg_rx_status(sky2)))
2169 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2170 dev->name, sky2->rx_next, status, length);
2171
2172 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2173 prefetch(sky2->rx_ring + sky2->rx_next);
2174
2175 /* This chip has hardware problems that generates bogus status.
2176 * So do only marginal checking and expect higher level protocols
2177 * to handle crap frames.
2178 */
2179 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2180 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2181 length != count)
2182 goto okay;
2183
2184 if (status & GMR_FS_ANY_ERR)
2185 goto error;
2186
2187 if (!(status & GMR_FS_RX_OK))
2188 goto resubmit;
2189
2190 /* if length reported by DMA does not match PHY, packet was truncated */
2191 if (length != count)
2192 goto len_error;
2193
2194 okay:
2195 if (length < copybreak)
2196 skb = receive_copy(sky2, re, length);
2197 else
2198 skb = receive_new(sky2, re, length);
2199 resubmit:
2200 sky2_rx_submit(sky2, re);
2201
2202 return skb;
2203
2204 len_error:
2205 /* Truncation of overlength packets
2206 causes PHY length to not match MAC length */
2207 ++dev->stats.rx_length_errors;
2208 if (netif_msg_rx_err(sky2) && net_ratelimit())
2209 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2210 dev->name, status, length);
2211 goto resubmit;
2212
2213 error:
2214 ++dev->stats.rx_errors;
2215 if (status & GMR_FS_RX_FF_OV) {
2216 dev->stats.rx_over_errors++;
2217 goto resubmit;
2218 }
2219
2220 if (netif_msg_rx_err(sky2) && net_ratelimit())
2221 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2222 dev->name, status, length);
2223
2224 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2225 dev->stats.rx_length_errors++;
2226 if (status & GMR_FS_FRAGMENT)
2227 dev->stats.rx_frame_errors++;
2228 if (status & GMR_FS_CRC_ERR)
2229 dev->stats.rx_crc_errors++;
2230
2231 goto resubmit;
2232 }
2233
2234 /* Transmit complete */
2235 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2236 {
2237 struct sky2_port *sky2 = netdev_priv(dev);
2238
2239 if (netif_running(dev)) {
2240 netif_tx_lock(dev);
2241 sky2_tx_complete(sky2, last);
2242 netif_tx_unlock(dev);
2243 }
2244 }
2245
2246 /* Process status response ring */
2247 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2248 {
2249 int work_done = 0;
2250 unsigned rx[2] = { 0, 0 };
2251
2252 rmb();
2253 do {
2254 struct sky2_port *sky2;
2255 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2256 unsigned port = le->css & CSS_LINK_BIT;
2257 struct net_device *dev;
2258 struct sk_buff *skb;
2259 u32 status;
2260 u16 length;
2261
2262 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2263
2264 dev = hw->dev[port];
2265 sky2 = netdev_priv(dev);
2266 length = le16_to_cpu(le->length);
2267 status = le32_to_cpu(le->status);
2268
2269 switch (le->opcode & ~HW_OWNER) {
2270 case OP_RXSTAT:
2271 ++rx[port];
2272 skb = sky2_receive(dev, length, status);
2273 if (unlikely(!skb)) {
2274 dev->stats.rx_dropped++;
2275 break;
2276 }
2277
2278 /* This chip reports checksum status differently */
2279 if (hw->flags & SKY2_HW_NEW_LE) {
2280 if (sky2->rx_csum &&
2281 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2282 (le->css & CSS_TCPUDPCSOK))
2283 skb->ip_summed = CHECKSUM_UNNECESSARY;
2284 else
2285 skb->ip_summed = CHECKSUM_NONE;
2286 }
2287
2288 skb->protocol = eth_type_trans(skb, dev);
2289 dev->stats.rx_packets++;
2290 dev->stats.rx_bytes += skb->len;
2291 dev->last_rx = jiffies;
2292
2293 #ifdef SKY2_VLAN_TAG_USED
2294 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2295 vlan_hwaccel_receive_skb(skb,
2296 sky2->vlgrp,
2297 be16_to_cpu(sky2->rx_tag));
2298 } else
2299 #endif
2300 netif_receive_skb(skb);
2301
2302 /* Stop after net poll weight */
2303 if (++work_done >= to_do)
2304 goto exit_loop;
2305 break;
2306
2307 #ifdef SKY2_VLAN_TAG_USED
2308 case OP_RXVLAN:
2309 sky2->rx_tag = length;
2310 break;
2311
2312 case OP_RXCHKSVLAN:
2313 sky2->rx_tag = length;
2314 /* fall through */
2315 #endif
2316 case OP_RXCHKS:
2317 if (!sky2->rx_csum)
2318 break;
2319
2320 /* If this happens then driver assuming wrong format */
2321 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2322 if (net_ratelimit())
2323 printk(KERN_NOTICE "%s: unexpected"
2324 " checksum status\n",
2325 dev->name);
2326 break;
2327 }
2328
2329 /* Both checksum counters are programmed to start at
2330 * the same offset, so unless there is a problem they
2331 * should match. This failure is an early indication that
2332 * hardware receive checksumming won't work.
2333 */
2334 if (likely(status >> 16 == (status & 0xffff))) {
2335 skb = sky2->rx_ring[sky2->rx_next].skb;
2336 skb->ip_summed = CHECKSUM_COMPLETE;
2337 skb->csum = status & 0xffff;
2338 } else {
2339 printk(KERN_NOTICE PFX "%s: hardware receive "
2340 "checksum problem (status = %#x)\n",
2341 dev->name, status);
2342 sky2->rx_csum = 0;
2343 sky2_write32(sky2->hw,
2344 Q_ADDR(rxqaddr[port], Q_CSR),
2345 BMU_DIS_RX_CHKSUM);
2346 }
2347 break;
2348
2349 case OP_TXINDEXLE:
2350 /* TX index reports status for both ports */
2351 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2352 sky2_tx_done(hw->dev[0], status & 0xfff);
2353 if (hw->dev[1])
2354 sky2_tx_done(hw->dev[1],
2355 ((status >> 24) & 0xff)
2356 | (u16)(length & 0xf) << 8);
2357 break;
2358
2359 default:
2360 if (net_ratelimit())
2361 printk(KERN_WARNING PFX
2362 "unknown status opcode 0x%x\n", le->opcode);
2363 }
2364 } while (hw->st_idx != idx);
2365
2366 /* Fully processed status ring so clear irq */
2367 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2368
2369 exit_loop:
2370 if (rx[0])
2371 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2372
2373 if (rx[1])
2374 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2375
2376 return work_done;
2377 }
2378
2379 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2380 {
2381 struct net_device *dev = hw->dev[port];
2382
2383 if (net_ratelimit())
2384 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2385 dev->name, status);
2386
2387 if (status & Y2_IS_PAR_RD1) {
2388 if (net_ratelimit())
2389 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2390 dev->name);
2391 /* Clear IRQ */
2392 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2393 }
2394
2395 if (status & Y2_IS_PAR_WR1) {
2396 if (net_ratelimit())
2397 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2398 dev->name);
2399
2400 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2401 }
2402
2403 if (status & Y2_IS_PAR_MAC1) {
2404 if (net_ratelimit())
2405 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2407 }
2408
2409 if (status & Y2_IS_PAR_RX1) {
2410 if (net_ratelimit())
2411 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2412 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2413 }
2414
2415 if (status & Y2_IS_TCP_TXA1) {
2416 if (net_ratelimit())
2417 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2418 dev->name);
2419 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2420 }
2421 }
2422
2423 static void sky2_hw_intr(struct sky2_hw *hw)
2424 {
2425 struct pci_dev *pdev = hw->pdev;
2426 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2427 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2428
2429 status &= hwmsk;
2430
2431 if (status & Y2_IS_TIST_OV)
2432 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2433
2434 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2435 u16 pci_err;
2436
2437 pci_read_config_word(pdev, PCI_STATUS, &pci_err);
2438 if (net_ratelimit())
2439 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2440 pci_err);
2441
2442 pci_write_config_word(pdev, PCI_STATUS,
2443 pci_err | PCI_STATUS_ERROR_BITS);
2444 }
2445
2446 if (status & Y2_IS_PCI_EXP) {
2447 /* PCI-Express uncorrectable Error occurred */
2448 int pos = pci_find_aer_capability(hw->pdev);
2449 u32 err;
2450
2451 pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_STATUS, &err);
2452 if (net_ratelimit())
2453 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2454 pci_cleanup_aer_uncorrect_error_status(pdev);
2455 }
2456
2457 if (status & Y2_HWE_L1_MASK)
2458 sky2_hw_error(hw, 0, status);
2459 status >>= 8;
2460 if (status & Y2_HWE_L1_MASK)
2461 sky2_hw_error(hw, 1, status);
2462 }
2463
2464 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2465 {
2466 struct net_device *dev = hw->dev[port];
2467 struct sky2_port *sky2 = netdev_priv(dev);
2468 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2469
2470 if (netif_msg_intr(sky2))
2471 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2472 dev->name, status);
2473
2474 if (status & GM_IS_RX_CO_OV)
2475 gma_read16(hw, port, GM_RX_IRQ_SRC);
2476
2477 if (status & GM_IS_TX_CO_OV)
2478 gma_read16(hw, port, GM_TX_IRQ_SRC);
2479
2480 if (status & GM_IS_RX_FF_OR) {
2481 ++dev->stats.rx_fifo_errors;
2482 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2483 }
2484
2485 if (status & GM_IS_TX_FF_UR) {
2486 ++dev->stats.tx_fifo_errors;
2487 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2488 }
2489 }
2490
2491 /* This should never happen it is a bug. */
2492 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2493 u16 q, unsigned ring_size)
2494 {
2495 struct net_device *dev = hw->dev[port];
2496 struct sky2_port *sky2 = netdev_priv(dev);
2497 unsigned idx;
2498 const u64 *le = (q == Q_R1 || q == Q_R2)
2499 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2500
2501 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2502 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2503 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2504 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2505
2506 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2507 }
2508
2509 static int sky2_rx_hung(struct net_device *dev)
2510 {
2511 struct sky2_port *sky2 = netdev_priv(dev);
2512 struct sky2_hw *hw = sky2->hw;
2513 unsigned port = sky2->port;
2514 unsigned rxq = rxqaddr[port];
2515 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2516 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2517 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2518 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2519
2520 /* If idle and MAC or PCI is stuck */
2521 if (sky2->check.last == dev->last_rx &&
2522 ((mac_rp == sky2->check.mac_rp &&
2523 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2524 /* Check if the PCI RX hang */
2525 (fifo_rp == sky2->check.fifo_rp &&
2526 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2527 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2528 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2529 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2530 return 1;
2531 } else {
2532 sky2->check.last = dev->last_rx;
2533 sky2->check.mac_rp = mac_rp;
2534 sky2->check.mac_lev = mac_lev;
2535 sky2->check.fifo_rp = fifo_rp;
2536 sky2->check.fifo_lev = fifo_lev;
2537 return 0;
2538 }
2539 }
2540
2541 static void sky2_watchdog(unsigned long arg)
2542 {
2543 struct sky2_hw *hw = (struct sky2_hw *) arg;
2544
2545 /* Check for lost IRQ once a second */
2546 if (sky2_read32(hw, B0_ISRC)) {
2547 napi_schedule(&hw->napi);
2548 } else {
2549 int i, active = 0;
2550
2551 for (i = 0; i < hw->ports; i++) {
2552 struct net_device *dev = hw->dev[i];
2553 if (!netif_running(dev))
2554 continue;
2555 ++active;
2556
2557 /* For chips with Rx FIFO, check if stuck */
2558 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2559 sky2_rx_hung(dev)) {
2560 pr_info(PFX "%s: receiver hang detected\n",
2561 dev->name);
2562 schedule_work(&hw->restart_work);
2563 return;
2564 }
2565 }
2566
2567 if (active == 0)
2568 return;
2569 }
2570
2571 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2572 }
2573
2574 /* Hardware/software error handling */
2575 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2576 {
2577 if (net_ratelimit())
2578 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2579
2580 if (status & Y2_IS_HW_ERR)
2581 sky2_hw_intr(hw);
2582
2583 if (status & Y2_IS_IRQ_MAC1)
2584 sky2_mac_intr(hw, 0);
2585
2586 if (status & Y2_IS_IRQ_MAC2)
2587 sky2_mac_intr(hw, 1);
2588
2589 if (status & Y2_IS_CHK_RX1)
2590 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2591
2592 if (status & Y2_IS_CHK_RX2)
2593 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2594
2595 if (status & Y2_IS_CHK_TXA1)
2596 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2597
2598 if (status & Y2_IS_CHK_TXA2)
2599 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2600 }
2601
2602 static int sky2_poll(struct napi_struct *napi, int work_limit)
2603 {
2604 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2605 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2606 int work_done = 0;
2607 u16 idx;
2608
2609 if (unlikely(status & Y2_IS_ERROR))
2610 sky2_err_intr(hw, status);
2611
2612 if (status & Y2_IS_IRQ_PHY1)
2613 sky2_phy_intr(hw, 0);
2614
2615 if (status & Y2_IS_IRQ_PHY2)
2616 sky2_phy_intr(hw, 1);
2617
2618 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2619 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2620
2621 if (work_done >= work_limit)
2622 goto done;
2623 }
2624
2625 /* Bug/Errata workaround?
2626 * Need to kick the TX irq moderation timer.
2627 */
2628 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2629 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2630 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2631 }
2632 napi_complete(napi);
2633 sky2_read32(hw, B0_Y2_SP_LISR);
2634 done:
2635
2636 return work_done;
2637 }
2638
2639 static irqreturn_t sky2_intr(int irq, void *dev_id)
2640 {
2641 struct sky2_hw *hw = dev_id;
2642 u32 status;
2643
2644 /* Reading this mask interrupts as side effect */
2645 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2646 if (status == 0 || status == ~0)
2647 return IRQ_NONE;
2648
2649 prefetch(&hw->st_le[hw->st_idx]);
2650
2651 napi_schedule(&hw->napi);
2652
2653 return IRQ_HANDLED;
2654 }
2655
2656 #ifdef CONFIG_NET_POLL_CONTROLLER
2657 static void sky2_netpoll(struct net_device *dev)
2658 {
2659 struct sky2_port *sky2 = netdev_priv(dev);
2660
2661 napi_schedule(&sky2->hw->napi);
2662 }
2663 #endif
2664
2665 /* Chip internal frequency for clock calculations */
2666 static u32 sky2_mhz(const struct sky2_hw *hw)
2667 {
2668 switch (hw->chip_id) {
2669 case CHIP_ID_YUKON_EC:
2670 case CHIP_ID_YUKON_EC_U:
2671 case CHIP_ID_YUKON_EX:
2672 return 125;
2673
2674 case CHIP_ID_YUKON_FE:
2675 return 100;
2676
2677 case CHIP_ID_YUKON_FE_P:
2678 return 50;
2679
2680 case CHIP_ID_YUKON_XL:
2681 return 156;
2682
2683 default:
2684 BUG();
2685 }
2686 }
2687
2688 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2689 {
2690 return sky2_mhz(hw) * us;
2691 }
2692
2693 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2694 {
2695 return clk / sky2_mhz(hw);
2696 }
2697
2698
2699 static int __devinit sky2_init(struct sky2_hw *hw)
2700 {
2701 int rc;
2702 u8 t8;
2703
2704 /* Enable all clocks and check for bad PCI access */
2705 rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
2706 if (rc)
2707 return rc;
2708
2709 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2710
2711 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2712 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2713
2714 switch(hw->chip_id) {
2715 case CHIP_ID_YUKON_XL:
2716 hw->flags = SKY2_HW_GIGABIT
2717 | SKY2_HW_NEWER_PHY;
2718 if (hw->chip_rev < 3)
2719 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2720
2721 break;
2722
2723 case CHIP_ID_YUKON_EC_U:
2724 hw->flags = SKY2_HW_GIGABIT
2725 | SKY2_HW_NEWER_PHY
2726 | SKY2_HW_ADV_POWER_CTL;
2727 break;
2728
2729 case CHIP_ID_YUKON_EX:
2730 hw->flags = SKY2_HW_GIGABIT
2731 | SKY2_HW_NEWER_PHY
2732 | SKY2_HW_NEW_LE
2733 | SKY2_HW_ADV_POWER_CTL;
2734
2735 /* New transmit checksum */
2736 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2737 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2738 break;
2739
2740 case CHIP_ID_YUKON_EC:
2741 /* This rev is really old, and requires untested workarounds */
2742 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2743 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2744 return -EOPNOTSUPP;
2745 }
2746 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2747 break;
2748
2749 case CHIP_ID_YUKON_FE:
2750 break;
2751
2752 case CHIP_ID_YUKON_FE_P:
2753 hw->flags = SKY2_HW_NEWER_PHY
2754 | SKY2_HW_NEW_LE
2755 | SKY2_HW_AUTO_TX_SUM
2756 | SKY2_HW_ADV_POWER_CTL;
2757 break;
2758 default:
2759 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2760 hw->chip_id);
2761 return -EOPNOTSUPP;
2762 }
2763
2764 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2765 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2766 hw->flags |= SKY2_HW_FIBRE_PHY;
2767
2768
2769 hw->ports = 1;
2770 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2771 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2772 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2773 ++hw->ports;
2774 }
2775
2776 return 0;
2777 }
2778
2779 static void sky2_reset(struct sky2_hw *hw)
2780 {
2781 struct pci_dev *pdev = hw->pdev;
2782 u16 status;
2783 int i, cap;
2784 u32 hwe_mask = Y2_HWE_ALL_MASK;
2785
2786 /* disable ASF */
2787 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2788 status = sky2_read16(hw, HCU_CCSR);
2789 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2790 HCU_CCSR_UC_STATE_MSK);
2791 sky2_write16(hw, HCU_CCSR, status);
2792 } else
2793 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2794 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2795
2796 /* do a SW reset */
2797 sky2_write8(hw, B0_CTST, CS_RST_SET);
2798 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2799
2800 /* clear PCI errors, if any */
2801 pci_read_config_word(pdev, PCI_STATUS, &status);
2802 status |= PCI_STATUS_ERROR_BITS;
2803 pci_write_config_word(pdev, PCI_STATUS, status);
2804
2805 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2806
2807 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2808 if (cap) {
2809 /* Check for advanced error reporting */
2810 pci_cleanup_aer_uncorrect_error_status(pdev);
2811 pci_cleanup_aer_correct_error_status(pdev);
2812
2813 /* If error bit is stuck on ignore it */
2814 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2815 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2816
2817 else if (pci_enable_pcie_error_reporting(pdev))
2818 hwe_mask |= Y2_IS_PCI_EXP;
2819 }
2820
2821 sky2_power_on(hw);
2822
2823 for (i = 0; i < hw->ports; i++) {
2824 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2825 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2826
2827 if (hw->chip_id == CHIP_ID_YUKON_EX)
2828 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2829 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2830 | GMC_BYP_RETR_ON);
2831 }
2832
2833 /* Clear I2C IRQ noise */
2834 sky2_write32(hw, B2_I2C_IRQ, 1);
2835
2836 /* turn off hardware timer (unused) */
2837 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2838 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2839
2840 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2841
2842 /* Turn off descriptor polling */
2843 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2844
2845 /* Turn off receive timestamp */
2846 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2847 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2848
2849 /* enable the Tx Arbiters */
2850 for (i = 0; i < hw->ports; i++)
2851 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2852
2853 /* Initialize ram interface */
2854 for (i = 0; i < hw->ports; i++) {
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2856
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2867 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2868 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2869 }
2870
2871 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2872
2873 for (i = 0; i < hw->ports; i++)
2874 sky2_gmac_reset(hw, i);
2875
2876 memset(hw->st_le, 0, STATUS_LE_BYTES);
2877 hw->st_idx = 0;
2878
2879 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2880 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2881
2882 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2883 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2884
2885 /* Set the list last index */
2886 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2887
2888 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2889 sky2_write8(hw, STAT_FIFO_WM, 16);
2890
2891 /* set Status-FIFO ISR watermark */
2892 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2893 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2894 else
2895 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2896
2897 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2898 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2899 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2900
2901 /* enable status unit */
2902 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2903
2904 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2905 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2906 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2907 }
2908
2909 static void sky2_restart(struct work_struct *work)
2910 {
2911 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2912 struct net_device *dev;
2913 int i, err;
2914
2915 rtnl_lock();
2916 sky2_write32(hw, B0_IMSK, 0);
2917 sky2_read32(hw, B0_IMSK);
2918
2919 for (i = 0; i < hw->ports; i++) {
2920 dev = hw->dev[i];
2921 if (netif_running(dev))
2922 sky2_down(dev);
2923 }
2924
2925 sky2_reset(hw);
2926 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2927
2928 for (i = 0; i < hw->ports; i++) {
2929 dev = hw->dev[i];
2930 if (netif_running(dev)) {
2931 err = sky2_up(dev);
2932 if (err) {
2933 printk(KERN_INFO PFX "%s: could not restart %d\n",
2934 dev->name, err);
2935 dev_close(dev);
2936 }
2937 }
2938 }
2939
2940 rtnl_unlock();
2941 }
2942
2943 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2944 {
2945 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2946 }
2947
2948 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2949 {
2950 const struct sky2_port *sky2 = netdev_priv(dev);
2951
2952 wol->supported = sky2_wol_supported(sky2->hw);
2953 wol->wolopts = sky2->wol;
2954 }
2955
2956 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2957 {
2958 struct sky2_port *sky2 = netdev_priv(dev);
2959 struct sky2_hw *hw = sky2->hw;
2960
2961 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2962 return -EOPNOTSUPP;
2963
2964 sky2->wol = wol->wolopts;
2965
2966 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2967 hw->chip_id == CHIP_ID_YUKON_EX ||
2968 hw->chip_id == CHIP_ID_YUKON_FE_P)
2969 sky2_write32(hw, B0_CTST, sky2->wol
2970 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2971
2972 if (!netif_running(dev))
2973 sky2_wol_init(sky2);
2974 return 0;
2975 }
2976
2977 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2978 {
2979 if (sky2_is_copper(hw)) {
2980 u32 modes = SUPPORTED_10baseT_Half
2981 | SUPPORTED_10baseT_Full
2982 | SUPPORTED_100baseT_Half
2983 | SUPPORTED_100baseT_Full
2984 | SUPPORTED_Autoneg | SUPPORTED_TP;
2985
2986 if (hw->flags & SKY2_HW_GIGABIT)
2987 modes |= SUPPORTED_1000baseT_Half
2988 | SUPPORTED_1000baseT_Full;
2989 return modes;
2990 } else
2991 return SUPPORTED_1000baseT_Half
2992 | SUPPORTED_1000baseT_Full
2993 | SUPPORTED_Autoneg
2994 | SUPPORTED_FIBRE;
2995 }
2996
2997 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2998 {
2999 struct sky2_port *sky2 = netdev_priv(dev);
3000 struct sky2_hw *hw = sky2->hw;
3001
3002 ecmd->transceiver = XCVR_INTERNAL;
3003 ecmd->supported = sky2_supported_modes(hw);
3004 ecmd->phy_address = PHY_ADDR_MARV;
3005 if (sky2_is_copper(hw)) {
3006 ecmd->port = PORT_TP;
3007 ecmd->speed = sky2->speed;
3008 } else {
3009 ecmd->speed = SPEED_1000;
3010 ecmd->port = PORT_FIBRE;
3011 }
3012
3013 ecmd->advertising = sky2->advertising;
3014 ecmd->autoneg = sky2->autoneg;
3015 ecmd->duplex = sky2->duplex;
3016 return 0;
3017 }
3018
3019 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3020 {
3021 struct sky2_port *sky2 = netdev_priv(dev);
3022 const struct sky2_hw *hw = sky2->hw;
3023 u32 supported = sky2_supported_modes(hw);
3024
3025 if (ecmd->autoneg == AUTONEG_ENABLE) {
3026 ecmd->advertising = supported;
3027 sky2->duplex = -1;
3028 sky2->speed = -1;
3029 } else {
3030 u32 setting;
3031
3032 switch (ecmd->speed) {
3033 case SPEED_1000:
3034 if (ecmd->duplex == DUPLEX_FULL)
3035 setting = SUPPORTED_1000baseT_Full;
3036 else if (ecmd->duplex == DUPLEX_HALF)
3037 setting = SUPPORTED_1000baseT_Half;
3038 else
3039 return -EINVAL;
3040 break;
3041 case SPEED_100:
3042 if (ecmd->duplex == DUPLEX_FULL)
3043 setting = SUPPORTED_100baseT_Full;
3044 else if (ecmd->duplex == DUPLEX_HALF)
3045 setting = SUPPORTED_100baseT_Half;
3046 else
3047 return -EINVAL;
3048 break;
3049
3050 case SPEED_10:
3051 if (ecmd->duplex == DUPLEX_FULL)
3052 setting = SUPPORTED_10baseT_Full;
3053 else if (ecmd->duplex == DUPLEX_HALF)
3054 setting = SUPPORTED_10baseT_Half;
3055 else
3056 return -EINVAL;
3057 break;
3058 default:
3059 return -EINVAL;
3060 }
3061
3062 if ((setting & supported) == 0)
3063 return -EINVAL;
3064
3065 sky2->speed = ecmd->speed;
3066 sky2->duplex = ecmd->duplex;
3067 }
3068
3069 sky2->autoneg = ecmd->autoneg;
3070 sky2->advertising = ecmd->advertising;
3071
3072 if (netif_running(dev)) {
3073 sky2_phy_reinit(sky2);
3074 sky2_set_multicast(dev);
3075 }
3076
3077 return 0;
3078 }
3079
3080 static void sky2_get_drvinfo(struct net_device *dev,
3081 struct ethtool_drvinfo *info)
3082 {
3083 struct sky2_port *sky2 = netdev_priv(dev);
3084
3085 strcpy(info->driver, DRV_NAME);
3086 strcpy(info->version, DRV_VERSION);
3087 strcpy(info->fw_version, "N/A");
3088 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3089 }
3090
3091 static const struct sky2_stat {
3092 char name[ETH_GSTRING_LEN];
3093 u16 offset;
3094 } sky2_stats[] = {
3095 { "tx_bytes", GM_TXO_OK_HI },
3096 { "rx_bytes", GM_RXO_OK_HI },
3097 { "tx_broadcast", GM_TXF_BC_OK },
3098 { "rx_broadcast", GM_RXF_BC_OK },
3099 { "tx_multicast", GM_TXF_MC_OK },
3100 { "rx_multicast", GM_RXF_MC_OK },
3101 { "tx_unicast", GM_TXF_UC_OK },
3102 { "rx_unicast", GM_RXF_UC_OK },
3103 { "tx_mac_pause", GM_TXF_MPAUSE },
3104 { "rx_mac_pause", GM_RXF_MPAUSE },
3105 { "collisions", GM_TXF_COL },
3106 { "late_collision",GM_TXF_LAT_COL },
3107 { "aborted", GM_TXF_ABO_COL },
3108 { "single_collisions", GM_TXF_SNG_COL },
3109 { "multi_collisions", GM_TXF_MUL_COL },
3110
3111 { "rx_short", GM_RXF_SHT },
3112 { "rx_runt", GM_RXE_FRAG },
3113 { "rx_64_byte_packets", GM_RXF_64B },
3114 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3115 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3116 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3117 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3118 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3119 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3120 { "rx_too_long", GM_RXF_LNG_ERR },
3121 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3122 { "rx_jabber", GM_RXF_JAB_PKT },
3123 { "rx_fcs_error", GM_RXF_FCS_ERR },
3124
3125 { "tx_64_byte_packets", GM_TXF_64B },
3126 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3127 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3128 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3129 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3130 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3131 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3132 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3133 };
3134
3135 static u32 sky2_get_rx_csum(struct net_device *dev)
3136 {
3137 struct sky2_port *sky2 = netdev_priv(dev);
3138
3139 return sky2->rx_csum;
3140 }
3141
3142 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3143 {
3144 struct sky2_port *sky2 = netdev_priv(dev);
3145
3146 sky2->rx_csum = data;
3147
3148 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3149 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3150
3151 return 0;
3152 }
3153
3154 static u32 sky2_get_msglevel(struct net_device *netdev)
3155 {
3156 struct sky2_port *sky2 = netdev_priv(netdev);
3157 return sky2->msg_enable;
3158 }
3159
3160 static int sky2_nway_reset(struct net_device *dev)
3161 {
3162 struct sky2_port *sky2 = netdev_priv(dev);
3163
3164 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3165 return -EINVAL;
3166
3167 sky2_phy_reinit(sky2);
3168 sky2_set_multicast(dev);
3169
3170 return 0;
3171 }
3172
3173 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3174 {
3175 struct sky2_hw *hw = sky2->hw;
3176 unsigned port = sky2->port;
3177 int i;
3178
3179 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3180 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3181 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3182 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3183
3184 for (i = 2; i < count; i++)
3185 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3186 }
3187
3188 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3189 {
3190 struct sky2_port *sky2 = netdev_priv(netdev);
3191 sky2->msg_enable = value;
3192 }
3193
3194 static int sky2_get_sset_count(struct net_device *dev, int sset)
3195 {
3196 switch (sset) {
3197 case ETH_SS_STATS:
3198 return ARRAY_SIZE(sky2_stats);
3199 default:
3200 return -EOPNOTSUPP;
3201 }
3202 }
3203
3204 static void sky2_get_ethtool_stats(struct net_device *dev,
3205 struct ethtool_stats *stats, u64 * data)
3206 {
3207 struct sky2_port *sky2 = netdev_priv(dev);
3208
3209 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3210 }
3211
3212 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3213 {
3214 int i;
3215
3216 switch (stringset) {
3217 case ETH_SS_STATS:
3218 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3219 memcpy(data + i * ETH_GSTRING_LEN,
3220 sky2_stats[i].name, ETH_GSTRING_LEN);
3221 break;
3222 }
3223 }
3224
3225 static int sky2_set_mac_address(struct net_device *dev, void *p)
3226 {
3227 struct sky2_port *sky2 = netdev_priv(dev);
3228 struct sky2_hw *hw = sky2->hw;
3229 unsigned port = sky2->port;
3230 const struct sockaddr *addr = p;
3231
3232 if (!is_valid_ether_addr(addr->sa_data))
3233 return -EADDRNOTAVAIL;
3234
3235 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3236 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3237 dev->dev_addr, ETH_ALEN);
3238 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3239 dev->dev_addr, ETH_ALEN);
3240
3241 /* virtual address for data */
3242 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3243
3244 /* physical address: used for pause frames */
3245 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3246
3247 return 0;
3248 }
3249
3250 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3251 {
3252 u32 bit;
3253
3254 bit = ether_crc(ETH_ALEN, addr) & 63;
3255 filter[bit >> 3] |= 1 << (bit & 7);
3256 }
3257
3258 static void sky2_set_multicast(struct net_device *dev)
3259 {
3260 struct sky2_port *sky2 = netdev_priv(dev);
3261 struct sky2_hw *hw = sky2->hw;
3262 unsigned port = sky2->port;
3263 struct dev_mc_list *list = dev->mc_list;
3264 u16 reg;
3265 u8 filter[8];
3266 int rx_pause;
3267 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3268
3269 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3270 memset(filter, 0, sizeof(filter));
3271
3272 reg = gma_read16(hw, port, GM_RX_CTRL);
3273 reg |= GM_RXCR_UCF_ENA;
3274
3275 if (dev->flags & IFF_PROMISC) /* promiscuous */
3276 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3277 else if (dev->flags & IFF_ALLMULTI)
3278 memset(filter, 0xff, sizeof(filter));
3279 else if (dev->mc_count == 0 && !rx_pause)
3280 reg &= ~GM_RXCR_MCF_ENA;
3281 else {
3282 int i;
3283 reg |= GM_RXCR_MCF_ENA;
3284
3285 if (rx_pause)
3286 sky2_add_filter(filter, pause_mc_addr);
3287
3288 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3289 sky2_add_filter(filter, list->dmi_addr);
3290 }
3291
3292 gma_write16(hw, port, GM_MC_ADDR_H1,
3293 (u16) filter[0] | ((u16) filter[1] << 8));
3294 gma_write16(hw, port, GM_MC_ADDR_H2,
3295 (u16) filter[2] | ((u16) filter[3] << 8));
3296 gma_write16(hw, port, GM_MC_ADDR_H3,
3297 (u16) filter[4] | ((u16) filter[5] << 8));
3298 gma_write16(hw, port, GM_MC_ADDR_H4,
3299 (u16) filter[6] | ((u16) filter[7] << 8));
3300
3301 gma_write16(hw, port, GM_RX_CTRL, reg);
3302 }
3303
3304 /* Can have one global because blinking is controlled by
3305 * ethtool and that is always under RTNL mutex
3306 */
3307 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3308 {
3309 u16 pg;
3310
3311 switch (hw->chip_id) {
3312 case CHIP_ID_YUKON_XL:
3313 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3314 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3315 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3316 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3317 PHY_M_LEDC_INIT_CTRL(7) |
3318 PHY_M_LEDC_STA1_CTRL(7) |
3319 PHY_M_LEDC_STA0_CTRL(7))
3320 : 0);
3321
3322 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3323 break;
3324
3325 default:
3326 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3327 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3328 on ? PHY_M_LED_ALL : 0);
3329 }
3330 }
3331
3332 /* blink LED's for finding board */
3333 static int sky2_phys_id(struct net_device *dev, u32 data)
3334 {
3335 struct sky2_port *sky2 = netdev_priv(dev);
3336 struct sky2_hw *hw = sky2->hw;
3337 unsigned port = sky2->port;
3338 u16 ledctrl, ledover = 0;
3339 long ms;
3340 int interrupted;
3341 int onoff = 1;
3342
3343 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3344 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3345 else
3346 ms = data * 1000;
3347
3348 /* save initial values */
3349 spin_lock_bh(&sky2->phy_lock);
3350 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3351 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3353 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3355 } else {
3356 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3357 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3358 }
3359
3360 interrupted = 0;
3361 while (!interrupted && ms > 0) {
3362 sky2_led(hw, port, onoff);
3363 onoff = !onoff;
3364
3365 spin_unlock_bh(&sky2->phy_lock);
3366 interrupted = msleep_interruptible(250);
3367 spin_lock_bh(&sky2->phy_lock);
3368
3369 ms -= 250;
3370 }
3371
3372 /* resume regularly scheduled programming */
3373 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3374 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3375 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3376 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3377 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3378 } else {
3379 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3380 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3381 }
3382 spin_unlock_bh(&sky2->phy_lock);
3383
3384 return 0;
3385 }
3386
3387 static void sky2_get_pauseparam(struct net_device *dev,
3388 struct ethtool_pauseparam *ecmd)
3389 {
3390 struct sky2_port *sky2 = netdev_priv(dev);
3391
3392 switch (sky2->flow_mode) {
3393 case FC_NONE:
3394 ecmd->tx_pause = ecmd->rx_pause = 0;
3395 break;
3396 case FC_TX:
3397 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3398 break;
3399 case FC_RX:
3400 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3401 break;
3402 case FC_BOTH:
3403 ecmd->tx_pause = ecmd->rx_pause = 1;
3404 }
3405
3406 ecmd->autoneg = sky2->autoneg;
3407 }
3408
3409 static int sky2_set_pauseparam(struct net_device *dev,
3410 struct ethtool_pauseparam *ecmd)
3411 {
3412 struct sky2_port *sky2 = netdev_priv(dev);
3413
3414 sky2->autoneg = ecmd->autoneg;
3415 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3416
3417 if (netif_running(dev))
3418 sky2_phy_reinit(sky2);
3419
3420 return 0;
3421 }
3422
3423 static int sky2_get_coalesce(struct net_device *dev,
3424 struct ethtool_coalesce *ecmd)
3425 {
3426 struct sky2_port *sky2 = netdev_priv(dev);
3427 struct sky2_hw *hw = sky2->hw;
3428
3429 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3430 ecmd->tx_coalesce_usecs = 0;
3431 else {
3432 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3433 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3434 }
3435 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3436
3437 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3438 ecmd->rx_coalesce_usecs = 0;
3439 else {
3440 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3441 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3442 }
3443 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3444
3445 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3446 ecmd->rx_coalesce_usecs_irq = 0;
3447 else {
3448 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3449 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3450 }
3451
3452 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3453
3454 return 0;
3455 }
3456
3457 /* Note: this affect both ports */
3458 static int sky2_set_coalesce(struct net_device *dev,
3459 struct ethtool_coalesce *ecmd)
3460 {
3461 struct sky2_port *sky2 = netdev_priv(dev);
3462 struct sky2_hw *hw = sky2->hw;
3463 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3464
3465 if (ecmd->tx_coalesce_usecs > tmax ||
3466 ecmd->rx_coalesce_usecs > tmax ||
3467 ecmd->rx_coalesce_usecs_irq > tmax)
3468 return -EINVAL;
3469
3470 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3471 return -EINVAL;
3472 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3473 return -EINVAL;
3474 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3475 return -EINVAL;
3476
3477 if (ecmd->tx_coalesce_usecs == 0)
3478 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3479 else {
3480 sky2_write32(hw, STAT_TX_TIMER_INI,
3481 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3482 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3483 }
3484 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3485
3486 if (ecmd->rx_coalesce_usecs == 0)
3487 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3488 else {
3489 sky2_write32(hw, STAT_LEV_TIMER_INI,
3490 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3491 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3492 }
3493 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3494
3495 if (ecmd->rx_coalesce_usecs_irq == 0)
3496 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3497 else {
3498 sky2_write32(hw, STAT_ISR_TIMER_INI,
3499 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3500 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3501 }
3502 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3503 return 0;
3504 }
3505
3506 static void sky2_get_ringparam(struct net_device *dev,
3507 struct ethtool_ringparam *ering)
3508 {
3509 struct sky2_port *sky2 = netdev_priv(dev);
3510
3511 ering->rx_max_pending = RX_MAX_PENDING;
3512 ering->rx_mini_max_pending = 0;
3513 ering->rx_jumbo_max_pending = 0;
3514 ering->tx_max_pending = TX_RING_SIZE - 1;
3515
3516 ering->rx_pending = sky2->rx_pending;
3517 ering->rx_mini_pending = 0;
3518 ering->rx_jumbo_pending = 0;
3519 ering->tx_pending = sky2->tx_pending;
3520 }
3521
3522 static int sky2_set_ringparam(struct net_device *dev,
3523 struct ethtool_ringparam *ering)
3524 {
3525 struct sky2_port *sky2 = netdev_priv(dev);
3526 int err = 0;
3527
3528 if (ering->rx_pending > RX_MAX_PENDING ||
3529 ering->rx_pending < 8 ||
3530 ering->tx_pending < MAX_SKB_TX_LE ||
3531 ering->tx_pending > TX_RING_SIZE - 1)
3532 return -EINVAL;
3533
3534 if (netif_running(dev))
3535 sky2_down(dev);
3536
3537 sky2->rx_pending = ering->rx_pending;
3538 sky2->tx_pending = ering->tx_pending;
3539
3540 if (netif_running(dev)) {
3541 err = sky2_up(dev);
3542 if (err)
3543 dev_close(dev);
3544 else
3545 sky2_set_multicast(dev);
3546 }
3547
3548 return err;
3549 }
3550
3551 static int sky2_get_regs_len(struct net_device *dev)
3552 {
3553 return 0x4000;
3554 }
3555
3556 /*
3557 * Returns copy of control register region
3558 * Note: ethtool_get_regs always provides full size (16k) buffer
3559 */
3560 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3561 void *p)
3562 {
3563 const struct sky2_port *sky2 = netdev_priv(dev);
3564 const void __iomem *io = sky2->hw->regs;
3565 unsigned int b;
3566
3567 regs->version = 1;
3568
3569 for (b = 0; b < 128; b++) {
3570 /* This complicated switch statement is to make sure and
3571 * only access regions that are unreserved.
3572 * Some blocks are only valid on dual port cards.
3573 * and block 3 has some special diagnostic registers that
3574 * are poison.
3575 */
3576 switch (b) {
3577 case 3:
3578 /* skip diagnostic ram region */
3579 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3580 break;
3581
3582 /* dual port cards only */
3583 case 5: /* Tx Arbiter 2 */
3584 case 9: /* RX2 */
3585 case 14 ... 15: /* TX2 */
3586 case 17: case 19: /* Ram Buffer 2 */
3587 case 22 ... 23: /* Tx Ram Buffer 2 */
3588 case 25: /* Rx MAC Fifo 1 */
3589 case 27: /* Tx MAC Fifo 2 */
3590 case 31: /* GPHY 2 */
3591 case 40 ... 47: /* Pattern Ram 2 */
3592 case 52: case 54: /* TCP Segmentation 2 */
3593 case 112 ... 116: /* GMAC 2 */
3594 if (sky2->hw->ports == 1)
3595 goto reserved;
3596 /* fall through */
3597 case 0: /* Control */
3598 case 2: /* Mac address */
3599 case 4: /* Tx Arbiter 1 */
3600 case 7: /* PCI express reg */
3601 case 8: /* RX1 */
3602 case 12 ... 13: /* TX1 */
3603 case 16: case 18:/* Rx Ram Buffer 1 */
3604 case 20 ... 21: /* Tx Ram Buffer 1 */
3605 case 24: /* Rx MAC Fifo 1 */
3606 case 26: /* Tx MAC Fifo 1 */
3607 case 28 ... 29: /* Descriptor and status unit */
3608 case 30: /* GPHY 1*/
3609 case 32 ... 39: /* Pattern Ram 1 */
3610 case 48: case 50: /* TCP Segmentation 1 */
3611 case 56 ... 60: /* PCI space */
3612 case 80 ... 84: /* GMAC 1 */
3613 memcpy_fromio(p, io, 128);
3614 break;
3615 default:
3616 reserved:
3617 memset(p, 0, 128);
3618 }
3619
3620 p += 128;
3621 io += 128;
3622 }
3623 }
3624
3625 /* In order to do Jumbo packets on these chips, need to turn off the
3626 * transmit store/forward. Therefore checksum offload won't work.
3627 */
3628 static int no_tx_offload(struct net_device *dev)
3629 {
3630 const struct sky2_port *sky2 = netdev_priv(dev);
3631 const struct sky2_hw *hw = sky2->hw;
3632
3633 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3634 }
3635
3636 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3637 {
3638 if (data && no_tx_offload(dev))
3639 return -EINVAL;
3640
3641 return ethtool_op_set_tx_csum(dev, data);
3642 }
3643
3644
3645 static int sky2_set_tso(struct net_device *dev, u32 data)
3646 {
3647 if (data && no_tx_offload(dev))
3648 return -EINVAL;
3649
3650 return ethtool_op_set_tso(dev, data);
3651 }
3652
3653 static int sky2_get_eeprom_len(struct net_device *dev)
3654 {
3655 struct sky2_port *sky2 = netdev_priv(dev);
3656 u16 reg2;
3657
3658 pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, &reg2);
3659 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3660 }
3661
3662 static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
3663 {
3664 u32 val;
3665
3666 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
3667
3668 do {
3669 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3670 } while (!(offset & PCI_VPD_ADDR_F));
3671
3672 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
3673 return val;
3674 }
3675
3676 static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
3677 {
3678 pci_write_config_word(pdev, cap + PCI_VPD_DATA, val);
3679 pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3680 do {
3681 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3682 } while (offset & PCI_VPD_ADDR_F);
3683 }
3684
3685 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3686 u8 *data)
3687 {
3688 struct sky2_port *sky2 = netdev_priv(dev);
3689 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3690 int length = eeprom->len;
3691 u16 offset = eeprom->offset;
3692
3693 if (!cap)
3694 return -EINVAL;
3695
3696 eeprom->magic = SKY2_EEPROM_MAGIC;
3697
3698 while (length > 0) {
3699 u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3700 int n = min_t(int, length, sizeof(val));
3701
3702 memcpy(data, &val, n);
3703 length -= n;
3704 data += n;
3705 offset += n;
3706 }
3707 return 0;
3708 }
3709
3710 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3711 u8 *data)
3712 {
3713 struct sky2_port *sky2 = netdev_priv(dev);
3714 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3715 int length = eeprom->len;
3716 u16 offset = eeprom->offset;
3717
3718 if (!cap)
3719 return -EINVAL;
3720
3721 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3722 return -EINVAL;
3723
3724 while (length > 0) {
3725 u32 val;
3726 int n = min_t(int, length, sizeof(val));
3727
3728 if (n < sizeof(val))
3729 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3730 memcpy(&val, data, n);
3731
3732 sky2_vpd_write(sky2->hw->pdev, cap, offset, val);
3733
3734 length -= n;
3735 data += n;
3736 offset += n;
3737 }
3738 return 0;
3739 }
3740
3741
3742 static const struct ethtool_ops sky2_ethtool_ops = {
3743 .get_settings = sky2_get_settings,
3744 .set_settings = sky2_set_settings,
3745 .get_drvinfo = sky2_get_drvinfo,
3746 .get_wol = sky2_get_wol,
3747 .set_wol = sky2_set_wol,
3748 .get_msglevel = sky2_get_msglevel,
3749 .set_msglevel = sky2_set_msglevel,
3750 .nway_reset = sky2_nway_reset,
3751 .get_regs_len = sky2_get_regs_len,
3752 .get_regs = sky2_get_regs,
3753 .get_link = ethtool_op_get_link,
3754 .get_eeprom_len = sky2_get_eeprom_len,
3755 .get_eeprom = sky2_get_eeprom,
3756 .set_eeprom = sky2_set_eeprom,
3757 .set_sg = ethtool_op_set_sg,
3758 .set_tx_csum = sky2_set_tx_csum,
3759 .set_tso = sky2_set_tso,
3760 .get_rx_csum = sky2_get_rx_csum,
3761 .set_rx_csum = sky2_set_rx_csum,
3762 .get_strings = sky2_get_strings,
3763 .get_coalesce = sky2_get_coalesce,
3764 .set_coalesce = sky2_set_coalesce,
3765 .get_ringparam = sky2_get_ringparam,
3766 .set_ringparam = sky2_set_ringparam,
3767 .get_pauseparam = sky2_get_pauseparam,
3768 .set_pauseparam = sky2_set_pauseparam,
3769 .phys_id = sky2_phys_id,
3770 .get_sset_count = sky2_get_sset_count,
3771 .get_ethtool_stats = sky2_get_ethtool_stats,
3772 };
3773
3774 #ifdef CONFIG_SKY2_DEBUG
3775
3776 static struct dentry *sky2_debug;
3777
3778 static int sky2_debug_show(struct seq_file *seq, void *v)
3779 {
3780 struct net_device *dev = seq->private;
3781 const struct sky2_port *sky2 = netdev_priv(dev);
3782 struct sky2_hw *hw = sky2->hw;
3783 unsigned port = sky2->port;
3784 unsigned idx, last;
3785 int sop;
3786
3787 if (!netif_running(dev))
3788 return -ENETDOWN;
3789
3790 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3791 sky2_read32(hw, B0_ISRC),
3792 sky2_read32(hw, B0_IMSK),
3793 sky2_read32(hw, B0_Y2_SP_ICR));
3794
3795 napi_disable(&hw->napi);
3796 last = sky2_read16(hw, STAT_PUT_IDX);
3797
3798 if (hw->st_idx == last)
3799 seq_puts(seq, "Status ring (empty)\n");
3800 else {
3801 seq_puts(seq, "Status ring\n");
3802 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3803 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3804 const struct sky2_status_le *le = hw->st_le + idx;
3805 seq_printf(seq, "[%d] %#x %d %#x\n",
3806 idx, le->opcode, le->length, le->status);
3807 }
3808 seq_puts(seq, "\n");
3809 }
3810
3811 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3812 sky2->tx_cons, sky2->tx_prod,
3813 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3814 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3815
3816 /* Dump contents of tx ring */
3817 sop = 1;
3818 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3819 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3820 const struct sky2_tx_le *le = sky2->tx_le + idx;
3821 u32 a = le32_to_cpu(le->addr);
3822
3823 if (sop)
3824 seq_printf(seq, "%u:", idx);
3825 sop = 0;
3826
3827 switch(le->opcode & ~HW_OWNER) {
3828 case OP_ADDR64:
3829 seq_printf(seq, " %#x:", a);
3830 break;
3831 case OP_LRGLEN:
3832 seq_printf(seq, " mtu=%d", a);
3833 break;
3834 case OP_VLAN:
3835 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3836 break;
3837 case OP_TCPLISW:
3838 seq_printf(seq, " csum=%#x", a);
3839 break;
3840 case OP_LARGESEND:
3841 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3842 break;
3843 case OP_PACKET:
3844 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3845 break;
3846 case OP_BUFFER:
3847 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3848 break;
3849 default:
3850 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3851 a, le16_to_cpu(le->length));
3852 }
3853
3854 if (le->ctrl & EOP) {
3855 seq_putc(seq, '\n');
3856 sop = 1;
3857 }
3858 }
3859
3860 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3861 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3862 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3863 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3864
3865 napi_enable(&hw->napi);
3866 return 0;
3867 }
3868
3869 static int sky2_debug_open(struct inode *inode, struct file *file)
3870 {
3871 return single_open(file, sky2_debug_show, inode->i_private);
3872 }
3873
3874 static const struct file_operations sky2_debug_fops = {
3875 .owner = THIS_MODULE,
3876 .open = sky2_debug_open,
3877 .read = seq_read,
3878 .llseek = seq_lseek,
3879 .release = single_release,
3880 };
3881
3882 /*
3883 * Use network device events to create/remove/rename
3884 * debugfs file entries
3885 */
3886 static int sky2_device_event(struct notifier_block *unused,
3887 unsigned long event, void *ptr)
3888 {
3889 struct net_device *dev = ptr;
3890 struct sky2_port *sky2 = netdev_priv(dev);
3891
3892 if (dev->open != sky2_up || !sky2_debug)
3893 return NOTIFY_DONE;
3894
3895 switch(event) {
3896 case NETDEV_CHANGENAME:
3897 if (sky2->debugfs) {
3898 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3899 sky2_debug, dev->name);
3900 }
3901 break;
3902
3903 case NETDEV_GOING_DOWN:
3904 if (sky2->debugfs) {
3905 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3906 dev->name);
3907 debugfs_remove(sky2->debugfs);
3908 sky2->debugfs = NULL;
3909 }
3910 break;
3911
3912 case NETDEV_UP:
3913 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3914 sky2_debug, dev,
3915 &sky2_debug_fops);
3916 if (IS_ERR(sky2->debugfs))
3917 sky2->debugfs = NULL;
3918 }
3919
3920 return NOTIFY_DONE;
3921 }
3922
3923 static struct notifier_block sky2_notifier = {
3924 .notifier_call = sky2_device_event,
3925 };
3926
3927
3928 static __init void sky2_debug_init(void)
3929 {
3930 struct dentry *ent;
3931
3932 ent = debugfs_create_dir("sky2", NULL);
3933 if (!ent || IS_ERR(ent))
3934 return;
3935
3936 sky2_debug = ent;
3937 register_netdevice_notifier(&sky2_notifier);
3938 }
3939
3940 static __exit void sky2_debug_cleanup(void)
3941 {
3942 if (sky2_debug) {
3943 unregister_netdevice_notifier(&sky2_notifier);
3944 debugfs_remove(sky2_debug);
3945 sky2_debug = NULL;
3946 }
3947 }
3948
3949 #else
3950 #define sky2_debug_init()
3951 #define sky2_debug_cleanup()
3952 #endif
3953
3954
3955 /* Initialize network device */
3956 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3957 unsigned port,
3958 int highmem, int wol)
3959 {
3960 struct sky2_port *sky2;
3961 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3962
3963 if (!dev) {
3964 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3965 return NULL;
3966 }
3967
3968 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3969 dev->irq = hw->pdev->irq;
3970 dev->open = sky2_up;
3971 dev->stop = sky2_down;
3972 dev->do_ioctl = sky2_ioctl;
3973 dev->hard_start_xmit = sky2_xmit_frame;
3974 dev->set_multicast_list = sky2_set_multicast;
3975 dev->set_mac_address = sky2_set_mac_address;
3976 dev->change_mtu = sky2_change_mtu;
3977 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3978 dev->tx_timeout = sky2_tx_timeout;
3979 dev->watchdog_timeo = TX_WATCHDOG;
3980 #ifdef CONFIG_NET_POLL_CONTROLLER
3981 dev->poll_controller = sky2_netpoll;
3982 #endif
3983
3984 sky2 = netdev_priv(dev);
3985 sky2->netdev = dev;
3986 sky2->hw = hw;
3987 sky2->msg_enable = netif_msg_init(debug, default_msg);
3988
3989 /* Auto speed and flow control */
3990 sky2->autoneg = AUTONEG_ENABLE;
3991 sky2->flow_mode = FC_BOTH;
3992
3993 sky2->duplex = -1;
3994 sky2->speed = -1;
3995 sky2->advertising = sky2_supported_modes(hw);
3996 sky2->rx_csum = 1;
3997 sky2->wol = wol;
3998
3999 spin_lock_init(&sky2->phy_lock);
4000 sky2->tx_pending = TX_DEF_PENDING;
4001 sky2->rx_pending = RX_DEF_PENDING;
4002
4003 hw->dev[port] = dev;
4004
4005 sky2->port = port;
4006
4007 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4008 if (highmem)
4009 dev->features |= NETIF_F_HIGHDMA;
4010
4011 #ifdef SKY2_VLAN_TAG_USED
4012 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4013 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4014 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4015 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4016 dev->vlan_rx_register = sky2_vlan_rx_register;
4017 }
4018 #endif
4019
4020 /* read the mac address */
4021 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4022 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4023
4024 return dev;
4025 }
4026
4027 static void __devinit sky2_show_addr(struct net_device *dev)
4028 {
4029 const struct sky2_port *sky2 = netdev_priv(dev);
4030 DECLARE_MAC_BUF(mac);
4031
4032 if (netif_msg_probe(sky2))
4033 printk(KERN_INFO PFX "%s: addr %s\n",
4034 dev->name, print_mac(mac, dev->dev_addr));
4035 }
4036
4037 /* Handle software interrupt used during MSI test */
4038 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4039 {
4040 struct sky2_hw *hw = dev_id;
4041 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4042
4043 if (status == 0)
4044 return IRQ_NONE;
4045
4046 if (status & Y2_IS_IRQ_SW) {
4047 hw->flags |= SKY2_HW_USE_MSI;
4048 wake_up(&hw->msi_wait);
4049 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4050 }
4051 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4052
4053 return IRQ_HANDLED;
4054 }
4055
4056 /* Test interrupt path by forcing a a software IRQ */
4057 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4058 {
4059 struct pci_dev *pdev = hw->pdev;
4060 int err;
4061
4062 init_waitqueue_head (&hw->msi_wait);
4063
4064 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4065
4066 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4067 if (err) {
4068 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4069 return err;
4070 }
4071
4072 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4073 sky2_read8(hw, B0_CTST);
4074
4075 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4076
4077 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4078 /* MSI test failed, go back to INTx mode */
4079 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4080 "switching to INTx mode.\n");
4081
4082 err = -EOPNOTSUPP;
4083 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4084 }
4085
4086 sky2_write32(hw, B0_IMSK, 0);
4087 sky2_read32(hw, B0_IMSK);
4088
4089 free_irq(pdev->irq, hw);
4090
4091 return err;
4092 }
4093
4094 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4095 {
4096 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4097 u16 value;
4098
4099 if (!pm)
4100 return 0;
4101 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4102 return 0;
4103 return value & PCI_PM_CTRL_PME_ENABLE;
4104 }
4105
4106 static int __devinit sky2_probe(struct pci_dev *pdev,
4107 const struct pci_device_id *ent)
4108 {
4109 struct net_device *dev;
4110 struct sky2_hw *hw;
4111 int err, using_dac = 0, wol_default;
4112
4113 err = pci_enable_device(pdev);
4114 if (err) {
4115 dev_err(&pdev->dev, "cannot enable PCI device\n");
4116 goto err_out;
4117 }
4118
4119 err = pci_request_regions(pdev, DRV_NAME);
4120 if (err) {
4121 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4122 goto err_out_disable;
4123 }
4124
4125 pci_set_master(pdev);
4126
4127 if (sizeof(dma_addr_t) > sizeof(u32) &&
4128 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4129 using_dac = 1;
4130 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4131 if (err < 0) {
4132 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4133 "for consistent allocations\n");
4134 goto err_out_free_regions;
4135 }
4136 } else {
4137 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4138 if (err) {
4139 dev_err(&pdev->dev, "no usable DMA configuration\n");
4140 goto err_out_free_regions;
4141 }
4142 }
4143
4144 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4145
4146 err = -ENOMEM;
4147 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4148 if (!hw) {
4149 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4150 goto err_out_free_regions;
4151 }
4152
4153 hw->pdev = pdev;
4154
4155 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4156 if (!hw->regs) {
4157 dev_err(&pdev->dev, "cannot map device registers\n");
4158 goto err_out_free_hw;
4159 }
4160
4161 #ifdef __BIG_ENDIAN
4162 /* The sk98lin vendor driver uses hardware byte swapping but
4163 * this driver uses software swapping.
4164 */
4165 {
4166 u32 reg;
4167 pci_read_config_dword(pdev,PCI_DEV_REG2, &reg);
4168 reg &= ~PCI_REV_DESC;
4169 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4170 }
4171 #endif
4172
4173 /* ring for status responses */
4174 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4175 if (!hw->st_le)
4176 goto err_out_iounmap;
4177
4178 err = sky2_init(hw);
4179 if (err)
4180 goto err_out_iounmap;
4181
4182 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4183 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4184 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4185 hw->chip_id, hw->chip_rev);
4186
4187 sky2_reset(hw);
4188
4189 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4190 if (!dev) {
4191 err = -ENOMEM;
4192 goto err_out_free_pci;
4193 }
4194 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4195
4196 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4197 err = sky2_test_msi(hw);
4198 if (err == -EOPNOTSUPP)
4199 pci_disable_msi(pdev);
4200 else if (err)
4201 goto err_out_free_netdev;
4202 }
4203
4204 err = register_netdev(dev);
4205 if (err) {
4206 dev_err(&pdev->dev, "cannot register net device\n");
4207 goto err_out_free_netdev;
4208 }
4209
4210 err = request_irq(pdev->irq, sky2_intr,
4211 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4212 dev->name, hw);
4213 if (err) {
4214 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4215 goto err_out_unregister;
4216 }
4217 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4218
4219 sky2_show_addr(dev);
4220
4221 if (hw->ports > 1) {
4222 struct net_device *dev1;
4223
4224 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4225 if (!dev1)
4226 dev_warn(&pdev->dev, "allocation for second device failed\n");
4227 else if ((err = register_netdev(dev1))) {
4228 dev_warn(&pdev->dev,
4229 "register of second port failed (%d)\n", err);
4230 hw->dev[1] = NULL;
4231 free_netdev(dev1);
4232 } else
4233 sky2_show_addr(dev1);
4234 }
4235
4236 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4237 INIT_WORK(&hw->restart_work, sky2_restart);
4238
4239 pci_set_drvdata(pdev, hw);
4240
4241 return 0;
4242
4243 err_out_unregister:
4244 if (hw->flags & SKY2_HW_USE_MSI)
4245 pci_disable_msi(pdev);
4246 unregister_netdev(dev);
4247 err_out_free_netdev:
4248 free_netdev(dev);
4249 err_out_free_pci:
4250 sky2_write8(hw, B0_CTST, CS_RST_SET);
4251 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4252 err_out_iounmap:
4253 iounmap(hw->regs);
4254 err_out_free_hw:
4255 kfree(hw);
4256 err_out_free_regions:
4257 pci_release_regions(pdev);
4258 err_out_disable:
4259 pci_disable_device(pdev);
4260 err_out:
4261 pci_set_drvdata(pdev, NULL);
4262 return err;
4263 }
4264
4265 static void __devexit sky2_remove(struct pci_dev *pdev)
4266 {
4267 struct sky2_hw *hw = pci_get_drvdata(pdev);
4268 struct net_device *dev0, *dev1;
4269
4270 if (!hw)
4271 return;
4272
4273 del_timer_sync(&hw->watchdog_timer);
4274
4275 flush_scheduled_work();
4276
4277 sky2_write32(hw, B0_IMSK, 0);
4278 synchronize_irq(hw->pdev->irq);
4279
4280 dev0 = hw->dev[0];
4281 dev1 = hw->dev[1];
4282 if (dev1)
4283 unregister_netdev(dev1);
4284 unregister_netdev(dev0);
4285
4286 sky2_power_aux(hw);
4287
4288 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4289 sky2_write8(hw, B0_CTST, CS_RST_SET);
4290 sky2_read8(hw, B0_CTST);
4291
4292 free_irq(pdev->irq, hw);
4293 if (hw->flags & SKY2_HW_USE_MSI)
4294 pci_disable_msi(pdev);
4295 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4296 pci_release_regions(pdev);
4297 pci_disable_device(pdev);
4298
4299 if (dev1)
4300 free_netdev(dev1);
4301 free_netdev(dev0);
4302 iounmap(hw->regs);
4303 kfree(hw);
4304
4305 pci_set_drvdata(pdev, NULL);
4306 }
4307
4308 #ifdef CONFIG_PM
4309 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4310 {
4311 struct sky2_hw *hw = pci_get_drvdata(pdev);
4312 int i, wol = 0;
4313
4314 if (!hw)
4315 return 0;
4316
4317 for (i = 0; i < hw->ports; i++) {
4318 struct net_device *dev = hw->dev[i];
4319 struct sky2_port *sky2 = netdev_priv(dev);
4320
4321 if (netif_running(dev))
4322 sky2_down(dev);
4323
4324 if (sky2->wol)
4325 sky2_wol_init(sky2);
4326
4327 wol |= sky2->wol;
4328 }
4329
4330 sky2_write32(hw, B0_IMSK, 0);
4331 sky2_power_aux(hw);
4332
4333 pci_save_state(pdev);
4334 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4335 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4336
4337 return 0;
4338 }
4339
4340 static int sky2_resume(struct pci_dev *pdev)
4341 {
4342 struct sky2_hw *hw = pci_get_drvdata(pdev);
4343 int i, err;
4344
4345 if (!hw)
4346 return 0;
4347
4348 err = pci_set_power_state(pdev, PCI_D0);
4349 if (err)
4350 goto out;
4351
4352 err = pci_restore_state(pdev);
4353 if (err)
4354 goto out;
4355
4356 pci_enable_wake(pdev, PCI_D0, 0);
4357
4358 /* Re-enable all clocks */
4359 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4360 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4361 hw->chip_id == CHIP_ID_YUKON_FE_P)
4362 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4363
4364 sky2_reset(hw);
4365
4366 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4367
4368 for (i = 0; i < hw->ports; i++) {
4369 struct net_device *dev = hw->dev[i];
4370 if (netif_running(dev)) {
4371 err = sky2_up(dev);
4372 if (err) {
4373 printk(KERN_ERR PFX "%s: could not up: %d\n",
4374 dev->name, err);
4375 dev_close(dev);
4376 goto out;
4377 }
4378
4379 sky2_set_multicast(dev);
4380 }
4381 }
4382
4383 return 0;
4384 out:
4385 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4386 pci_disable_device(pdev);
4387 return err;
4388 }
4389 #endif
4390
4391 static void sky2_shutdown(struct pci_dev *pdev)
4392 {
4393 struct sky2_hw *hw = pci_get_drvdata(pdev);
4394 int i, wol = 0;
4395
4396 if (!hw)
4397 return;
4398
4399 del_timer_sync(&hw->watchdog_timer);
4400
4401 for (i = 0; i < hw->ports; i++) {
4402 struct net_device *dev = hw->dev[i];
4403 struct sky2_port *sky2 = netdev_priv(dev);
4404
4405 if (sky2->wol) {
4406 wol = 1;
4407 sky2_wol_init(sky2);
4408 }
4409 }
4410
4411 if (wol)
4412 sky2_power_aux(hw);
4413
4414 pci_enable_wake(pdev, PCI_D3hot, wol);
4415 pci_enable_wake(pdev, PCI_D3cold, wol);
4416
4417 pci_disable_device(pdev);
4418 pci_set_power_state(pdev, PCI_D3hot);
4419
4420 }
4421
4422 static struct pci_driver sky2_driver = {
4423 .name = DRV_NAME,
4424 .id_table = sky2_id_table,
4425 .probe = sky2_probe,
4426 .remove = __devexit_p(sky2_remove),
4427 #ifdef CONFIG_PM
4428 .suspend = sky2_suspend,
4429 .resume = sky2_resume,
4430 #endif
4431 .shutdown = sky2_shutdown,
4432 };
4433
4434 static int __init sky2_init_module(void)
4435 {
4436 sky2_debug_init();
4437 return pci_register_driver(&sky2_driver);
4438 }
4439
4440 static void __exit sky2_cleanup_module(void)
4441 {
4442 pci_unregister_driver(&sky2_driver);
4443 sky2_debug_cleanup();
4444 }
4445
4446 module_init(sky2_init_module);
4447 module_exit(sky2_cleanup_module);
4448
4449 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4450 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4451 MODULE_LICENSE("GPL");
4452 MODULE_VERSION(DRV_VERSION);
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