drivers/net/wan/lmc/lmc_var.h

   1 #ifndef _LMC_VAR_H_
   2 #define _LMC_VAR_H_
   3
   4 /* $Id: lmc_var.h,v 1.17 2000/04/06 12:16:47 asj Exp $ */
   5
   6  /*
   7   * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
   8   * All rights reserved.  www.lanmedia.com
   9   *
  10   * This code is written by:
  11   * Andrew Stanley-Jones (asj@cban.com)
  12   * Rob Braun (bbraun@vix.com),
  13   * Michael Graff (explorer@vix.com) and
  14   * Matt Thomas (matt@3am-software.com).
  15   *
  16   * This software may be used and distributed according to the terms
  17   * of the GNU General Public License version 2, incorporated herein by reference.
  18   */
  19
  20 #include <linux/timer.h>
  21
  22 #ifndef __KERNEL__
  23 typedef signed char s8;
  24 typedef unsigned char u8;
  25
  26 typedef signed short s16;
  27 typedef unsigned short u16;
  28
  29 typedef signed int s32;
  30 typedef unsigned int u32;
  31
  32 typedef signed long long s64;
  33 typedef unsigned long long u64;
  34
  35 #define BITS_PER_LONG 32
  36
  37 #endif
  38
  39 /*
  40  * basic definitions used in lmc include files
  41  */
  42
  43 typedef struct lmc___softc lmc_softc_t;
  44 typedef struct lmc___media lmc_media_t;
  45 typedef struct lmc___ctl lmc_ctl_t;
  46
  47 #define lmc_csrptr_t    unsigned long
  48 #define u_int16_t       u16
  49 #define u_int8_t        u8
  50 #define tulip_uint32_t  u32
  51
  52 #define LMC_REG_RANGE 0x80
  53
  54 #define LMC_PRINTF_FMT  "%s"
  55 #define LMC_PRINTF_ARGS (sc->lmc_device->name)
  56
  57 #define TX_TIMEOUT (2*HZ)
  58
  59 #define LMC_TXDESCS            32
  60 #define LMC_RXDESCS            32
  61
  62 #define LMC_LINK_UP            1
  63 #define LMC_LINK_DOWN          0
  64
  65 /* These macros for generic read and write to and from the dec chip */
  66 #define LMC_CSR_READ(sc, csr) \
  67         inl((sc)->lmc_csrs.csr)
  68 #define LMC_CSR_WRITE(sc, reg, val) \
  69         outl((val), (sc)->lmc_csrs.reg)
  70
  71 //#ifdef _LINUX_DELAY_H
  72 //      #define SLOW_DOWN_IO udelay(2);
  73 //      #undef __SLOW_DOWN_IO
  74 //      #define __SLOW_DOWN_IO udelay(2);
  75 //#endif
  76
  77 #define DELAY(n) SLOW_DOWN_IO
  78
  79 #define lmc_delay() inl(sc->lmc_csrs.csr_9)
  80
  81 /* This macro sync's up with the mii so that reads and writes can take place */
  82 #define LMC_MII_SYNC(sc) do {int n=32; while( n >= 0 ) { \
  83                 LMC_CSR_WRITE((sc), csr_9, 0x20000); \
  84                 lmc_delay(); \
  85                 LMC_CSR_WRITE((sc), csr_9, 0x30000); \
  86                 lmc_delay(); \
  87                 n--; }} while(0)
  88
  89 struct lmc_regfile_t {
  90     lmc_csrptr_t csr_busmode;                  /* CSR0 */
  91     lmc_csrptr_t csr_txpoll;                   /* CSR1 */
  92     lmc_csrptr_t csr_rxpoll;                   /* CSR2 */
  93     lmc_csrptr_t csr_rxlist;                   /* CSR3 */
  94     lmc_csrptr_t csr_txlist;                   /* CSR4 */
  95     lmc_csrptr_t csr_status;                   /* CSR5 */
  96     lmc_csrptr_t csr_command;                  /* CSR6 */
  97     lmc_csrptr_t csr_intr;                     /* CSR7 */
  98     lmc_csrptr_t csr_missed_frames;            /* CSR8 */
  99     lmc_csrptr_t csr_9;                        /* CSR9 */
 100     lmc_csrptr_t csr_10;                       /* CSR10 */
 101     lmc_csrptr_t csr_11;                       /* CSR11 */
 102     lmc_csrptr_t csr_12;                       /* CSR12 */
 103     lmc_csrptr_t csr_13;                       /* CSR13 */
 104     lmc_csrptr_t csr_14;                       /* CSR14 */
 105     lmc_csrptr_t csr_15;                       /* CSR15 */
 106 };
 107
 108 #define csr_enetrom             csr_9   /* 21040 */
 109 #define csr_reserved            csr_10  /* 21040 */
 110 #define csr_full_duplex         csr_11  /* 21040 */
 111 #define csr_bootrom             csr_10  /* 21041/21140A/?? */
 112 #define csr_gp                  csr_12  /* 21140* */
 113 #define csr_watchdog            csr_15  /* 21140* */
 114 #define csr_gp_timer            csr_11  /* 21041/21140* */
 115 #define csr_srom_mii            csr_9   /* 21041/21140* */
 116 #define csr_sia_status          csr_12  /* 2104x */
 117 #define csr_sia_connectivity    csr_13  /* 2104x */
 118 #define csr_sia_tx_rx           csr_14  /* 2104x */
 119 #define csr_sia_general         csr_15  /* 2104x */
 120
 121 /* tulip length/control transmit descriptor definitions
 122  *  used to define bits in the second tulip_desc_t field (length)
 123  *  for the transmit descriptor -baz */
 124
 125 #define LMC_TDES_FIRST_BUFFER_SIZE       ((u_int32_t)(0x000007FF))
 126 #define LMC_TDES_SECOND_BUFFER_SIZE      ((u_int32_t)(0x003FF800))
 127 #define LMC_TDES_HASH_FILTERING          ((u_int32_t)(0x00400000))
 128 #define LMC_TDES_DISABLE_PADDING         ((u_int32_t)(0x00800000))
 129 #define LMC_TDES_SECOND_ADDR_CHAINED     ((u_int32_t)(0x01000000))
 130 #define LMC_TDES_END_OF_RING             ((u_int32_t)(0x02000000))
 131 #define LMC_TDES_ADD_CRC_DISABLE         ((u_int32_t)(0x04000000))
 132 #define LMC_TDES_SETUP_PACKET            ((u_int32_t)(0x08000000))
 133 #define LMC_TDES_INVERSE_FILTERING       ((u_int32_t)(0x10000000))
 134 #define LMC_TDES_FIRST_SEGMENT           ((u_int32_t)(0x20000000))
 135 #define LMC_TDES_LAST_SEGMENT            ((u_int32_t)(0x40000000))
 136 #define LMC_TDES_INTERRUPT_ON_COMPLETION ((u_int32_t)(0x80000000))
 137
 138 #define TDES_SECOND_BUFFER_SIZE_BIT_NUMBER  11
 139 #define TDES_COLLISION_COUNT_BIT_NUMBER     3
 140
 141 /* Constants for the RCV descriptor RDES */
 142
 143 #define LMC_RDES_OVERFLOW             ((u_int32_t)(0x00000001))
 144 #define LMC_RDES_CRC_ERROR            ((u_int32_t)(0x00000002))
 145 #define LMC_RDES_DRIBBLING_BIT            ((u_int32_t)(0x00000004))
 146 #define LMC_RDES_REPORT_ON_MII_ERR    ((u_int32_t)(0x00000008))
 147 #define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u_int32_t)(0x00000010))
 148 #define LMC_RDES_FRAME_TYPE           ((u_int32_t)(0x00000020))
 149 #define LMC_RDES_COLLISION_SEEN       ((u_int32_t)(0x00000040))
 150 #define LMC_RDES_FRAME_TOO_LONG       ((u_int32_t)(0x00000080))
 151 #define LMC_RDES_LAST_DESCRIPTOR      ((u_int32_t)(0x00000100))
 152 #define LMC_RDES_FIRST_DESCRIPTOR     ((u_int32_t)(0x00000200))
 153 #define LMC_RDES_MULTICAST_FRAME      ((u_int32_t)(0x00000400))
 154 #define LMC_RDES_RUNT_FRAME           ((u_int32_t)(0x00000800))
 155 #define LMC_RDES_DATA_TYPE            ((u_int32_t)(0x00003000))
 156 #define LMC_RDES_LENGTH_ERROR         ((u_int32_t)(0x00004000))
 157 #define LMC_RDES_ERROR_SUMMARY        ((u_int32_t)(0x00008000))
 158 #define LMC_RDES_FRAME_LENGTH         ((u_int32_t)(0x3FFF0000))
 159 #define LMC_RDES_OWN_BIT              ((u_int32_t)(0x80000000))
 160
 161 #define RDES_FRAME_LENGTH_BIT_NUMBER       16
 162
 163 #define LMC_RDES_ERROR_MASK ( (u_int32_t)( \
 164           LMC_RDES_OVERFLOW \
 165         | LMC_RDES_DRIBBLING_BIT \
 166         | LMC_RDES_REPORT_ON_MII_ERR \
 167         | LMC_RDES_COLLISION_SEEN ) )
 168
 169
 170 /*
 171  * Ioctl info
 172  */
 173
 174 typedef struct {
 175         u_int32_t       n;
 176         u_int32_t       m;
 177         u_int32_t       v;
 178         u_int32_t       x;
 179         u_int32_t       r;
 180         u_int32_t       f;
 181         u_int32_t       exact;
 182 } lmc_av9110_t;
 183
 184 /*
 185  * Common structure passed to the ioctl code.
 186  */
 187 struct lmc___ctl {
 188         u_int32_t       cardtype;
 189         u_int32_t       clock_source;           /* HSSI, T1 */
 190         u_int32_t       clock_rate;             /* T1 */
 191         u_int32_t       crc_length;
 192         u_int32_t       cable_length;           /* DS3 */
 193         u_int32_t       scrambler_onoff;        /* DS3 */
 194         u_int32_t       cable_type;             /* T1 */
 195         u_int32_t       keepalive_onoff;        /* protocol */
 196         u_int32_t       ticks;                  /* ticks/sec */
 197         union {
 198                 lmc_av9110_t    ssi;
 199         } cardspec;
 200         u_int32_t       circuit_type;   /* T1 or E1 */
 201 };
 202
 203
 204 /*
 205  * Carefull, look at the data sheet, there's more to this
 206  * structure than meets the eye.  It should probably be:
 207  *
 208  * struct tulip_desc_t {
 209  *         u8  own:1;
 210  *         u32 status:31;
 211  *         u32 control:10;
 212  *         u32 buffer1;
 213  *         u32 buffer2;
 214  * };
 215  * You could also expand status control to provide more bit information
 216  */
 217
 218 struct tulip_desc_t {
 219         s32 status;
 220         s32 length;
 221         u32 buffer1;
 222         u32 buffer2;
 223 };
 224
 225 /*
 226  * media independent methods to check on media status, link, light LEDs,
 227  * etc.
 228  */
 229 struct lmc___media {
 230         void    (* init)(lmc_softc_t * const);
 231         void    (* defaults)(lmc_softc_t * const);
 232         void    (* set_status)(lmc_softc_t * const, lmc_ctl_t *);
 233         void    (* set_clock_source)(lmc_softc_t * const, int);
 234         void    (* set_speed)(lmc_softc_t * const, lmc_ctl_t *);
 235         void    (* set_cable_length)(lmc_softc_t * const, int);
 236         void    (* set_scrambler)(lmc_softc_t * const, int);
 237         int     (* get_link_status)(lmc_softc_t * const);
 238         void    (* set_link_status)(lmc_softc_t * const, int);
 239         void    (* set_crc_length)(lmc_softc_t * const, int);
 240         void    (* set_circuit_type)(lmc_softc_t * const, int);
 241         void    (* watchdog)(lmc_softc_t * const);
 242 };
 243
 244
 245 #define STATCHECK     0xBEEFCAFE
 246
 247 /*  Included in this structure are first
 248  *   - standard net_device_stats
 249  *   - some other counters used for debug and driver performance
 250  *  evaluation -baz
 251  */
 252 struct lmc_statistics
 253 {
 254         unsigned long     rx_packets;             /* total packets received       */
 255         unsigned long     tx_packets;             /* total packets transmitted    */
 256         unsigned long     rx_bytes;
 257         unsigned long     tx_bytes;
 258
 259         unsigned long     rx_errors;              /* bad packets received         */
 260         unsigned long     tx_errors;              /* packet transmit problems     */
 261         unsigned long     rx_dropped;             /* no space in linux buffers    */
 262         unsigned long     tx_dropped;             /* no space available in linux  */
 263         unsigned long     multicast;              /* multicast packets received   */
 264         unsigned long     collisions;
 265
 266         /* detailed rx_errors: */
 267         unsigned long     rx_length_errors;
 268         unsigned long     rx_over_errors;         /* receiver ring buff overflow  */
 269         unsigned long     rx_crc_errors;          /* recved pkt with crc error    */
 270         unsigned long     rx_frame_errors;        /* recv'd frame alignment error */
 271         unsigned long     rx_fifo_errors;         /* recv'r fifo overrun          */
 272         unsigned long     rx_missed_errors;       /* receiver missed packet       */
 273
 274         /* detailed tx_errors */
 275         unsigned long     tx_aborted_errors;
 276         unsigned long     tx_carrier_errors;
 277         unsigned long     tx_fifo_errors;
 278         unsigned long     tx_heartbeat_errors;
 279         unsigned long     tx_window_errors;
 280
 281         /* for cslip etc */
 282         unsigned long rx_compressed;
 283         unsigned long tx_compressed;
 284
 285         /* -------------------------------------
 286          * Custom stats & counters follow -baz */
 287         u_int32_t       version_size;
 288         u_int32_t       lmc_cardtype;
 289
 290         u_int32_t       tx_ProcTimeout;
 291         u_int32_t       tx_IntTimeout;
 292         u_int32_t       tx_NoCompleteCnt;
 293         u_int32_t       tx_MaxXmtsB4Int;
 294         u_int32_t       tx_TimeoutCnt;
 295         u_int32_t       tx_OutOfSyncPtr;
 296         u_int32_t       tx_tbusy0;
 297         u_int32_t       tx_tbusy1;
 298         u_int32_t       tx_tbusy_calls;
 299         u_int32_t       resetCount;
 300         u_int32_t       lmc_txfull;
 301         u_int32_t       tbusy;
 302         u_int32_t       dirtyTx;
 303         u_int32_t       lmc_next_tx;
 304         u_int32_t       otherTypeCnt;
 305         u_int32_t       lastType;
 306         u_int32_t       lastTypeOK;
 307         u_int32_t       txLoopCnt;
 308         u_int32_t       usedXmtDescripCnt;
 309         u_int32_t       txIndexCnt;
 310         u_int32_t       rxIntLoopCnt;
 311
 312         u_int32_t       rx_SmallPktCnt;
 313         u_int32_t       rx_BadPktSurgeCnt;
 314         u_int32_t       rx_BuffAllocErr;
 315         u_int32_t       tx_lossOfClockCnt;
 316
 317         /* T1 error counters */
 318         u_int32_t       framingBitErrorCount;
 319         u_int32_t       lineCodeViolationCount;
 320
 321         u_int32_t       lossOfFrameCount;
 322         u_int32_t       changeOfFrameAlignmentCount;
 323         u_int32_t       severelyErroredFrameCount;
 324
 325         u_int32_t       check;
 326 };
 327
 328
 329 typedef struct lmc_xinfo {
 330         u_int32_t       Magic0;                         /* BEEFCAFE */
 331
 332         u_int32_t       PciCardType;
 333         u_int32_t       PciSlotNumber;          /* PCI slot number       */
 334
 335         u_int16_t       DriverMajorVersion;
 336         u_int16_t       DriverMinorVersion;
 337         u_int16_t       DriverSubVersion;
 338
 339         u_int16_t       XilinxRevisionNumber;
 340         u_int16_t       MaxFrameSize;
 341
 342         u_int16_t       t1_alarm1_status;
 343         u_int16_t       t1_alarm2_status;
 344
 345         int                     link_status;
 346         u_int32_t       mii_reg16;
 347
 348         u_int32_t       Magic1;                         /* DEADBEEF */
 349 } LMC_XINFO;
 350
 351
 352 /*
 353  * forward decl
 354  */
 355 struct lmc___softc {
 356         void *if_ptr;   /* General purpose pointer (used by SPPP) */
 357         char                   *name;
 358         u8                      board_idx;
 359         struct lmc_statistics   stats;
 360         struct net_device          *lmc_device;
 361
 362         int                     hang, rxdesc, bad_packet, some_counter;
 363         u_int32_t               txgo;
 364         struct lmc_regfile_t    lmc_csrs;
 365         volatile u_int32_t      lmc_txtick;
 366         volatile u_int32_t      lmc_rxtick;
 367         u_int32_t               lmc_flags;
 368         u_int32_t               lmc_intrmask;   /* our copy of csr_intr */
 369         u_int32_t               lmc_cmdmode;    /* our copy of csr_cmdmode */
 370         u_int32_t               lmc_busmode;    /* our copy of csr_busmode */
 371         u_int32_t               lmc_gpio_io;    /* state of in/out settings */
 372         u_int32_t               lmc_gpio;       /* state of outputs */
 373         struct sk_buff*         lmc_txq[LMC_TXDESCS];
 374         struct sk_buff*         lmc_rxq[LMC_RXDESCS];
 375         volatile
 376         struct tulip_desc_t     lmc_rxring[LMC_RXDESCS];
 377         volatile
 378         struct tulip_desc_t     lmc_txring[LMC_TXDESCS];
 379         unsigned int            lmc_next_rx, lmc_next_tx;
 380         volatile
 381         unsigned int            lmc_taint_tx, lmc_taint_rx;
 382         int                     lmc_tx_start, lmc_txfull;
 383         int                     lmc_txbusy;
 384         u_int16_t               lmc_miireg16;
 385         int                     lmc_ok;
 386         int                     last_link_status;
 387         int                     lmc_cardtype;
 388         u_int32_t               last_frameerr;
 389         lmc_media_t            *lmc_media;
 390         struct timer_list       timer;
 391         lmc_ctl_t               ictl;
 392         u_int32_t               TxDescriptControlInit;
 393
 394         int                     tx_TimeoutInd; /* additional driver state */
 395         int                     tx_TimeoutDisplay;
 396         unsigned int            lastlmc_taint_tx;
 397         int                     lasttx_packets;
 398         u_int32_t               tx_clockState;
 399         u_int32_t               lmc_crcSize;
 400         LMC_XINFO               lmc_xinfo;
 401         char                    lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */
 402         char                    lmc_timing; /* for HSSI and SSI */
 403         int                     got_irq;
 404
 405         char                    last_led_err[4];
 406
 407         u32                     last_int;
 408         u32                     num_int;
 409
 410         spinlock_t              lmc_lock;
 411         u_int16_t               if_type;       /* PPP or NET */
 412         struct ppp_device       *pd;
 413
 414         /* Failure cases */
 415         u8                       failed_ring;
 416         u8                       failed_recv_alloc;
 417
 418         /* Structure check */
 419         u32                     check;
 420 };
 421
 422 #define LMC_PCI_TIME 1
 423 #define LMC_EXT_TIME 0
 424
 425 #define PKT_BUF_SZ              1542  /* was 1536 */
 426
 427 /* CSR5 settings */
 428 #define TIMER_INT     0x00000800
 429 #define TP_LINK_FAIL  0x00001000
 430 #define TP_LINK_PASS  0x00000010
 431 #define NORMAL_INT    0x00010000
 432 #define ABNORMAL_INT  0x00008000
 433 #define RX_JABBER_INT 0x00000200
 434 #define RX_DIED       0x00000100
 435 #define RX_NOBUFF     0x00000080
 436 #define RX_INT        0x00000040
 437 #define TX_FIFO_UNDER 0x00000020
 438 #define TX_JABBER     0x00000008
 439 #define TX_NOBUFF     0x00000004
 440 #define TX_DIED       0x00000002
 441 #define TX_INT        0x00000001
 442
 443 /* CSR6 settings */
 444 #define OPERATION_MODE  0x00000200 /* Full Duplex      */
 445 #define PROMISC_MODE    0x00000040 /* Promiscuous Mode */
 446 #define RECIEVE_ALL     0x40000000 /* Recieve All      */
 447 #define PASS_BAD_FRAMES 0x00000008 /* Pass Bad Frames  */
 448
 449 /* Dec control registers  CSR6 as well */
 450 #define LMC_DEC_ST 0x00002000
 451 #define LMC_DEC_SR 0x00000002
 452
 453 /* CSR15 settings */
 454 #define RECV_WATCHDOG_DISABLE 0x00000010
 455 #define JABBER_DISABLE        0x00000001
 456
 457 /* More settings */
 458 /*
 459  * aSR6 -- Command (Operation Mode) Register
 460  */
 461 #define TULIP_CMD_RECEIVEALL    0x40000000L /* (RW)  Receivel all frames? */
 462 #define TULIP_CMD_MUSTBEONE     0x02000000L /* (RW)  Must Be One (21140) */
 463 #define TULIP_CMD_TXTHRSHLDCTL  0x00400000L /* (RW)  Transmit Threshold Mode (21140) */
 464 #define TULIP_CMD_STOREFWD      0x00200000L /* (RW)  Store and Foward (21140) */
 465 #define TULIP_CMD_NOHEARTBEAT   0x00080000L /* (RW)  No Heartbeat (21140) */
 466 #define TULIP_CMD_PORTSELECT    0x00040000L /* (RW)  Post Select (100Mb) (21140) */
 467 #define TULIP_CMD_FULLDUPLEX    0x00000200L /* (RW)  Full Duplex Mode */
 468 #define TULIP_CMD_OPERMODE      0x00000C00L /* (RW)  Operating Mode */
 469 #define TULIP_CMD_PROMISCUOUS   0x00000041L /* (RW)  Promiscuous Mode */
 470 #define TULIP_CMD_PASSBADPKT    0x00000008L /* (RW)  Pass Bad Frames */
 471 #define TULIP_CMD_THRESHOLDCTL  0x0000C000L /* (RW)  Threshold Control */
 472
 473 #define TULIP_GP_PINSET         0x00000100L
 474 #define TULIP_BUSMODE_SWRESET   0x00000001L
 475 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L
 476 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L
 477
 478 #define TULIP_STS_NORMALINTR    0x00010000L /* (RW)  Normal Interrupt */
 479 #define TULIP_STS_ABNRMLINTR    0x00008000L /* (RW)  Abnormal Interrupt */
 480 #define TULIP_STS_ERI           0x00004000L /* (RW)  Early Receive Interrupt */
 481 #define TULIP_STS_SYSERROR      0x00002000L /* (RW)  System Error */
 482 #define TULIP_STS_GTE           0x00000800L /* (RW)  General Pupose Timer Exp */
 483 #define TULIP_STS_ETI           0x00000400L /* (RW)  Early Transmit Interrupt */
 484 #define TULIP_STS_RXWT          0x00000200L /* (RW)  Receiver Watchdog Timeout */
 485 #define TULIP_STS_RXSTOPPED     0x00000100L /* (RW)  Receiver Process Stopped */
 486 #define TULIP_STS_RXNOBUF       0x00000080L /* (RW)  Receive Buf Unavail */
 487 #define TULIP_STS_RXINTR        0x00000040L /* (RW)  Receive Interrupt */
 488 #define TULIP_STS_TXUNDERFLOW   0x00000020L /* (RW)  Transmit Underflow */
 489 #define TULIP_STS_TXJABER       0x00000008L /* (RW)  Jabber timeout */
 490 #define TULIP_STS_TXNOBUF       0x00000004L
 491 #define TULIP_STS_TXSTOPPED     0x00000002L /* (RW)  Transmit Process Stopped */
 492 #define TULIP_STS_TXINTR        0x00000001L /* (RW)  Transmit Interrupt */
 493
 494 #define TULIP_STS_RXS_STOPPED   0x00000000L /*        000 - Stopped */
 495
 496 #define TULIP_STS_RXSTOPPED     0x00000100L             /* (RW)  Receive Process Stopped */
 497 #define TULIP_STS_RXNOBUF       0x00000080L
 498
 499 #define TULIP_CMD_TXRUN         0x00002000L /* (RW)  Start/Stop Transmitter */
 500 #define TULIP_CMD_RXRUN         0x00000002L /* (RW)  Start/Stop Receive Filtering */
 501 #define TULIP_DSTS_TxDEFERRED   0x00000001      /* Initially Deferred */
 502 #define TULIP_DSTS_OWNER        0x80000000      /* Owner (1 = 21040) */
 503 #define TULIP_DSTS_RxMIIERR     0x00000008
 504 #define LMC_DSTS_ERRSUM         (TULIP_DSTS_RxMIIERR)
 505
 506 #define TULIP_DEFAULT_INTR_MASK  (TULIP_STS_NORMALINTR \
 507   | TULIP_STS_RXINTR       \
 508   | TULIP_STS_TXINTR     \
 509   | TULIP_STS_ABNRMLINTR \
 510   | TULIP_STS_SYSERROR   \
 511   | TULIP_STS_TXSTOPPED  \
 512   | TULIP_STS_TXUNDERFLOW\
 513   | TULIP_STS_RXSTOPPED )
 514
 515 #define DESC_OWNED_BY_SYSTEM   ((u_int32_t)(0x00000000))
 516 #define DESC_OWNED_BY_DC21X4   ((u_int32_t)(0x80000000))
 517
 518 #ifndef TULIP_CMD_RECEIVEALL
 519 #define TULIP_CMD_RECEIVEALL 0x40000000L
 520 #endif
 521
 522 /* Adapter module number */
 523 #define LMC_ADAP_HSSI           2
 524 #define LMC_ADAP_DS3            3
 525 #define LMC_ADAP_SSI            4
 526 #define LMC_ADAP_T1             5
 527
 528 #define HDLC_HDR_LEN  4
 529 #define HDLC_ADDR_LEN 1
 530 #define HDLC_SLARP    0x8035
 531 #define LMC_MTU 1500
 532 #define SLARP_LINECHECK 2
 533
 534 #define LMC_CRC_LEN_16 2  /* 16-bit CRC */
 535 #define LMC_CRC_LEN_32 4
 536
 537 #ifdef LMC_HDLC
 538 /* definition of an hdlc header. */
 539 struct hdlc_hdr
 540 {
 541         u8  address;
 542         u8  control;
 543         u16 type;
 544 };
 545
 546 /* definition of a slarp header. */
 547 struct slarp
 548 {
 549         long code;
 550         union sl
 551         {
 552                 struct
 553                 {
 554                         ulong address;
 555                         ulong mask;
 556                         ushort unused;
 557                 } add;
 558                 struct
 559                 {
 560                         ulong mysequence;
 561                         ulong yoursequence;
 562                         ushort reliability;
 563                         ulong time;
 564                 } chk;
 565         } t;
 566 };
 567 #endif /* LMC_HDLC */
 568
 569
 570 #endif /* _LMC_VAR_H_ */