drivers/video/sis/sis.h

   1 /*
   2  * SiS 300/540/630[S]/730[S],
   3  * SiS 315[E|PRO]/550/[M]65x/[M]661[F|M]X/740/[M]741[GX]/330/[M]76x[GX],
   4  * XGI V3XT/V5/V8, Z7
   5  * frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3
   6  *
   7  * Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the named License,
  12  * or any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
  22  */
  23
  24 #ifndef _SIS_H_
  25 #define _SIS_H_
  26
  27 #include <linux/version.h>
  28
  29 #include "osdef.h"
  30 #include <video/sisfb.h>
  31
  32 #include "vgatypes.h"
  33 #include "vstruct.h"
  34
  35 #define VER_MAJOR               1
  36 #define VER_MINOR               8
  37 #define VER_LEVEL               9
  38
  39 #include <linux/spinlock.h>
  40
  41 #ifdef CONFIG_COMPAT
  42 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10)
  43 #include <linux/ioctl32.h>
  44 #define SIS_OLD_CONFIG_COMPAT
  45 #else
  46 #define SIS_NEW_CONFIG_COMPAT
  47 #endif
  48 #endif  /* CONFIG_COMPAT */
  49
  50 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,8)
  51 #define SIS_IOTYPE1 void __iomem
  52 #define SIS_IOTYPE2 __iomem
  53 #define SISINITSTATIC static
  54 #else
  55 #define SIS_IOTYPE1 unsigned char
  56 #define SIS_IOTYPE2
  57 #define SISINITSTATIC
  58 #endif
  59
  60 #undef SISFBDEBUG
  61
  62 #ifdef SISFBDEBUG
  63 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
  64 #define TWDEBUG(x) printk(KERN_INFO x "\n");
  65 #else
  66 #define DPRINTK(fmt, args...)
  67 #define TWDEBUG(x)
  68 #endif
  69
  70 #define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)
  71
  72 /* To be included in pci_ids.h */
  73 #ifndef PCI_DEVICE_ID_SI_650_VGA
  74 #define PCI_DEVICE_ID_SI_650_VGA        0x6325
  75 #endif
  76 #ifndef PCI_DEVICE_ID_SI_650
  77 #define PCI_DEVICE_ID_SI_650            0x0650
  78 #endif
  79 #ifndef PCI_DEVICE_ID_SI_651
  80 #define PCI_DEVICE_ID_SI_651            0x0651
  81 #endif
  82 #ifndef PCI_DEVICE_ID_SI_740
  83 #define PCI_DEVICE_ID_SI_740            0x0740
  84 #endif
  85 #ifndef PCI_DEVICE_ID_SI_330
  86 #define PCI_DEVICE_ID_SI_330            0x0330
  87 #endif
  88 #ifndef PCI_DEVICE_ID_SI_660_VGA
  89 #define PCI_DEVICE_ID_SI_660_VGA        0x6330
  90 #endif
  91 #ifndef PCI_DEVICE_ID_SI_661
  92 #define PCI_DEVICE_ID_SI_661            0x0661
  93 #endif
  94 #ifndef PCI_DEVICE_ID_SI_741
  95 #define PCI_DEVICE_ID_SI_741            0x0741
  96 #endif
  97 #ifndef PCI_DEVICE_ID_SI_660
  98 #define PCI_DEVICE_ID_SI_660            0x0660
  99 #endif
 100 #ifndef PCI_DEVICE_ID_SI_760
 101 #define PCI_DEVICE_ID_SI_760            0x0760
 102 #endif
 103 #ifndef PCI_DEVICE_ID_SI_761
 104 #define PCI_DEVICE_ID_SI_761            0x0761
 105 #endif
 106
 107 #ifndef PCI_VENDOR_ID_XGI
 108 #define PCI_VENDOR_ID_XGI               0x18ca
 109 #endif
 110
 111 #ifndef PCI_DEVICE_ID_XGI_20
 112 #define PCI_DEVICE_ID_XGI_20            0x0020
 113 #endif
 114
 115 #ifndef PCI_DEVICE_ID_XGI_40
 116 #define PCI_DEVICE_ID_XGI_40            0x0040
 117 #endif
 118
 119 /* To be included in fb.h */
 120 #ifndef FB_ACCEL_SIS_GLAMOUR_2
 121 #define FB_ACCEL_SIS_GLAMOUR_2  40      /* SiS 315, 65x, 740, 661, 741  */
 122 #endif
 123 #ifndef FB_ACCEL_SIS_XABRE
 124 #define FB_ACCEL_SIS_XABRE      41      /* SiS 330 ("Xabre"), 76x       */
 125 #endif
 126 #ifndef FB_ACCEL_XGI_VOLARI_V
 127 #define FB_ACCEL_XGI_VOLARI_V   47      /* XGI Volari Vx (V3XT, V5, V8) */
 128 #endif
 129 #ifndef FB_ACCEL_XGI_VOLARI_Z
 130 #define FB_ACCEL_XGI_VOLARI_Z   48      /* XGI Volari Z7                */
 131 #endif
 132
 133 /* ivideo->caps */
 134 #define HW_CURSOR_CAP           0x80
 135 #define TURBO_QUEUE_CAP         0x40
 136 #define AGP_CMD_QUEUE_CAP       0x20
 137 #define VM_CMD_QUEUE_CAP        0x10
 138 #define MMIO_CMD_QUEUE_CAP      0x08
 139
 140 /* For 300 series */
 141 #define TURBO_QUEUE_AREA_SIZE   (512 * 1024)    /* 512K */
 142 #define HW_CURSOR_AREA_SIZE_300 4096            /* 4K */
 143
 144 /* For 315/Xabre series */
 145 #define COMMAND_QUEUE_AREA_SIZE (512 * 1024)    /* 512K */
 146 #define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024) /* 128k for XGI Z7 */
 147 #define HW_CURSOR_AREA_SIZE_315 16384           /* 16K */
 148 #define COMMAND_QUEUE_THRESHOLD 0x1F
 149
 150 #define SIS_OH_ALLOC_SIZE       4000
 151 #define SENTINEL                0x7fffffff
 152
 153 #define SEQ_ADR                 0x14
 154 #define SEQ_DATA                0x15
 155 #define DAC_ADR                 0x18
 156 #define DAC_DATA                0x19
 157 #define CRTC_ADR                0x24
 158 #define CRTC_DATA               0x25
 159 #define DAC2_ADR                (0x16-0x30)
 160 #define DAC2_DATA               (0x17-0x30)
 161 #define VB_PART1_ADR            (0x04-0x30)
 162 #define VB_PART1_DATA           (0x05-0x30)
 163 #define VB_PART2_ADR            (0x10-0x30)
 164 #define VB_PART2_DATA           (0x11-0x30)
 165 #define VB_PART3_ADR            (0x12-0x30)
 166 #define VB_PART3_DATA           (0x13-0x30)
 167 #define VB_PART4_ADR            (0x14-0x30)
 168 #define VB_PART4_DATA           (0x15-0x30)
 169
 170 #define SISSR                   ivideo->SiS_Pr.SiS_P3c4
 171 #define SISCR                   ivideo->SiS_Pr.SiS_P3d4
 172 #define SISDACA                 ivideo->SiS_Pr.SiS_P3c8
 173 #define SISDACD                 ivideo->SiS_Pr.SiS_P3c9
 174 #define SISPART1                ivideo->SiS_Pr.SiS_Part1Port
 175 #define SISPART2                ivideo->SiS_Pr.SiS_Part2Port
 176 #define SISPART3                ivideo->SiS_Pr.SiS_Part3Port
 177 #define SISPART4                ivideo->SiS_Pr.SiS_Part4Port
 178 #define SISPART5                ivideo->SiS_Pr.SiS_Part5Port
 179 #define SISDAC2A                SISPART5
 180 #define SISDAC2D                (SISPART5 + 1)
 181 #define SISMISCR                (ivideo->SiS_Pr.RelIO + 0x1c)
 182 #define SISMISCW                ivideo->SiS_Pr.SiS_P3c2
 183 #define SISINPSTAT              (ivideo->SiS_Pr.RelIO + 0x2a)
 184 #define SISPEL                  ivideo->SiS_Pr.SiS_P3c6
 185 #define SISVGAENABLE            (ivideo->SiS_Pr.RelIO + 0x13)
 186 #define SISVID                  (ivideo->SiS_Pr.RelIO + 0x02 - 0x30)
 187 #define SISCAP                  (ivideo->SiS_Pr.RelIO + 0x00 - 0x30)
 188
 189 #define IND_SIS_PASSWORD                0x05  /* SRs */
 190 #define IND_SIS_COLOR_MODE              0x06
 191 #define IND_SIS_RAMDAC_CONTROL          0x07
 192 #define IND_SIS_DRAM_SIZE               0x14
 193 #define IND_SIS_MODULE_ENABLE           0x1E
 194 #define IND_SIS_PCI_ADDRESS_SET         0x20
 195 #define IND_SIS_TURBOQUEUE_ADR          0x26
 196 #define IND_SIS_TURBOQUEUE_SET          0x27
 197 #define IND_SIS_POWER_ON_TRAP           0x38
 198 #define IND_SIS_POWER_ON_TRAP2          0x39
 199 #define IND_SIS_CMDQUEUE_SET            0x26
 200 #define IND_SIS_CMDQUEUE_THRESHOLD      0x27
 201
 202 #define IND_SIS_AGP_IO_PAD      0x48
 203
 204 #define SIS_CRT2_WENABLE_300    0x24  /* Part1 */
 205 #define SIS_CRT2_WENABLE_315    0x2F
 206
 207 #define SIS_PASSWORD            0x86  /* SR05 */
 208
 209 #define SIS_INTERLACED_MODE     0x20  /* SR06 */
 210 #define SIS_8BPP_COLOR_MODE     0x0
 211 #define SIS_15BPP_COLOR_MODE    0x1
 212 #define SIS_16BPP_COLOR_MODE    0x2
 213 #define SIS_32BPP_COLOR_MODE    0x4
 214
 215 #define SIS_ENABLE_2D           0x40  /* SR1E */
 216
 217 #define SIS_MEM_MAP_IO_ENABLE   0x01  /* SR20 */
 218 #define SIS_PCI_ADDR_ENABLE     0x80
 219
 220 #define SIS_AGP_CMDQUEUE_ENABLE         0x80  /* 315/330/340 series SR26 */
 221 #define SIS_VRAM_CMDQUEUE_ENABLE        0x40
 222 #define SIS_MMIO_CMD_ENABLE             0x20
 223 #define SIS_CMD_QUEUE_SIZE_512k         0x00
 224 #define SIS_CMD_QUEUE_SIZE_1M           0x04
 225 #define SIS_CMD_QUEUE_SIZE_2M           0x08
 226 #define SIS_CMD_QUEUE_SIZE_4M           0x0C
 227 #define SIS_CMD_QUEUE_RESET             0x01
 228 #define SIS_CMD_AUTO_CORR               0x02
 229
 230 #define SIS_CMD_QUEUE_SIZE_Z7_64k       0x00 /* XGI Z7 */
 231 #define SIS_CMD_QUEUE_SIZE_Z7_128k      0x04
 232
 233 #define SIS_SIMULTANEOUS_VIEW_ENABLE    0x01  /* CR30 */
 234 #define SIS_MODE_SELECT_CRT2            0x02
 235 #define SIS_VB_OUTPUT_COMPOSITE         0x04
 236 #define SIS_VB_OUTPUT_SVIDEO            0x08
 237 #define SIS_VB_OUTPUT_SCART             0x10
 238 #define SIS_VB_OUTPUT_LCD               0x20
 239 #define SIS_VB_OUTPUT_CRT2              0x40
 240 #define SIS_VB_OUTPUT_HIVISION          0x80
 241
 242 #define SIS_VB_OUTPUT_DISABLE   0x20  /* CR31 */
 243 #define SIS_DRIVER_MODE         0x40
 244
 245 #define SIS_VB_COMPOSITE        0x01  /* CR32 */
 246 #define SIS_VB_SVIDEO           0x02
 247 #define SIS_VB_SCART            0x04
 248 #define SIS_VB_LCD              0x08
 249 #define SIS_VB_CRT2             0x10
 250 #define SIS_CRT1                0x20
 251 #define SIS_VB_HIVISION         0x40
 252 #define SIS_VB_YPBPR            0x80
 253 #define SIS_VB_TV               (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \
 254                                 SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR)
 255
 256 #define SIS_EXTERNAL_CHIP_MASK                  0x0E  /* CR37 (< SiS 660) */
 257 #define SIS_EXTERNAL_CHIP_SIS301                0x01  /* in CR37 << 1 ! */
 258 #define SIS_EXTERNAL_CHIP_LVDS                  0x02
 259 #define SIS_EXTERNAL_CHIP_TRUMPION              0x03
 260 #define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL         0x04
 261 #define SIS_EXTERNAL_CHIP_CHRONTEL              0x05
 262 #define SIS310_EXTERNAL_CHIP_LVDS               0x02
 263 #define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL      0x03
 264
 265 #define SIS_AGP_2X              0x20  /* CR48 */
 266
 267 /* vbflags, private entries (others in sisfb.h) */
 268 #define VB_CONEXANT             0x00000800      /* 661 series only */
 269 #define VB_TRUMPION             VB_CONEXANT     /* 300 series only */
 270 #define VB_302ELV               0x00004000
 271 #define VB_301                  0x00100000      /* Video bridge type */
 272 #define VB_301B                 0x00200000
 273 #define VB_302B                 0x00400000
 274 #define VB_30xBDH               0x00800000      /* 30xB DH version (w/o LCD support) */
 275 #define VB_LVDS                 0x01000000
 276 #define VB_CHRONTEL             0x02000000
 277 #define VB_301LV                0x04000000
 278 #define VB_302LV                0x08000000
 279 #define VB_301C                 0x10000000
 280
 281 #define VB_SISBRIDGE            (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV)
 282 #define VB_VIDEOBRIDGE          (VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT)
 283
 284 /* vbflags2 (static stuff only!) */
 285 #define VB2_SISUMC              0x00000001
 286 #define VB2_301                 0x00000002      /* Video bridge type */
 287 #define VB2_301B                0x00000004
 288 #define VB2_301C                0x00000008
 289 #define VB2_307T                0x00000010
 290 #define VB2_302B                0x00000800
 291 #define VB2_301LV               0x00001000
 292 #define VB2_302LV               0x00002000
 293 #define VB2_302ELV              0x00004000
 294 #define VB2_307LV               0x00008000
 295 #define VB2_30xBDH              0x08000000      /* 30xB DH version (w/o LCD support) */
 296 #define VB2_CONEXANT            0x10000000
 297 #define VB2_TRUMPION            0x20000000
 298 #define VB2_LVDS                0x40000000
 299 #define VB2_CHRONTEL            0x80000000
 300
 301 #define VB2_SISLVDSBRIDGE       (VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)
 302 #define VB2_SISTMDSBRIDGE       (VB2_301   | VB2_301B  | VB2_301C   | VB2_302B | VB2_307T)
 303 #define VB2_SISBRIDGE           (VB2_SISLVDSBRIDGE | VB2_SISTMDSBRIDGE)
 304
 305 #define VB2_SISTMDSLCDABRIDGE   (VB2_301C | VB2_307T)
 306 #define VB2_SISLCDABRIDGE       (VB2_SISTMDSLCDABRIDGE | VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)
 307
 308 #define VB2_SISHIVISIONBRIDGE   (VB2_301  | VB2_301B | VB2_302B)
 309 #define VB2_SISYPBPRBRIDGE      (VB2_301C | VB2_307T | VB2_SISLVDSBRIDGE)
 310 #define VB2_SISYPBPRARBRIDGE    (VB2_301C | VB2_307T | VB2_307LV)
 311 #define VB2_SISTAP4SCALER       (VB2_301C | VB2_307T | VB2_302ELV | VB2_307LV)
 312 #define VB2_SISTVBRIDGE         (VB2_SISHIVISIONBRIDGE | VB2_SISYPBPRBRIDGE)
 313
 314 #define VB2_SISVGA2BRIDGE       (VB2_301 | VB2_301B | VB2_301C | VB2_302B | VB2_307T)
 315
 316 #define VB2_VIDEOBRIDGE         (VB2_SISBRIDGE | VB2_LVDS | VB2_CHRONTEL | VB2_CONEXANT)
 317
 318 #define VB2_30xB                (VB2_301B  | VB2_301C   | VB2_302B  | VB2_307T)
 319 #define VB2_30xBLV              (VB2_30xB  | VB2_SISLVDSBRIDGE)
 320 #define VB2_30xC                (VB2_301C  | VB2_307T)
 321 #define VB2_30xCLV              (VB2_301C  | VB2_307T   | VB2_302ELV| VB2_307LV)
 322 #define VB2_SISEMIBRIDGE        (VB2_302LV | VB2_302ELV | VB2_307LV)
 323 #define VB2_LCD162MHZBRIDGE     (VB2_301C  | VB2_307T)
 324 #define VB2_LCDOVER1280BRIDGE   (VB2_301C  | VB2_307T   | VB2_302LV | VB2_302ELV | VB2_307LV)
 325 #define VB2_LCDOVER1600BRIDGE   (VB2_307T  | VB2_307LV)
 326 #define VB2_RAMDAC202MHZBRIDGE  (VB2_301C  | VB2_307T)
 327
 328 /* I/O port access macros */
 329 #define inSISREG(base)          inb(base)
 330
 331 #define outSISREG(base,val)     outb(val,base)
 332
 333 #define orSISREG(base,val)                              \
 334                 do {                                    \
 335                         u8 __Temp = inSISREG(base);     \
 336                         outSISREG(base, __Temp | (val));\
 337                 } while (0)
 338
 339 #define andSISREG(base,val)                             \
 340                 do {                                    \
 341                         u8 __Temp = inSISREG(base);     \
 342                         outSISREG(base, __Temp & (val));\
 343                 } while (0)
 344
 345 #define inSISIDXREG(base,idx,var)                       \
 346                 do {                                    \
 347                         outSISREG(base, idx);           \
 348                         var = inSISREG((base)+1);       \
 349                 } while (0)
 350
 351 #define outSISIDXREG(base,idx,val)                      \
 352                 do {                                    \
 353                         outSISREG(base, idx);           \
 354                         outSISREG((base)+1, val);       \
 355                 } while (0)
 356
 357 #define orSISIDXREG(base,idx,val)                               \
 358                 do {                                            \
 359                         u8 __Temp;                              \
 360                         outSISREG(base, idx);                   \
 361                         __Temp = inSISREG((base)+1) | (val);    \
 362                         outSISREG((base)+1, __Temp);            \
 363                 } while (0)
 364
 365 #define andSISIDXREG(base,idx,and)                              \
 366                 do {                                            \
 367                         u8 __Temp;                              \
 368                         outSISREG(base, idx);                   \
 369                         __Temp = inSISREG((base)+1) & (and);    \
 370                         outSISREG((base)+1, __Temp);            \
 371                 } while (0)
 372
 373 #define setSISIDXREG(base,idx,and,or)                                   \
 374                 do {                                                    \
 375                         u8 __Temp;                                      \
 376                         outSISREG(base, idx);                           \
 377                         __Temp = (inSISREG((base)+1) & (and)) | (or);   \
 378                         outSISREG((base)+1, __Temp);                    \
 379                 } while (0)
 380
 381 /* MMIO access macros */
 382 #define MMIO_IN8(base, offset)  readb((base+offset))
 383 #define MMIO_IN16(base, offset) readw((base+offset))
 384 #define MMIO_IN32(base, offset) readl((base+offset))
 385
 386 #define MMIO_OUT8(base, offset, val)  writeb(((u8)(val)), (base+offset))
 387 #define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset))
 388 #define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))
 389
 390 /* Queue control MMIO registers */
 391 #define Q_BASE_ADDR             0x85C0  /* Base address of software queue */
 392 #define Q_WRITE_PTR             0x85C4  /* Current write pointer */
 393 #define Q_READ_PTR              0x85C8  /* Current read pointer */
 394 #define Q_STATUS                0x85CC  /* queue status */
 395
 396 #define MMIO_QUEUE_PHYBASE      Q_BASE_ADDR
 397 #define MMIO_QUEUE_WRITEPORT    Q_WRITE_PTR
 398 #define MMIO_QUEUE_READPORT     Q_READ_PTR
 399
 400 #ifndef FB_BLANK_UNBLANK
 401 #define FB_BLANK_UNBLANK        0
 402 #endif
 403 #ifndef FB_BLANK_NORMAL
 404 #define FB_BLANK_NORMAL         1
 405 #endif
 406 #ifndef FB_BLANK_VSYNC_SUSPEND
 407 #define FB_BLANK_VSYNC_SUSPEND  2
 408 #endif
 409 #ifndef FB_BLANK_HSYNC_SUSPEND
 410 #define FB_BLANK_HSYNC_SUSPEND  3
 411 #endif
 412 #ifndef FB_BLANK_POWERDOWN
 413 #define FB_BLANK_POWERDOWN      4
 414 #endif
 415
 416 enum _SIS_LCD_TYPE {
 417     LCD_INVALID = 0,
 418     LCD_800x600,
 419     LCD_1024x768,
 420     LCD_1280x1024,
 421     LCD_1280x960,
 422     LCD_640x480,
 423     LCD_1600x1200,
 424     LCD_1920x1440,
 425     LCD_2048x1536,
 426     LCD_320x240,        /* FSTN */
 427     LCD_1400x1050,
 428     LCD_1152x864,
 429     LCD_1152x768,
 430     LCD_1280x768,
 431     LCD_1024x600,
 432     LCD_320x240_2,      /* DSTN */
 433     LCD_320x240_3,      /* DSTN */
 434     LCD_848x480,
 435     LCD_1280x800,
 436     LCD_1680x1050,
 437     LCD_1280x720,
 438     LCD_1280x854,
 439     LCD_CUSTOM,
 440     LCD_UNKNOWN
 441 };
 442
 443 enum _SIS_CMDTYPE {
 444     MMIO_CMD = 0,
 445     AGP_CMD_QUEUE,
 446     VM_CMD_QUEUE,
 447 };
 448
 449 struct SIS_OH {
 450         struct SIS_OH *poh_next;
 451         struct SIS_OH *poh_prev;
 452         u32            offset;
 453         u32            size;
 454 };
 455
 456 struct SIS_OHALLOC {
 457         struct SIS_OHALLOC *poha_next;
 458         struct SIS_OH aoh[1];
 459 };
 460
 461 struct SIS_HEAP {
 462         struct SIS_OH   oh_free;
 463         struct SIS_OH   oh_used;
 464         struct SIS_OH   *poh_freelist;
 465         struct SIS_OHALLOC *poha_chain;
 466         u32             max_freesize;
 467         struct sis_video_info *vinfo;
 468 };
 469
 470 /* Our "par" */
 471 struct sis_video_info {
 472         int             cardnumber;
 473         struct fb_info  *memyselfandi;
 474
 475         struct SiS_Private SiS_Pr;
 476
 477         struct sisfb_info sisfbinfo;    /* For ioctl SISFB_GET_INFO */
 478
 479         struct fb_var_screeninfo default_var;
 480
 481         struct fb_fix_screeninfo sisfb_fix;
 482         u32             pseudo_palette[16];
 483
 484         struct sisfb_monitor {
 485                 u16 hmin;
 486                 u16 hmax;
 487                 u16 vmin;
 488                 u16 vmax;
 489                 u32 dclockmax;
 490                 u8  feature;
 491                 bool datavalid;
 492         }               sisfb_thismonitor;
 493
 494         unsigned short  chip_id;        /* PCI ID of chip */
 495         unsigned short  chip_vendor;    /* PCI ID of vendor */
 496         char            myid[40];
 497
 498         struct pci_dev  *nbridge;
 499         struct pci_dev  *lpcdev;
 500
 501         int             mni;    /* Mode number index */
 502
 503         unsigned long   video_size;
 504         unsigned long   video_base;
 505         unsigned long   mmio_size;
 506         unsigned long   mmio_base;
 507         unsigned long   vga_base;
 508
 509         unsigned long   video_offset;
 510
 511         unsigned long   UMAsize, LFBsize;
 512
 513         SIS_IOTYPE1     *video_vbase;
 514         SIS_IOTYPE1     *mmio_vbase;
 515
 516         unsigned char   *bios_abase;
 517
 518         int             mtrr;
 519
 520         u32             sisfb_mem;
 521
 522         u32             sisfb_parm_mem;
 523         int             sisfb_accel;
 524         int             sisfb_ypan;
 525         int             sisfb_max;
 526         int             sisfb_userom;
 527         int             sisfb_useoem;
 528         int             sisfb_mode_idx;
 529         int             sisfb_parm_rate;
 530         int             sisfb_crt1off;
 531         int             sisfb_forcecrt1;
 532         int             sisfb_crt2type;
 533         int             sisfb_crt2flags;
 534         int             sisfb_dstn;
 535         int             sisfb_fstn;
 536         int             sisfb_tvplug;
 537         int             sisfb_tvstd;
 538         int             sisfb_nocrt2rate;
 539
 540         u32             heapstart;              /* offset  */
 541         SIS_IOTYPE1     *sisfb_heap_start;      /* address */
 542         SIS_IOTYPE1     *sisfb_heap_end;        /* address */
 543         u32             sisfb_heap_size;
 544         int             havenoheap;
 545
 546         struct SIS_HEAP sisfb_heap;             /* This card's vram heap */
 547
 548         int             video_bpp;
 549         int             video_cmap_len;
 550         int             video_width;
 551         int             video_height;
 552         unsigned int    refresh_rate;
 553
 554         unsigned int    chip;
 555         u8              revision_id;
 556         int             sisvga_enabled;         /* PCI device was enabled */
 557
 558         int             video_linelength;       /* real pitch */
 559         int             scrnpitchCRT1;          /* pitch regarding interlace */
 560
 561         u16             DstColor;               /* For 2d acceleration */
 562         u32             SiS310_AccelDepth;
 563         u32             CommandReg;
 564         int             cmdqueuelength;         /* Current (for accel) */
 565         u32             cmdQueueSize;           /* Total size in KB */
 566
 567         spinlock_t      lockaccel;              /* Do not use outside of kernel! */
 568
 569         unsigned int    pcibus;
 570         unsigned int    pcislot;
 571         unsigned int    pcifunc;
 572
 573         int             accel;
 574         int             engineok;
 575
 576         u16             subsysvendor;
 577         u16             subsysdevice;
 578
 579         u32             vbflags;                /* Replacing deprecated stuff from above */
 580         u32             currentvbflags;
 581         u32             vbflags2;
 582
 583         int             lcdxres, lcdyres;
 584         int             lcddefmodeidx, tvdefmodeidx, defmodeidx;
 585         u32             CRT2LCDType;            /* defined in "SIS_LCD_TYPE" */
 586         u32             curFSTN, curDSTN;
 587
 588         int             current_bpp;
 589         int             current_width;
 590         int             current_height;
 591         int             current_htotal;
 592         int             current_vtotal;
 593         int             current_linelength;
 594         __u32           current_pixclock;
 595         int             current_refresh_rate;
 596
 597         unsigned int    current_base;
 598
 599         u8              mode_no;
 600         u8              rate_idx;
 601         int             modechanged;
 602         unsigned char   modeprechange;
 603
 604         u8              sisfb_lastrates[128];
 605
 606         int             newrom;
 607         int             haveXGIROM;
 608         int             registered;
 609         int             warncount;
 610 #ifdef SIS_OLD_CONFIG_COMPAT
 611         int             ioctl32registered;
 612 #endif
 613
 614         int             sisvga_engine;
 615         int             hwcursor_size;
 616         int             CRT2_write_enable;
 617         u8              caps;
 618
 619         u8              detectedpdc;
 620         u8              detectedpdca;
 621         u8              detectedlcda;
 622
 623         SIS_IOTYPE1     *hwcursor_vbase;
 624
 625         int             chronteltype;
 626         int             tvxpos, tvypos;
 627         u8              p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02;
 628         int             tvx, tvy;
 629
 630         u8              sisfblocked;
 631
 632         struct sisfb_info sisfb_infoblock;
 633
 634         struct sisfb_cmd sisfb_command;
 635
 636         u32             sisfb_id;
 637
 638         u8              sisfb_can_post;
 639         u8              sisfb_card_posted;
 640         u8              sisfb_was_boot_device;
 641
 642         struct sis_video_info *next;
 643 };
 644
 645 #endif